CN101488476A - Encapsulation method - Google Patents
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- CN101488476A CN101488476A CNA2009100468932A CN200910046893A CN101488476A CN 101488476 A CN101488476 A CN 101488476A CN A2009100468932 A CNA2009100468932 A CN A2009100468932A CN 200910046893 A CN200910046893 A CN 200910046893A CN 101488476 A CN101488476 A CN 101488476A
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Abstract
The invention provides an encapsulation method, comprising the following steps: forming a plurality of cavity walls on a substrate; forming a notch between the cavity walls on the side where the cavity walls are formed; the cavity wall and a wafer where a semiconductor device is provided are agglutinated; the substrate is cut at the notch. Compared with the prior art, first, the notch is formed between the cavity walls at one side where the cavity walls are formed, namely, the substrate is thinned at the position where the substrate is to be separated, so that the lower surface of the substrate is far away from a weld pad, therefore, the weld pad is not harmed in the follow-up process of separating the substrate.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor device, relate in particular to a kind of method for packing.
Background technology
Optical sensor chip has very high requirement to environment cleanliness, therefore in the process that it is encapsulated, need avoid it to be exposed to the environment that is full of dust as much as possible, thereby reduces extraneous dust and foreign matter intrusion and attached work on optical sensor chip.
Encapsulation technology for optical sensor chip has a variety of at present, chip on board (Chip onBoard wherein, COB) encapsulation technology is because the properties of product of its encapsulation are reliable and stable, the integrated level height, small product size after the encapsulation is little, and ease for use is strong, and product process flow is simple, low or the like the series of advantages of the cost of encapsulation is widely used a kind of in the optical current sensor Chip Packaging.
As shown in Figure 1, COB encapsulation is to adopt bonding agent or methods such as tape welding, wire bond, flip chip bonding automatically, optical sensor chip 101 directly is mounted on the circuit board 102, realizes being electrically connected of tie point 104 on weld pad 103 and the circuit board 102 on the optical sensor chip 101 by Wire Bonding Technology again.Do not isolate because optical sensor chip 101 has protected device in the COB encapsulation process, therefore in the COB of optical sensor chip encapsulation process, cause chip to pollute easily.About COB encapsulation, can in Chinese invention patent application 200710180151.X number, find more information.
Based on advantage and the existing shortcoming thereof of COB encapsulation technology in the optical sensor chip encapsulation, industry has been developed a kind of new packaged type for optical sensor chip.Promptly as shown in Figure 2, utilize transparency carrier 203 to protect earlier the light-sensitive area 202 of optical sensor chip 201, utilize the COB encapsulation technology to encapsulate afterwards again.This kind method can be avoided in the traditional C OB encapsulation process directly cutting crystal wafer to greatest extent and directly not protected optical sensor chip be mounted the dust foreign substance pollution that is caused thereafter, has improved the encapsulation yield greatly.And this first mounted substrate 203 is cut into wafer the method for monolithic again, and (Wafer Level Chip SizePackaging, WLCSP) technology improves packaging efficiency can to introduce the crystal wafer chip dimension encapsulation.So-called crystal wafer chip dimension encapsulation is that the full wafer wafer is carried out cutting the technology that obtains single finished chip again after the packaging and testing, and the chip size after the encapsulation is consistent with nude film.The cost of WLCSP encapsulation with the increase of wafer size and chip size reduce present bright advantage, complied with that market is light day by day, little, short to microelectronic product, thinning and low priceization requirement.
But, owing to be cut into single after substrate integral body that the formed substrate 203 of use crystal wafer chip dimension encapsulation technology is wafer sizes and wafer are bonding again, and the weld pad 204 of optical sensor chip 201 is positioned at outside the substrate 203, therefore, when carrying out substrate 203 cutting and separating, the weld pad 204 to chip 201 causes damage easily.
Summary of the invention
Technical problem to be solved by this invention is: how in the process of minute cutting board, prevent that weld pad is impaired.
For addressing the above problem, according to an aspect of the present invention, provide a kind of method for packing, comprise step: on substrate, form a plurality of cavity walls; Be formed with at substrate on the side of cavity wall, the position between the cavity wall forms groove; The one side that is shaped on semiconductor device on cavity wall and the wafer is bonding; Substrate is cut apart at described groove.
Alternatively, the chip of being made up of described semiconductor device comprises weld pad, described with the one side that is shaped on semiconductor device on cavity wall and the wafer bonding after, described weld pad is between cavity wall.
Alternatively, described substrate is specially in the step that described groove is cut apart on the opposite face of the one side that is formed with cavity wall from described substrate, described substrate is cut to cutting apart described substrate fully in the position of groove correspondence.
Alternatively, the described step that substrate is cut apart at described groove is to be thinned to the described groove of exposure by the opposite face that described substrate is formed with the one side of cavity wall to realize.
Alternatively, the material that forms described substrate is selected from unorganic glass or polymethyl methacrylate.
Alternatively, the described cavity wall side's of being annular or annular.
Alternatively, the degree of depth of described groove is less than 2/3 of described substrate thickness.
Alternatively, described semiconductor device comprises optical pickocff or optical-electrical converter.
According to another aspect of the present invention, provide a kind of method for packing, comprise step: substrate is provided, and described substrate is bonded by adhesive layer by upper substrate and infrabasal plate; On infrabasal plate, form a plurality of cavity walls; Be formed with at infrabasal plate on the side of cavity wall, the position between the cavity wall forms groove; The one side that is shaped on semiconductor device on cavity wall and the wafer is bonding; Remove upper substrate; Infrabasal plate is cut apart at described groove.
Alternatively, the chip of being made up of described semiconductor device comprises weld pad, described with the one side that is shaped on semiconductor device on cavity wall and the wafer bonding after, described weld pad is between cavity wall.
Alternatively, the material of described adhesive layer is selected from photoresist or ultraviolet cured adhesive.
Alternatively, described groove exposes described adhesive layer, and the described step that infrabasal plate is cut apart at described groove is to realize by separating upper substrate.
Alternatively, described infrabasal plate is specially in the step that described groove is cut apart: be formed with from described infrabasal plate on the opposite face of one side of cavity wall, described infrabasal plate is cut to cutting apart described infrabasal plate fully in the position of groove correspondence.
Alternatively, the described step that infrabasal plate is cut apart at described groove is to be thinned to the described groove of exposure by the opposite face that described infrabasal plate is formed with the one side of cavity wall to realize.
Alternatively, the material that forms described infrabasal plate is a glass, and the material that forms described upper substrate is selected from metal, glass, pottery, rubber or plastics.
Alternatively, the described cavity wall side's of being annular or annular.
Alternatively, the degree of depth of described groove is less than 2/3 of described infrabasal plate thickness.
Alternatively, described semiconductor device comprises optical pickocff or optical-electrical converter.
Compared with prior art, the present invention earlier forms groove in the position that substrate forms between the side upper plenum wall of cavity wall, promptly at the position attenuate substrate of predetermined separating base plate, makes the lower surface of substrate away from weld pad, thereby in the process of later separation substrate, can not damage weld pad.
Description of drawings
Fig. 1 is a kind of optical chip encapsulating structure schematic diagram in the prior art;
Fig. 2 is an another kind of optical chip encapsulating structure schematic diagram in the prior art;
Fig. 3 is an one embodiment of the invention method for packing flow chart;
The schematic diagram of Fig. 4 to Fig. 8 for encapsulating according to flow process shown in Figure 3;
Fig. 9 is an another embodiment of the present invention method for packing flow chart;
The schematic diagram of Figure 10 to Figure 13 for encapsulating according to flow process shown in Figure 9.
Embodiment
Embodiment 1
As shown in Figure 3, present embodiment provides a kind of method for packing, comprises step:
S301 forms a plurality of cavity walls on substrate;
S302, the position that is formed with at substrate between the side upper plenum wall of cavity wall forms groove;
S303, the one side that is shaped on semiconductor device on cavity wall and the wafer is bonding;
S304 is cut apart substrate at described groove.
Be elaborated below in conjunction with accompanying drawing.
And then on substrate 401, form a plurality of cavity walls 402.The method that forms cavity wall 402 has multiple, the method that substrate 401 is carried out photoetching for example, i.e. first spin coating photoresist on substrate 401, method by exposure, development etches the cavity wall 402 that thickness is about 10 μ m to 200 μ m on substrate 401 again, form structure as shown in Figure 4, completing steps S301.Certainly, also can directly the cavity wall of making 402 be bonded on the substrate 401, also can performing step S301.
Because the present invention can be in conjunction with the method for crystal wafer chip dimension encapsulation, therefore, can be at the suitable and corresponding cavity wall 402 in position of number of chips that forms on the substrate 401 of a wafer size on a plurality of and the wafer, as shown in Figure 5.
The side's of being shaped as annular of cavity wall 402 can be an annular as shown in Figure 5, also can be annular, certainly, also can be other annulars.The shape of cavity wall 402 can be selected according to the encapsulation needs of reality.
Execution in step S302 as shown in Figure 6, forms on the side of cavity wall 402 at substrate 401 then, forms groove 403, the position of this groove between cavity wall 402.As described in summary of the invention, the present invention position between a side upper plenum wall 402 of substrate 401 formation cavity walls 402 earlier forms groove 403, promptly at the position attenuate substrate 401 of being scheduled to separating base plate 401, make the lower surface of substrate 401 away from weld pad 405 (with reference to figure 7), thereby in the process of later separation substrate 401, can not damage weld pad 405.Therefore, the degree of depth of groove 403 should be the bigger the better.But along with the increase of groove 403 degree of depth, the mechanical strength of substrate 401 reduces, and is dark excessively as the degree of depth of figure groove 403, will cause in manufacture process, and substrate 401 ruptures voluntarily, and this will cause the encapsulation failure.
The method of formation groove 403 has multiple, comprises mechanical means and chemical method.Mechanical means is to utilize cutting knife, carries out the part cutting as the diamond rotary cutter from the position between the side upper plenum wall 402 of substrate 401 formation cavity walls 402, to form groove 403.Chemical method is elder generation's spin coating photoresist on substrate 401, and the method by exposure, development etches groove 403 on substrate 401 again.The concrete technology of these two kinds of methods is well known to those skilled in the art, does not repeat them here.
In an embodiment shown in Figure 6, the width of groove 403 is identical with spacing between the cavity wall 402, and this only is an example.The width of groove 403 can as long as the width of groove 403 can guarantee to expose weld pad 405 in subsequent technique, just can be realized purpose of the present invention less than the spacing between the cavity wall 402.
Execution in step S303 is as shown in Figure 7, bonding with the one side that is shaped on semiconductor device 404 on cavity wall 402 and the wafer 406 then.Here saidly bondingly specifically can be: forming one deck adhesive layer (figure does not show) by methods such as plastic rolls on away from the one side of substrate 401 on the cavity wall 402 earlier; The one side that then cavity wall 402 is scribbled adhesive layer and wafer 406 are shaped on the one side pressing of semiconductor device 404, make semiconductor device 404 fall in the space that toroidal cavity wall 402 surrounded, and make and also promptly make weld pad 405 fall into groove 403 pairing positions in the space of weld pad 405 between two cavity walls 402.Bonding like this result makes the semiconductor device 404 that needs protection fall in the confined space that itself is surrounded by substrate 401, cavity wall 402 and wafer 406, thereby has played the effect of encapsulated semiconductor device 404.And, be used to carry out the weld pad 405 that external electric connects and be positioned at outside this cavity, can conveniently carry out follow-up connection technology.Semiconductor device wherein can for example be an optical pickocff.
Follow execution in step S304 again, as shown in Figure 8, substrate 401 is cut apart at groove 403 places.The concrete grammar of in this step substrate 401 being cut apart has two kinds at least, the method that the first is directly cut apart for example uses cutting tool to be formed with the position cutting substrate 401 of opposite face of one side of cavity wall 402 from the substrate 401 of groove 403 correspondences to dividing cutting board 401 fully.Because the existence of groove 403, make cutting tool in the whole process of separating base plate 401 all away from weld pad 405, thereby protection weld pad 405 is injury-free in the process of minute cutting board 401.Certainly, using cutter to cut apart only is a kind of of direct dividing method, for example at groove 403 places substrate 401 is carried out methods such as photoetching, also can play the effect of direct minute cutting board 401, does not repeat them here.
Except that directly cutting apart, another method of dividing cutting board 401 is that the opposite face that is formed with the one side of cavity wall 402 on substrate 401 is thinned to exposure weld pad 405 to whole base plate, be thinned to the bottom of groove 403 in other words, equally also can realize the effect of branch cutting board 401.
Embodiment 2
As shown in Figure 9, present embodiment provides a kind of method for packing, comprises step:
S501 forms a plurality of cavity walls on infrabasal plate;
S502, upper substrate and infrabasal plate is bonding;
S503, the position between a side upper plenum wall of infrabasal plate formation cavity wall forms groove;
S504, the one side that is shaped on semiconductor device on cavity wall and the wafer is bonding;
S505 removes upper substrate, cuts apart infrabasal plate.
Be elaborated below in conjunction with accompanying drawing.
At first execution in step S501 forms a plurality of cavity walls 604 on infrabasal plate 601, forms structure as shown in figure 10.The material of making infrabasal plate 601 should satisfy the demand of package strength at least.And when packaged object for example was optical sensor chip such as image chip, the material of making infrabasal plate 601 for example can be a glass, comprised inorganic silicate glass or polymethyl methacrylate such as polymethyl methacrylate for example.The method that forms cavity wall 604 has multiple, the method that infrabasal plate 601 is carried out photoetching for example, i.e. and spin coating photoresist on infrabasal plate 601 earlier etches the cavity wall 604 that thickness is about 10 μ m to 200 μ m by exposure, the method for developing again on infrabasal plate 601.Certainly, directly the cavity wall of making 604 is bonded on the infrabasal plate 601, also can performing step S501.
Similar to embodiment 1, for realizing the application of crystal wafer chip dimension encapsulation, can be at the suitable and corresponding cavity wall 604 in position of number of chips that forms on the infrabasal plate 601 of a wafer size on a plurality of and the wafer.
Execution in step S502 is bonding by adhesive 603 with infrabasal plate 601 and upper substrate 602 then, forms structure as shown in figure 11.The thickness of infrabasal plate 601 and upper substrate 602 can be selected according to the structural strength etc. of encapsulation, for example can be approximately all thickness of 100 μ m to 1000 μ m.
Because upper substrate 602 mainly plays the effect of support, the selection of the manufactured materials of institute's above substrate 602 mainly should be considered mechanical strength.Therefore, the material of formation upper substrate 602 can be selected from metal, glass, pottery, rubber or plastics.
Because subsequent step will separate upper substrate 602, so the adhesive 603 of bonding upper substrate 602 and infrabasal plate 601 should be can the bonding adhesive of reverse releasing, for example can be photoresist or ultraviolet cured adhesive.Photoresist can realize that releasing is bonding by exposure and the method for developing, and ultraviolet cured adhesive can be realized bonding by the method for UV-irradiation and remove bonding by the method realization of heating.
Here it should be noted that the order between step S501 and the step S502 is not inventive point of the present invention place, one skilled in the art will appreciate that the order of step S501 and step S502 is changed, can realize purpose of the present invention equally.
Follow execution in step S503, as shown in figure 12, the position between a side upper plenum wall 604 of infrabasal plate 601 formation cavity walls 604 forms groove 605.Groove 605 herein equals the thickness of infrabasal plate 601 at least, thereby blocks infrabasal plate 601 fully.The degree of depth of groove 605 shown in Figure 12 equals the thickness of infrabasal plate 601 just and the situation that arrives adhesive layer 603 only is an example, and the degree of depth that continues to increase groove 605 also can realize purpose of the present invention to going deep into upper substrate 602 inside.
The method that forms groove 605 has multiple, carries out part and is cut to and exposes adhesive layer 603 as using the diamond rotary cutter to be formed with position between the side upper plenum wall 604 of cavity wall 604 from infrabasal plate 601, with formation groove 605.Or elder generation's spin coating photoresist on infrabasal plate 601, the method by exposure, development etches the groove 605 that exposes adhesive layer 603 on infrabasal plate 601 again.
Similar to embodiment 1, the width of groove 605 can as long as the width of groove 605 can guarantee to expose weld pad 608 (with reference to Figure 13) in subsequent technique, just can be realized purpose of the present invention less than the spacing between the cavity wall 604.
Execution in step S504 is as shown in figure 13, bonding with the one side that is shaped on semiconductor device 607 on cavity wall 604 and the wafer 606 then.Here saidly bondingly specifically can be: forming one deck adhesive layer (figure does not show) by methods such as plastic rolls on away from the one side of infrabasal plate 601 on the cavity wall 604 earlier; The one side that then cavity wall 604 is scribbled adhesive layer and wafer 606 are shaped on the one side pressing of semiconductor device 607, make semiconductor device 607 fall in the space that toroidal cavity wall 604 surrounded, and make and also promptly make weld pad 608 fall into groove 605 pairing positions in the space of weld pad 608 between cavity wall 604 and cavity wall 604.Make the semiconductor device 607 that needs protection fall in the confined space that itself is surrounded by infrabasal plate 601, cavity wall 604 and wafer 606, thereby played the effect of encapsulated semiconductor device 607.And, be used to carry out the weld pad 608 that external electric connects and be positioned at outside this confined space, can conveniently carry out follow-up connection technology.
Follow execution in step S505 again, remove upper substrate 602, cut apart infrabasal plate 601.In step S505, just can remove upper substrate 602 as long as remove the viscosity of adhesive layer 603, as previously mentioned, can adopt corresponding method to remove viscosity according to the adhesive layer 603 of different materials.Because when step S503 forms groove 605, the degree of depth of groove 605 has arrived adhesive layer 603, also promptly infrabasal plate 601 is cut apart, just the existence owing to adhesive layer 603 and upper substrate 602 makes infrabasal plate 601 remain an integral body, therefore, after the substrate 602, infrabasal plate 601 has just separated naturally in separation.Separated upper substrate 602 can be reused, and this also is an advantage of present embodiment.
In embodiment 2, the degree of depth of groove 605 is more than or equal to the thickness of infrabasal plate 601, but the invention is not restricted to this.When the degree of depth of groove 605 during less than the thickness of infrabasal plate 601, after removing upper substrate 602, just formed structure as shown in Figure 7, therefore the follow-up embodiment 1 described method that can adopt is cut apart infrabasal plate 601.So also can realize purpose of the present invention.In this case, upper substrate 602 just plays the effect of the mechanical strength that increases infrabasal plate 601 fully.
Certainly, those skilled in the art know that also the described method for packing of the foregoing description is not limited to the encapsulation of optical chip or optical-electrical converter.If desired, also can encapsulate the chip that other need mechanical protection, for example need carry out sealing protection chip of micro-electro-mechanical system encapsulation or need the encapsulation etc. of the chip of mechanical protection.In this case, also can use nontransparent material to make substrate.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (18)
1. a method for packing is characterized in that, comprises step:
On substrate, form a plurality of cavity walls;
Be formed with at substrate on the side of cavity wall, the position between the cavity wall forms groove;
The one side that is shaped on semiconductor device on cavity wall and the wafer is bonding;
Substrate is cut apart at described groove.
2. method for packing as claimed in claim 1 is characterized in that: the chip of being made up of described semiconductor device comprises weld pad, described with the one side that is shaped on semiconductor device on cavity wall and the wafer bonding after, described weld pad is between cavity wall.
3. method for packing as claimed in claim 1, it is characterized in that: described substrate is specially in the step that described groove is cut apart on the opposite face of the one side that is formed with cavity wall from described substrate, described substrate is cut to cutting apart described substrate fully in the position of groove correspondence.
4. method for packing as claimed in claim 1 is characterized in that: the described step that substrate is cut apart at described groove is to be thinned to the described groove of exposure by the opposite face that described substrate is formed with the one side of cavity wall to realize.
5. method for packing as claimed in claim 1 is characterized in that: the material that forms described substrate is selected from unorganic glass or polymethyl methacrylate.
6. method for packing as claimed in claim 1 is characterized in that: the described cavity wall side's of being annular or annular.
7. method for packing as claimed in claim 1 is characterized in that: the degree of depth of described groove is less than 2/3 of described substrate thickness.
8. method for packing as claimed in claim 1 is characterized in that: described semiconductor device comprises optical pickocff or optical-electrical converter.
9. a method for packing is characterized in that, comprises step:
Substrate is provided, and described substrate is bonded by adhesive layer by upper substrate and infrabasal plate;
On infrabasal plate, form a plurality of cavity walls;
Be formed with at infrabasal plate on the side of cavity wall, the position between the cavity wall forms groove;
The one side that is shaped on semiconductor device on cavity wall and the wafer is bonding;
Remove upper substrate;
Infrabasal plate is cut apart at described groove.
10. method for packing as claimed in claim 9 is characterized in that: the chip of being made up of described semiconductor device comprises weld pad, described with the one side that is shaped on semiconductor device on cavity wall and the wafer bonding after, described weld pad is between cavity wall.
11. method for packing as claimed in claim 9 is characterized in that: the material of described adhesive layer is selected from photoresist or ultraviolet cured adhesive.
12. as claim 9 or 11 described method for packing, it is characterized in that: described groove exposes described adhesive layer, the described step that infrabasal plate is cut apart at described groove is to realize by separating upper substrate.
13. method for packing as claimed in claim 9, it is characterized in that, described infrabasal plate is specially in the step that described groove is cut apart: be formed with from described infrabasal plate on the opposite face of one side of cavity wall, described infrabasal plate is cut to cutting apart described infrabasal plate fully in the position of groove correspondence.
14. method for packing as claimed in claim 9 is characterized in that: the described step that infrabasal plate is cut apart at described groove is to be thinned to the described groove of exposure by the opposite face that described infrabasal plate is formed with the one side of cavity wall to realize.
15. method for packing as claimed in claim 9 is characterized in that: the material that forms described infrabasal plate is a glass, and the material that forms described upper substrate is selected from metal, glass, pottery, rubber or plastics.
16. method for packing as claimed in claim 9 is characterized in that: the described cavity wall side's of being annular or annular.
17. method for packing as claimed in claim 9 is characterized in that: the degree of depth of described groove is less than 2/3 of described infrabasal plate thickness.
18. method for packing as claimed in claim 9 is characterized in that: described semiconductor device comprises optical pickocff or optical-electrical converter.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009100468932A CN101488476B (en) | 2009-02-25 | 2009-02-25 | Encapsulation method |
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| CN2009100468932A CN101488476B (en) | 2009-02-25 | 2009-02-25 | Encapsulation method |
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| CN101488476A true CN101488476A (en) | 2009-07-22 |
| CN101488476B CN101488476B (en) | 2011-06-22 |
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| CN2009100468932A Active CN101488476B (en) | 2009-02-25 | 2009-02-25 | Encapsulation method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102024649A (en) * | 2009-12-31 | 2011-04-20 | 四川虹欧显示器件有限公司 | Plasma display screen and manufacture method thereof |
| CN102280391A (en) * | 2011-09-01 | 2011-12-14 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and formation method thereof |
| CN102464293A (en) * | 2010-11-04 | 2012-05-23 | 无锡华润安盛科技有限公司 | Capping assisting device |
| CN103487175A (en) * | 2013-09-02 | 2014-01-01 | 无锡慧思顿科技有限公司 | Method for manufacturing pressure sensor packaged by plastic |
| CN103698968A (en) * | 2013-12-10 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Photoresistance wall forming method |
| CN103728830A (en) * | 2013-12-10 | 2014-04-16 | 华进半导体封装先导技术研发中心有限公司 | Modular molding method for light resistance wall structure |
| CN106206328A (en) * | 2016-07-27 | 2016-12-07 | 桂林电子科技大学 | A kind of manufacture method imbedding Chip package substrate |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1450651A (en) * | 2003-05-15 | 2003-10-22 | 王鸿仁 | Image sensor package structure and image taking module using said sensor |
| US6905910B1 (en) * | 2004-01-06 | 2005-06-14 | Freescale Semiconductor, Inc. | Method of packaging an optical sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024649A (en) * | 2009-12-31 | 2011-04-20 | 四川虹欧显示器件有限公司 | Plasma display screen and manufacture method thereof |
| CN102464293B (en) * | 2010-11-04 | 2014-09-03 | 无锡华润安盛科技有限公司 | Capping assisting device |
| CN102464293A (en) * | 2010-11-04 | 2012-05-23 | 无锡华润安盛科技有限公司 | Capping assisting device |
| CN102280391A (en) * | 2011-09-01 | 2011-12-14 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and formation method thereof |
| CN102280391B (en) * | 2011-09-01 | 2013-05-08 | 苏州晶方半导体科技股份有限公司 | Wafer level package structure and formation method thereof |
| CN103487175A (en) * | 2013-09-02 | 2014-01-01 | 无锡慧思顿科技有限公司 | Method for manufacturing pressure sensor packaged by plastic |
| CN103487175B (en) * | 2013-09-02 | 2015-09-30 | 无锡慧思顿科技有限公司 | A kind of manufacture method of pressure sensor of Plastic Package |
| CN103728830A (en) * | 2013-12-10 | 2014-04-16 | 华进半导体封装先导技术研发中心有限公司 | Modular molding method for light resistance wall structure |
| CN103698968A (en) * | 2013-12-10 | 2014-04-02 | 华进半导体封装先导技术研发中心有限公司 | Photoresistance wall forming method |
| CN103698968B (en) * | 2013-12-10 | 2017-01-25 | 华进半导体封装先导技术研发中心有限公司 | Photoresistance wall forming method |
| CN103728830B (en) * | 2013-12-10 | 2017-02-01 | 华进半导体封装先导技术研发中心有限公司 | Modular molding method for light resistance wall structure |
| CN106206328A (en) * | 2016-07-27 | 2016-12-07 | 桂林电子科技大学 | A kind of manufacture method imbedding Chip package substrate |
| CN106206328B (en) * | 2016-07-27 | 2018-12-18 | 桂林电子科技大学 | A kind of production method being embedded to Chip package substrate |
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|---|---|
| CN101488476B (en) | 2011-06-22 |
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