CN101483980A - Combined surface processing method for firm-flexible combined circuit board - Google Patents
Combined surface processing method for firm-flexible combined circuit board Download PDFInfo
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- CN101483980A CN101483980A CNA2009101050098A CN200910105009A CN101483980A CN 101483980 A CN101483980 A CN 101483980A CN A2009101050098 A CNA2009101050098 A CN A2009101050098A CN 200910105009 A CN200910105009 A CN 200910105009A CN 101483980 A CN101483980 A CN 101483980A
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- coverlay
- circuit board
- scratch
- processing method
- vacuum chamber
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Abstract
The invention provides a method for combining surface treating to a rigidity-flexibility combination circuit board which includes a process for plasma etching to a coat film on the flexibility board inner layer surface. The method can increase peeling-off intension of the rigidity-flexibility combination circuit board obviously, solve difficult problem that the rigidity-flexibility combination circuit board is easy to layered in poor condition; the plasma etching process processes micro-etch and roughening to the coat film surface that has little effect to the flexible circuit board size stability and does not effect the flexible circuit board appearance, especially is suitable for conditions of the flexible circuit board having golden finger and the rigidity-flexibility combination circuit board having large exposed area of the flexible circuit board; the method has little effect to the coat film appearance; the producing process is clean and has no pollution.
Description
[technical field]
The present invention relates to the wiring board manufacturing technology, especially a kind ofly strengthened just-scratched the slight surface treatment method of combination of combined circuit board.
[background technology]
Just-scratch combined circuit board to combine by rigidity wiring board and flex circuit application.In the manufacturing process, after finishing circuit on the flex circuit application and laying, the coverlay of fitting on the one side of rigidity wiring board at flex circuit application combines rigidity wiring board and flex circuit application then.For improve rigidity wiring board and flex circuit application in conjunction with effect, strengthened just-scratched combined circuit board adhesion, prevent layering and foaming, rigidity wiring board and flex circuit application in conjunction with before to handle the surface towards the rigidity wiring board of coverlay earlier.Coverlay surface treatment method of the prior art has nog plate, chemical cleaning and sandblast.Nog plate is to adopt the mode of mechanical grinding that brushing is carried out on the surface of coverlay, to play cleaning action and to make the coverlay surface form certain matsurface; Chemical cleaning is to utilize chemical medicinal liquid that the greasy dirt of removing the coverlay surface is cleaned on the coverlay surface, improves the surface cleanliness of its pressing; Sandblast is with mainly by AL
2O
3And SiO
2Forming molecule (about diameter 20-30um) mixes with water, high-pressure injection is to the coverlay surface when stirring into suspended state, utilize the high rigidity of this molecule under the situation of high pressure, the coverlay surface to be clashed into, thereby make its surface form certain scraggly matsurface.The treatment effect of this several method is not very good.
[summary of the invention]
Technical problem to be solved by this invention provides a kind of slight surface treatment method of combination of combined circuit board that strengthened just-scratched.
For solving the problems of the technologies described above, the invention provides a kind of just-scratch the mating surface processing method of combined circuit board, comprise that the coverlay to flex plate internal layer surface carries out the process of plasma etching.Here said flex plate internal layer surface is meant the one side towards the rigidity wiring board of flex circuit application, and coverlay is fitted on the flex plate internal layer surface.The inventive method adopts plasma etching, plasma carries out etchback and ion bombardment to the coverlay surface, make the coverlay surface reach " coarse " degree in the molecular level scope, thereby change its surperficial adhesion properties, made just-scratch combined circuit board and have higher binding strength.
On this basis, further:
The process of flex plate internal layer surface coverlay being carried out plasma etching may further comprise the steps:
A. coverlay or the flex plate that posts coverlay are placed in the vacuum chamber;
B. charge into etching gas in vacuum chamber, and the etching gas in the vacuum chamber is loaded electromagnetic field so that etching gas produces plasma, plasma carries out etch processes to the faying face of flex plate internal layer surface coverlay;
The faying face of the coverlay among the step b is meant the surface that combines with rigid plate of coverlay.
Adopt the inventive method, can after coverlay is fitted on the flex circuit application, carry out etch processes by the faying face to coverlay, the faying face of coverlay and rigidity circuit are hardened close again; Also can be earlier the faying face of coverlay be carried out etch processes, again coverlay and flex circuit application, rigidity circuit are hardened and close.
Used etching gas is N among the step b
2, CF
4And O
2In one or more combination.Etching gas can adopt a kind of gas, also can adopt the mist of two or more gas composition.
A kind of embodiment of step b comprises following process: carry out following four-stage under the situation that the etching gas in the vacuum chamber is loaded electromagnetic field: the phase I, the etching gas in the vacuum chamber is N
2Gas was handled 3-15 minute; Second stage, the etching gas in the vacuum chamber are CF
4And O
2Two kinds of gases were handled 10-50 minute; Phase III, the etching gas in the vacuum chamber is O
2Gas was handled 5-15 minute; Quadravalence section, the etching gas in the vacuum chamber are N
2Gas was handled 3-10 minute.
In order to guarantee the good binding effect, after step b finishes, through the coverlay of etch processes in 6 hours with the rigid plate pressing.
In order to get rid of foreign matter, the faying face to coverlay before etching cleans and drying; With etch processes after the coverlay pressing before, the faying face of rigidity wiring board is cleaned and dry.The faying face of rigidity wiring board be meant rigid plate with cover membrane-bound surface.
The invention has the beneficial effects as follows: can obviously improve just-scratch the peel strength of combined circuit board, solve just-scratched the difficult problem of combined circuit board easy layering under mal-condition; Etch processes is that microetch and alligatoring are carried out in the coverlay surface, dimensional stability influence to flex circuit application is less, can not influence the outward appearance of flex circuit application, especially be fit to have on the flex circuit application golden finger and just-the scratch situation that the flex circuit application large tracts of land exposes in the combined circuit board; Appearance effects to coverlay is less; The production process cleaning, pollution-free.
[description of drawings]
Below by embodiment also in conjunction with the accompanying drawings, the present invention is described in further detail:
Fig. 1 is the schematic flow sheet of a kind of embodiment of the present invention.
[embodiment]
Embodiment one
The process of making just-scratching combined circuit board in the present embodiment as shown in Figure 1.The material of the used flex plate of present embodiment is a 1mil PI thickness, and 10Z copper is thick, two-sided no glue cathode copper; The material of rigid plate is FR4, the thick 1/2OZ of copper (not cupric), gross thickness 0.2mm, TG 〉=170 ℃, the yellow material of no word; The material of coverlay is polyimides (PI).The detailed process of making just-scratching combined circuit board is as follows:
1. flex plate is opened material: the size according to design is prepared the flex plate blank;
Internal layer circuit: on the flex plate blank, lay circuit;
Internal layer pastes epiphragma: at the flex circuit application coverlay of fitting on the one side of rigidity wiring board
Plasma etching: flex plate is lain on the pallet in the plasma machine process chamber, shut vacuum chamber, enter the back by the normal boot-strap program and handle by following plasma etching parameter:
Phase I only charges into N2 gas, power 3000W, and flow 250cc/min handled 3 minutes;
Second stage charges into CF4+O2, power 3000W, and flow 80+160cc/min handled 10 minutes;
Phase III charges into O2 gas, power 3000W, and flow 250cc/min handled 5 minutes;
The quadravalence section charges into N2 gas, power 3000W, and flow 250cc/min handled 3 minutes.
In plasma etch processes, in the vacuum electric field environment, the plasma (active group) that etching gas produces high etching intensity carries out etchback and ion bombardment to coverlay (PI) surface, make coverlay (PI) surface form molecular level scope interior " coarse ", thereby change its surperficial adhesion properties.
2. rigid plate is opened material: the size according to design is prepared the rigid plate blank;
Outer-layer circuit: on the rigid plate blank, lay circuit;
3. just-and scratch applying: rigid plate and flex plate are fitted, and the faying face of coverlay contacts with rigid plate;
4. pressing: use that vacuum pressure transmission machine pressing step 3 obtains just-scratch jointing plate, the pressing parameter is: 140 ℃ * 100PSI * 15MIN, suppress simultaneously in vacuum pressure transmission machine that 6 steps 3 obtain just-scratch jointing plate, the lamination mode is as follows:
5. solidify the compacting back: 160 ℃ * 60MIN
Adopt above method finally to make just-scratched combined circuit board.In the said method, except that plasma etch processes, other process all can adopt manufacturing process of the prior art.
Embodiment two
Present embodiment only is to have adopted different plasma etching parameters with the difference of embodiment one:
Phase I only charges into N2 gas, power 3800W, and flow 320cc/min handled 8 minutes;
Second stage charges into CF4+O2, power 3800W, and flow 100+200cc/min handled 30 minutes;
Phase III charges into O2 gas, power 3800W, and flow 320cc/min handled 8 minutes;
The quadravalence section charges into N2 gas, power 3800W, and flow 320cc/min handled 6 minutes.
Embodiment three
Present embodiment only is to have adopted different plasma etching parameters with the difference of embodiment one:
Phase I only charges into N2 gas, power 4500W, and flow 400cc/min handled 15 minutes;
Second stage charges into CF4+O2, power 4500W, and flow 120+240cc/min handled 50 minutes;
Phase III charges into O2 gas, power 4500W, and flow 400cc/min handled 15 minutes;
The quadravalence section charges into N2 gas, power 4500W, and flow 400cc/min handled 10 minutes.
Comparative Examples one (sandblast)
The difference of this Comparative Examples and embodiment one only is: embodiment one adopts plasma etching method that the faying face of coverlay is handled, and this Comparative Examples usage level sand-blasting machine carries out blasting treatment: AL to the faying face of coverlay by following condition
2O
3Concentration 10%, sandblast speed 1.8m/min, on spray pressure 1.0kg/cm
2, following spray pressure 1.2kg/cm
2The back usage level of finishing dealing with is washed the plate machine and is cleaned condition: pickling concentration 2.5%, on spray pressure 1.2kg/cm
2, following spray pressure 1.2kg/cm
2, speed 1.8m/min, 85 ℃ of bake out temperatures.
Comparative Examples two (nog plate)
This Comparative Examples only is with the difference of embodiment one: embodiment one adopts plasma etching method that the faying face of coverlay is handled, and this Comparative Examples usage level Plate grinder carries out nog plate to the faying face of coverlay by following condition and handles: polish-brush electric current 2.9A, nog plate speed 1.8m/min, polish-brush order several 500
#, 800
#, polishing scratch requires 10～20mm.The back usage level of finishing dealing with is washed the plate machine and is cleaned condition: pickling concentration 2.5%, on spray pressure 1.2kg/cm
2, following spray pressure 1.2kg/cm
2, speed 1.8m/min, 85 ℃ of bake out temperatures.
Comparative Examples three (chemical cleaning)
The difference of this Comparative Examples and embodiment one only is: embodiment one adopts plasma etching method that the faying face of coverlay is handled, and this Comparative Examples usage level chemical cleaning machine carries out chemical cleaning (microetch) to the faying face of coverlay by following condition and handles: microetch pressure 0.9kg/cm
2, 30 ℃ of microetch temperature, microetch speed 0.5um/min crosses motor speed 1.8m/min.The back usage level of finishing dealing with is washed the plate machine and is cleaned condition: pickling concentration 2.5%, on spray pressure 1.2kg/cm
2, following spray pressure 1.2kg/cm
2, speed 1.8m/min, 85 ℃ of bake out temperatures.
Test
With above each embodiment and Comparative Examples obtain just-scratching combined circuit board carries out peel strength test and thermal shock test.
Strength test method: with 90 degree peel strength testers, model is cut into the strip tester of 1 * 25cm, light sample one end with lighter, make flex plate and rigid plate from playing 0.5mm length, fixedly sample is on the stripping machine fixed axis, clamp the flex plate of having peeled off with clip, open and peel off test machine and printer record data.Test result sees Table one.
The thermal shock test method: sampling size 8 * 10cm, 150 ℃ * 60min of baking, the tin stove is heated 288 ℃, and sample is vertically immersed under the tin face, takes out behind the manual time-keeping 10S, repeats above method test 5 times.Test result sees Table two.
Table one peel strength test result
In the table one in " plasma etching process processes " hurdle 1., 2., 3. represent respectively embodiment one, two, three gained just-scratch the data that combined circuit board carries out peel strength test.
From table one data as can be known, adopt the inventive method to the coverlay faying face carry out that plasma etching process processes obtains just-peel strength of flex combined board obviously be better than adopting sandblast of the prior art, nog plate and chemical cleaning to the coverlay faying face handle obtain just-peel strength of flex combined board.
Table two thermal shock test result
In the table two in " processing method " hurdle 1., 2., 3. represent respectively embodiment one, two, three gained just-scratch the result that combined circuit board carries out thermal shock test.
Test result from table two as can be known, adopt the inventive method to the coverlay faying face carry out that plasma etching process processes obtains just-flex combined board slight layering just occurring behind the 5th thermal shock test continuously, and adopt chemical cleaning of the prior art to the coverlay faying face handle obtain just-flex combined board slight layering just occurs, adopts sandblast of the prior art behind the 2nd thermal shock test, nog plate is handled the firm-flex combined board that obtains to the coverlay faying face and slight layering just occurred at the 3rd thermal shock test.Adopt the inventive method to the coverlay faying face carry out that plasma etching process processes obtains just-thermal shock resistance of flex combined board obviously be better than adopting sandblast of the prior art, nog plate and chemical cleaning to the coverlay faying face handle obtain just-thermal shock resistance of flex combined board.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (8)
1, a kind of just-scratch the mating surface processing method of combined circuit board, it is characterized in that: comprise that the coverlay to flex plate internal layer surface carries out the process of plasma etching.
2, according to claim 1 just-scratch the mating surface processing method of combined circuit board, it is characterized in that: the process of flex plate internal layer surface coverlay being carried out plasma etching may further comprise the steps:
A. coverlay or the flex plate that posts coverlay are placed in the vacuum chamber;
B. charge into etching gas in vacuum chamber, and the etching gas in the vacuum chamber is loaded electromagnetic field so that etching gas ionization produces plasma, plasma carries out etch processes to the faying face of coverlay;
The faying face of the coverlay among the step b is meant the surface that combines with rigid plate of coverlay.
3, according to claim 2 just-scratch the mating surface processing method of combined circuit board, it is characterized in that: used etching gas is N among the step b
2, CF
4And O
2In one or more combination.
4, according to claim 2 or 3 described just-scratch the mating surface processing method of combined circuit board, it is characterized in that: step b comprises following process: carry out following four-stage under the situation that the etching gas in the vacuum chamber is loaded electromagnetic field: the phase I, the etching gas in the vacuum chamber is N
2Gas was handled 3-15 minute; Second stage, the etching gas in the vacuum chamber are CF
4And O
2Two kinds of gases were handled 10-50 minute; Phase III, the etching gas in the vacuum chamber is O
2Gas was handled 5-15 minute; Quadravalence section, the etching gas in the vacuum chamber are N
2Gas was handled 3-10 minute.
5, according to claim 2 or 3 described just-scratch the mating surface processing method of combined circuit board, it is characterized in that: after step b finishes, through the coverlay of etch processes in 6 hours with the rigid plate pressing.
6, according to claim 4 just-scratch the mating surface processing method of combined circuit board, it is characterized in that: after step b finishes, through the coverlay of etch processes in 6 hours with the rigidity circuit board pressing.
7, according to claim 5 just-scratch the mating surface processing method of combined circuit board, it is characterized in that: before etching, the faying face of coverlay cleaned and dry; With etch processes after the coverlay pressing before, the faying face of rigidity wiring board is cleaned and dry.
8, according to claim 6 just-scratch the mating surface processing method of combined circuit board, it is characterized in that: before etching, the faying face of coverlay cleaned and dry; With etch processes after the coverlay pressing before, the faying face of rigidity wiring board is cleaned and dry.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101050098A CN101483980B (en) | 2009-01-15 | 2009-01-15 | Combined surface processing method for firm-flexible combined circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101050098A CN101483980B (en) | 2009-01-15 | 2009-01-15 | Combined surface processing method for firm-flexible combined circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101483980A true CN101483980A (en) | 2009-07-15 |
| CN101483980B CN101483980B (en) | 2010-08-11 |
Family
ID=40880852
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101050098A Active CN101483980B (en) | 2009-01-15 | 2009-01-15 | Combined surface processing method for firm-flexible combined circuit board |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102695374A (en) * | 2012-06-14 | 2012-09-26 | 广州美维电子有限公司 | Processing method for enhancing lamination bonding force of rigid and flexible boards |
| CN102711394A (en) * | 2012-06-25 | 2012-10-03 | 广州美维电子有限公司 | Electroplating interconnecting processing technology for circuit board |
| CN103071646A (en) * | 2011-10-25 | 2013-05-01 | 深圳市迅捷兴电路技术有限公司 | Method for removing drilling smear on rigid-flexible printed circuit board by using plasma |
| CN103915374A (en) * | 2013-01-09 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Post-passivation interconnect structure and methods for forming the same |
| CN110248501A (en) * | 2019-07-01 | 2019-09-17 | 高德（无锡）电子有限公司 | The manufacturing process of the Rigid Flex of text is printed on soft board |
-
2009
- 2009-01-15 CN CN2009101050098A patent/CN101483980B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103071646A (en) * | 2011-10-25 | 2013-05-01 | 深圳市迅捷兴电路技术有限公司 | Method for removing drilling smear on rigid-flexible printed circuit board by using plasma |
| CN102695374A (en) * | 2012-06-14 | 2012-09-26 | 广州美维电子有限公司 | Processing method for enhancing lamination bonding force of rigid and flexible boards |
| CN102695374B (en) * | 2012-06-14 | 2014-10-08 | 广州美维电子有限公司 | Processing method for enhancing lamination bonding force of rigid and flexible boards |
| CN102711394A (en) * | 2012-06-25 | 2012-10-03 | 广州美维电子有限公司 | Electroplating interconnecting processing technology for circuit board |
| CN103915374A (en) * | 2013-01-09 | 2014-07-09 | 台湾积体电路制造股份有限公司 | Post-passivation interconnect structure and methods for forming the same |
| CN103915374B (en) * | 2013-01-09 | 2017-11-21 | 台湾积体电路制造股份有限公司 | Interconnection structure and forming method thereof after passivation |
| CN110248501A (en) * | 2019-07-01 | 2019-09-17 | 高德（无锡）电子有限公司 | The manufacturing process of the Rigid Flex of text is printed on soft board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101483980B (en) | 2010-08-11 |
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| C14 | Grant of patent or utility model | ||
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| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN KINWONG ELECTRONIC CO., LTD. Free format text: FORMER NAME: KINGWONG ELECTRONICS (SHENZHEN) CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 518000, No. 166, Reservoir Road, iron Gang village, West Village, Shenzhen, Guangdong, Baoan District Patentee after: Shenzhen Kinwong Electronic Co., Ltd. Address before: 518000, No. 166, Reservoir Road, iron Gang village, West Village, Shenzhen, Guangdong, Baoan District Patentee before: Kinwong Electronic (Shenzhen) Co., Ltd. |