CN101483386B - DC to DC transformer - Google Patents
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- CN101483386B CN101483386B CN200910006822XA CN200910006822A CN101483386B CN 101483386 B CN101483386 B CN 101483386B CN 200910006822X A CN200910006822X A CN 200910006822XA CN 200910006822 A CN200910006822 A CN 200910006822A CN 101483386 B CN101483386 B CN 101483386B
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Abstract
The present invention discloses a DC to DC converter, which comprises: a control circuit used for receiving and comparing DC output pressure, and outputs pulse wave width modulation signal of the first frequency when the DC output pressure no more than the first threshold voltage, and outputs pulse wave width modulation signal of the second frequency when the DC output pressure more than the first threshold voltage and the second frequency higher than the first frequency; a gate drive circuit used for receiving pulse wave width modulation signal and converting it into the first drive signal and the second drive signal; and a power stage circuit used for converting DC input pressure into DC output pressure according to the first drive signal and the second drive signal.
Description
Technical field
The invention relates to a kind of DC-DC converter (DC-to-DC converter) and particularly relevant for a kind of DC-DC converter and reduce the control method of overshoot phenomenon (over shoot).
Background technology
As everyone knows, DC-DC converter (DC-to-DC converter) can convert the different VD (DC outputvoltage) of size into DC input voitage (DC input voltage).
Please with reference to Fig. 1, it is depicted as known DC-DC converter sketch map.The DC-DC converter comprises a control circuit 10, a grid drive circuit (gate driver) 20, one power stage circuit (power stage) 30.In general; But the VD (Vout) that control circuit 10 received power level circuit 30 are produced; And produce corresponding pulse wave width modulation signal (pulse width modulation signal is hereinafter to be referred as pwm signal) according to the variation of VD (Vout).Moreover; Grid drive circuit 20 receives pwm signal and is converted into one first drive signal and one second drive signal to power stage circuit 30, and power stage circuit 30 can convert DC input voitage (Vin) to VD (Vout) according to the variation of first drive signal and second drive signal.
Moreover grid drive circuit 20 comprises one first driver 22 and one second driver 24.First driver 22 receives first drive signal of pwm signal and generation and pwm signal homophase; And second driver 24 receives pwm signal and second drive signal of generation and pwm signal anti-phase.
Moreover power stage circuit 30 comprises power transistor on (upper powertransistor) 32, once power transistor (lower power transistor) 34, one output inductor (Lo) and an output capacitor (Co).Last power transistor 32 drain electrodes are connected to DC input voitage (Vin), and last power transistor 32 grids receive first drive signal.Following power transistor 34 drain electrodes are connected to power transistor 32 source electrodes, and following power transistor 34 grids receive second drive signal, and following power transistor 34 source electrodes are connected to earth terminal (GND).And first end of output inductor (Lo) is connected to power transistor 32 source electrodes, and second end of output inductor (Lo) is the exportable VD of output (Vout) of power stage circuit 30.Moreover two ends of output capacitor (Co) are connected to respectively between the output and earth terminal (GND) of power stage circuit 30.In general, when DC input voitage (Vin) during greater than VD (Vout), the DC-DC converter can be considered buck DC-DC converter (Buck DC-to-DC converter).
With buck DC-DC converter; First drive signal and second drive signal that grid drive circuit 20 produces can be opened (turn on) respectively and gone up power transistor 32 and following power transistor 34, and upward power transistor 32 can't be unlocked with following power transistor 34 simultaneously.That is to say; When last power transistor 32 is opened; Following power transistor 34 is closed (turn off), and second electric current this moment (I2) is zero, and the output current Iout of power stage circuit 30 is provided by first electric current (I1) that the last power transistor 32 of unlatching is produced.Otherwise when power transistor 34 was opened instantly, last power transistor 32 was closed, and first electric current this moment (I1) is zero, and the output current Iout of power stage circuit 30 is provided by second electric current (I2) that power transistor 34 under opening is produced.In general; When the VD (Vout) of control circuit 10 receptions is lower than default value (for example 3.3V); The pulse bandwidth of pwm signal can broaden; Therefore, power transistor 32 is opened the long time on the first drive signal may command of grid drive circuit 20 generations, and power transistor 32 is closed the long time under the control of second drive signal.Otherwise; When the VD (Vout) of control circuit 10 receptions is higher than default value (for example 3.3V); The pulse bandwidth of pwm signal can narrow down; Therefore, power transistor 32 is opened the short time on the first drive signal may command that grid drive circuit 20 produces, and power transistor 32 is closed the short time under the second drive signal may command.
Moreover the control circuit 10 in the DC-DC converter has many control models (mode).General common having, voltage mode control (voltage mode), current control mode (currentmode) and fixing opening time control model (constant on-time mode).These three kinds of control models below are detailed, and grid drive circuit 20, all identical with the structure of power stage circuit 30, so repeat no more.
Please with reference to Fig. 2 A, it is depicted as the DC-DC converter sketch map of known voltage control model.The DC-DC converter of voltage mode control comprises: a control circuit 210, a grid drive circuit 220, a power stage circuit 230.Wherein, control circuit 210 comprises: an error amplifier (error amplifier) 212, one a modulation unit (modulator) 214 and a signal generator (wave generator) 216.Error amplifier 212 receives VDs (Vout) and reference voltages (Vref), and error amplifier 212 can compare VD (Vout) and with reference voltage (Vref) and then produce a compensating signal (comp) to modulation unit 214.
Moreover the sawtooth signal (ramp) of signal generator 216 exportable first frequencies makes modulation unit 214 to produce pwm signal according to compensating signal (comp) and sawtooth signal (ramp) to modulation unit 214.Certainly, signal generator 216 also can be exported other shape signal except exportable sawtooth signal (ramp), for example triangular signal (trianglesignal).
Please with reference to Fig. 2 B, its be depicted as compensating signal (comp) in the DC-DC converter of voltage mode control, sawtooth signal (ramp), pwm signal, first signal, with the secondary signal sketch map.When compensating signal (comp) during greater than sawtooth signal (ramp) pwm signal be high level, otherwise, when compensating signal (comp) during less than sawtooth signal (ramp) pwm signal be low level.Clearly, when compensating signal (comp) was changing, the pulse bandwidth of pwm signal also can change thereupon.Moreover, first drive signal and pwm signal homophase, second drive signal and pwm signal anti-phase.And the frequency of the frequency of pwm signal and sawtooth signal is all first frequency.
Please with reference to Fig. 3 A, it is depicted as the DC-DC converter of current known control model.The DC-DC converter of current control mode comprises: a control circuit 310, a grid drive circuit 320, a power stage circuit 330.Wherein, control circuit 310 comprises: an error amplifier 312, PWM comparator (PWM comparator) 313, one signal generator 314, a current sense amplifier (current sense amplifier) 315, one adder (adder) 316, with a SR latch (SR latch) 317.Error amplifier 312 receives VDs (Vout) and reference voltages (Vref), and error amplifier 312 can compare VD (Vout) and with reference voltage (Vref) and then produce a compensating signal (comp) to PWM comparator 313.
Moreover current sense amplifier 315 can be detected first electric current (I1) that flows through power transistor in the power stage circuit 330 or second electric current (I2) that descends power transistor.For instance, current sense amplifier 315 can be converted into sensing signal (Vsense) with the electric current of going up power transistor (I1).
Moreover signal generator 314 can be exported a sawtooth signal (ramp) and a clock pulse signal (CLK) simultaneously, and sawtooth signal (ramp) has identical first frequency with clock signal (CLK).Sawtooth signal (ramp) and sensing signal (Vsense) become afterwards via adder 316 superpositions (superpose) and add resultant signal (sum).Add resultant signal (sum) and compensating signal (comp) input PWM comparator 313.When adding resultant signal (sum) greater than compensating signal (comp), and the replacement end of PWM comparator 313 meeting output one pulse wave to SR latchs 317 (reset terminal, R).Moreover, the setting end of clock signal (CLK) meeting input SR latch 317 (set terminal, S).And can produce pwm signal with the signal variation of setting end (S) according to the replacement end (R) of SR latch 317.Certainly, signal generator 216 also can be exported other shape signal except exportable sawtooth signal (ramp), for example triangular signal (triangle signal).
Please with reference to Fig. 3 B, it is depicted as output current (Iout), sensing signal (Vsense), sawtooth signal (ramp), compensating signal (comp) in the DC-DC converter of current control mode, adds the replacement end (R) and signal, the pwm signal sketch map of setting end (S) of resultant signal (sum), SR latch.
Wherein, the zone that output current (Iout) rises is first electric current (I1) of power transistor, and the zone that output current (Iout) descends is down second electric current (I2) of power transistor.Therefore, current sense amplifier 315 gets final product sensing first electric current (I1) and produces sensing signal (Vsense).By knowing that when the setting end (S) of SR latch received a pulse wave, pwm signal was a high level among the figure, when the replacement end (R) of SR latch was received a pulse wave, pwm signal was a low level.Therefore, the pulse bandwidth of pwm signal can change along with first electric current (I1) size.
Please with reference to Fig. 4 A, it is depicted as the DC-DC converter of known fixed opening time control model.Fixedly the DC-DC converter of opening time control model comprises: control circuit 410, a grid drive circuit 420, a power stage circuit 430.Wherein, control circuit 410 comprises: a loop comparator (loop comparator) 412, one SR latch (SR latch) 414, one opening time timer (on-time timer) 416.Wherein, opening time timer 416 is to utilize a constant current source (Ion) to a capacitor (Con) action of charging, and the relation between charging voltage (Vcharge) and the constant current source (Ion) is:
That is to say; When opening time timer 416 starts each time; The action that begins to charge, when charging voltage arrives a scheduled voltage (predetermined voltage), the replacement end (R) that opening time timer 416 can output one pulse wave to SR latchs 414.Because constant current source (Ion) and capacitor (Con) are all fixed numeric values, therefore, the time that each charging voltage (Vcharge) arrives scheduled voltage is all the fixedly opening time of Ton.
Moreover loop comparator 412 receives VDs (Vout) and reference voltages (Vref), and when VD (Vout) during less than reference voltage (Vref), loop comparator 412 can be exported the setting end (S) of a pulse wave to SR latchs 414.Pick up counting and when the setting end (S) of loop comparator 412 output pulse wave to SR latchs 414, also can control opening time timer 416, and export the replacement end (R) of a pulse wave to SR latch 414 after the time in Ton.And can produce pwm signal with the signal variation of setting end (S) according to the replacement end (R) of SR latch 414.
Please with reference to Fig. 4 B, it is depicted as the output voltage (Vout) in the DC-DC converter of fixing opening time control model, replacement end (R) and the signal and the pwm signal sketch map of setting end (S) of SR latch.
Wherein, when output voltage (Vout) during less than reference voltage, the setting end (S) of SR latch receives pulse wave.And through after the time of Ton, opening time timer 416 produces the replacement end (R) of a pulse wave to SR latch.By knowing that when the setting end (S) of SR latch received a pulse wave, the PM signal was a high level among the figure, when the replacement end (R) of SR latch was received a pulse wave, the PM signal was a low level.
As everyone knows, the central processing unit in the computer system (CPU), dynamic random access memory (DRAM), drawing chip (graphic chip), the employed operating voltage of chipset (chip set) are neither identical.Therefore, need many DC-DC converters to press (for example 19V) to be converted into the required operating voltage of each element in the computer system in order to the direct current input that power supply unit is provided.Yet the transient state of DC-DC converter (transient) can produce influence greatly for the efficient (performance) of above-mentioned each element.
When the load (load) of DC-DC converter changes when violent, output current (Iout) can change apace.For instance, when the output current (Iout) of DC-DC converter when reducing suddenly, VD (Vout) can raise accordingly fast, and this phenomenon is called overshoot phenomenon (overshoot).Otherwise when the output current (Iout) of DC-DC converter when raising suddenly, VD (Vout) can reduce accordingly fast, and this phenomenon is called owes towards phenomenon (undershoot).
When the overshoot phenomenon or owe when phenomenon takes place, the control circuit in the DC-DC converter must return back to too high or too low VD the voltage of stable state (steady state).With the overshoot phenomenon is example, and when the transient state that the overshoot phenomenon takes place, VD can be higher than the VD of stable state, is overshoot voltage (overshoot voltage) and exceed maximum.
As shown in Figure 5; With the frequency of operation of the pwm signal of the DC-DC converter of voltage mode control is 200KHz and the VD of stable state is 1.26V is example; When output current sharply is reduced to 5A by 90A; The VD of transient state can increase to 1.36V, that is overshoot voltage is 100mV.As shown in Figure 6; With the fixing frequency of operation of the pwm signal of the DC-DC converter of opening time control model is 276KHz and the VD of stable state is 1.96V is example; When output current sharply is reduced to 1.5 A by 25A; The VD of transient state can increase to 2.04V, that is overshoot voltage is 80mV.
Therefore, the designer of DC-DC converter can be to overshoot phenomenon and the road of owing to propose towards phenomenon improvement.Yet most DC-DC converter design person is directed against to owe to improve towards phenomenon, and bright few overshoot phenomenon that proposes to improve.
Propose a kind of soft start voltage level like U.S. Pat 7157943 and carry out the switch mode power converter (Frequency selection of switch mode power convertersvia softstart voltage level) that frequency is selected.The switch mode power converter that this patent proposed is declared to reduce overshoot phenomenon.Yet, in this patent and not mentionedly how to put into practice and reduce overshoot phenomenon.
Moreover TaiWan, China patent I251395 proposes a kind of PWM device that utilizes output voltage back coupling hysteresis circuitry to change output frequency automatically.Clearly, this patent is the influence that causes for the loss that solves power transistor or following power transistor.Moreover the pwm signal of this patent can constantly change, and therefore, the stability of whole DC-DC converter can variation.
Summary of the invention
The present invention proposes a kind of DC-DC converter; Comprise: a control circuit, reception is also compared a direct current output voltage, when VD does not surpass one first limit voltage; Export a pulse wave width modulation signal of a first frequency; And when VD surpasses first limit voltage, export the pulse wave width modulation signal of a second frequency, and second frequency is greater than first frequency; One grid drive circuit receives the pulse wave width modulation signal and is converted into one first drive signal and one second drive signal; One power stage circuit converts a direct current input voltage to VD according to first drive signal and second drive signal.
The present invention more proposes a kind of control method of DC-DC converter; This DC-DC converter comprises; One control circuit, a grid drive circuit, with a power stage circuit; And control circuit can receive the direct current output voltage that this power stage circuit produces; And produce a corresponding pulse wave width modulation signal according to the variation of VD; And the grid drive circuit receives the pulse wave width modulation signal and is converted into one first drive signal and one second drive signal to power stage circuit, makes power stage circuit to convert a direct current input voltage to VD according to the variation of first drive signal and second drive signal, and the control method of this DC-DC converter comprises the following step: monitor output dc voltage constantly; When this VD does not surpass one first limit voltage, switch frequency of operation to a first frequency of this pulse wave width modulation signal; And, when VD surpasses first limit voltage, switch frequency of operation to a second frequency of pulse wave width modulation signal, and second frequency is greater than first frequency.
The present invention also proposes a kind of control method of DC-DC converter; The DC-DC converter comprises; One control circuit, a grid drive circuit, with a power stage circuit; And control circuit can receive the direct current output voltage that this power stage circuit produces; And produce a corresponding pulse wave width modulation signal according to the variation of VD; And the grid drive circuit receives this pulse wave width modulation signal and is converted into one first drive signal and one second drive signal to power stage circuit; Make power stage circuit to convert a direct current input voltage to VD and an output current flow through a sensing impedance and a load according to the variation of first drive signal and second drive signal, the control method of DC-DC converter comprises the following step: monitor output current stream Copper Foil constantly and survey the sensing voltage that impedance produced; When sensing voltage is mended voltage partially less than one, switch frequency of operation to a first frequency of pulse wave width modulation signal; And, when the rapid decline of output current causes sensing voltage to increase, switch frequency of operation to a second frequency of pulse wave width modulation signal, and second frequency is greater than first frequency.
Therefore, the invention has the advantages that and monitor VD (Vout) constantly, when VD surpasses first limit voltage (for example, stable state VD 1.03 times), represent DC-DC converter generation overshoot phenomenon.At this moment, control circuit improves the frequency of operation of pwm signal.Make and go up power transistor and the switch speed increase of power transistor down, in order to suppress overshoot voltage.When being lower than first limit voltage (for example, stable state VD 1.03 times), represent the DC-DC converter to be about to reply stable state when VD.At this moment, control circuit is replied the normal running frequency of pwm signal.
Description of drawings
In order to make the auditor can further understand characteristic of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet appended accompanying drawing only provides reference and explanation, is not to be used for the present invention is limited, wherein:
Shown in Figure 1 is known DC-DC converter sketch map;
Fig. 2 A is depicted as the DC-DC converter of known voltage control model;
Fig. 2 B be depicted as compensating signal (comp) in the DC-DC converter of voltage mode control, sawtooth signal (ramp), pwm signal, first signal, with the secondary signal sketch map;
Fig. 3 A is depicted as the DC-DC converter of current known control model;
The replacement end (R) that Fig. 3 B is depicted as output current (Iout), sensing signal (Vsense), sawtooth signal (ramp), compensating signal (comp) in the DC-DC converter of current control mode, add resultant signal (sum), SR latch and the signal of setting end (S), with the pwm signal sketch map;
Fig. 4 A is depicted as the DC-DC converter of known fixed opening time control model;
The replacement end (R) that Fig. 4 B is depicted as output voltage (Vout) in the DC-DC converter of fixing opening time control model, SR latch and the signal of setting end (S), with the pwm signal sketch map;
Shown in Figure 5 is the DC-DC converter overcharged voltage sketch map of known voltage control model;
Shown in Figure 6 is the DC-DC converter overcharged voltage sketch map of known fixed opening time control model.
Shown in Figure 7 for the control method flow chart of DC-DC converter of the present invention;
Fig. 8 A is depicted as the DC-DC converter of the voltage mode control of first embodiment of the invention;
Fig. 8 B be depicted as compensating signal (comp) in the DC-DC converter of voltage mode control, sawtooth signal (ramp), with the pwm signal sketch map;
Shown in Figure 9 for the DC-DC converter overcharged voltage sketch map of voltage mode control of the present invention;
Figure 10 A is depicted as the DC-DC converter of second embodiment of the invention current control mode.
The replacement end (R) that Figure 10 B is depicted as output current (Iout), sensing signal (Vsense), sawtooth signal (ramp), compensating signal (comp) in the DC-DC converter of current control mode, add resultant signal (sum), SR latch and the signal of setting end (S), with the pwm signal sketch map;
Figure 11 A is depicted as the fixedly DC-DC converter of opening time control model of third embodiment of the invention;
Figure 11 B, its replacement end (R) that is depicted as output voltage (Vout) in the DC-DC converter of fixing opening time control model, SR latch and the signal of setting end (S), with the pwm signal sketch map;
Shown in Figure 12ly be the fixing DC-DC converter overcharged voltage sketch map of opening time control model of the present invention;
Shown in Figure 13 is the DC-DC converter of voltage mode control.
Embodiment
Please with reference to Fig. 7, it is depicted as the control method flow chart of DC-DC converter of the present invention.Monitor VD (step S10) at first, constantly.When VD during less than first limit voltage (step S12), then skip to step S10; Otherwise, when VD during greater than first limit voltage (step S12), then improve the frequency of pwm signal, that is, be increased to a second frequency (step S14) by a first frequency.Then, monitor VD (step S16) unceasingly.When VD during greater than first limit voltage (step S18), then skip to step S16; Otherwise, when VD during less than first limit voltage (step S18), then recover the frequency of former pwm signal, that is, be reduced to first frequency (step S20) by second frequency, and skip to (step S10).
According to embodiments of the invention; VD can be monitored constantly; When VD surpasses first limit voltage (Vth1) (for example, Vth1=Vout+Delta, and Vout is the VD of stable state; And Delta can be set at 0.03Vout), represent DC-DC converter generation overshoot phenomenon.At this moment, the frequency of operation of control circuit raising pwm signal is to second frequency.Make and go up power transistor and the switch speed increase of power transistor down, therefore, can suppress overshoot voltage effectively.
Moreover, when VD is lower than first limit voltage (for example, stable state VD 1.03 times), represent the DC-DC converter to be about to reply stable state.At this moment, the frequency of operation of control circuit answer pwm signal is to first frequency.
Below introduce in detail voltage mode control of the present invention DC-DC converter, current control mode the DC-DC converter and, the fixing DC-DC converter of opening time control model.
Please with reference to Fig. 8 A, it is depicted as the DC-DC converter of the voltage mode control of first embodiment of the invention.The DC-DC converter of voltage mode control comprises: a control circuit 610, a grid drive circuit 620, a power stage circuit 630.Wherein, control circuit 610 comprises: an error amplifier 612, a modulation unit 614, with a signal generator 616, with a comparator 618.
Moreover; Signal generator 616 is optionally exported the sawtooth signal (ramp) of first frequency (F1) or second frequency (F2) to modulation unit 614, makes modulation unit 614 to produce pwm signal according to compensating signal (comp) and sawtooth signal (ramp).Certainly; Signal generator 616 is except the sawtooth signal (ramp) of exportable first frequency (F1) or second frequency (F2); Also can export other shape signal of first frequency (F1) or second frequency (F2), for example triangular signal (triangle signal).Wherein, first frequency (F1) is less than second frequency (F2).
Moreover comparator 618 can receive first limit voltage (Vth1) and VD (Vout).When VD (Vout) during less than first limit voltage (Vth1), comparator 618 exportable first level are to signal generator 616, make the sawtooth signal (ramp) of signal generator 616 output first frequencies (F1) to modulation unit 614.Otherwise when VD (Vout) during greater than first limit voltage (Vth1), comparator 618 exportable second level are to signal generator 616, make the sawtooth signal (ramp) of signal generator 616 output second frequencies (F2) to modulation unit 614.
Please with reference to Fig. 8 B, its be depicted as compensating signal (comp) in the DC-DC converter of voltage mode control, sawtooth signal (ramp), with the pwm signal sketch map.When compensating signal (comp) during greater than sawtooth signal (ramp) pwm signal be high level, otherwise when compensating signal (comp) during less than sawtooth signal (ramp) pwm signal be low level.Clearly, when sawtooth signal (ramp) was changing, the pulse bandwidth of pwm signal also can change thereupon; Moreover when sawtooth signal (ramp) was first frequency (F1), pwm signal operated in first frequency (F1); When sawtooth signal (ramp) was second frequency (F2), pwm signal operated in second frequency (F2).Therefore, the DC-DC converter of voltage mode control of the present invention can be controlled the frequency of operation of pwm signal according to the size of VD (Vout).
As shown in Figure 9; According to the first embodiment of the present invention; When the first frequency of the pwm signal of the DC-DC converter of voltage mode control is 200KHz and the VD of stable state is 1.26V is example, when output current sharply is reduced to 5A by 90A, pwm signal is adjusted into second frequency (342KHz) can make the VD of transient state can increase to 1.33V; That is overshoot voltage is 70mV.Therefore can suppress overshoot voltage effectively.
Please with reference to Figure 10 A, it is depicted as the DC-DC converter of second embodiment of the invention current control mode.The DC-DC converter of current control mode comprises: a control circuit 710, a grid drive circuit 720, a power stage circuit 730.Wherein, control circuit 7 10 comprises: an error amplifier 712, PWM comparator 713, a signal generator 714, a current sense amplifier 715, an adder 716, a SR latch 717, with a comparator 718.Error amplifier 712 receives VDs (Vout) and reference voltages (Vref), and error amplifier 712 can compare VD (Vout) and with reference voltage (Vref) and then produce a compensating signal (comp) to PWM comparator 713.
Moreover current sense amplifier 715 can be detected first electric current (I1) that flows through power transistor in the power stage circuit 730 or second electric current (I2) that descends power transistor.For instance, current sense amplifier 715 can be converted into sensing signal (Vsense) with the electric current of going up power transistor (I1).
Moreover signal generator 314 can be exported a sawtooth signal (ramp) and a clock pulse signal (CLK) simultaneously, and sawtooth signal (ramp) optionally has identical first frequency (F1) or second frequency (F2) with clock signal (CLK).And sawtooth signal (ramp) and sensing signal (Vsense) become afterwards via adder 716 superpositions (superpose) and add resultant signal (sum).Wherein, first frequency (F1) is less than second frequency (F2).
And add resultant signal (sum) and compensating signal (comp) input PWM comparator 313, when adding resultant signal (sum) greater than compensating signal (comp), the replacement end of PWM comparator 313 meeting output one pulse wave to SR latchs 317 (reset terminal, R).Moreover, the setting end of clock signal (CLK) meeting input SR latch 317 (set terminal, S).And can produce pwm signal with the signal variation of setting end (S) according to the replacement end (R) of SR latch 317.Certainly, signal generator 216 also can be exported triangular signal (trianglesignal) except exportable sawtooth signal (ramp).
Moreover comparator 718 can receive first limit voltage (Vth1) and VD (Vout).When VD (Vout) during less than first limit voltage (Vth1), comparator 718 exportable first level are to signal generator 716, make the sawtooth signal (ramp) and clock signal (CLK) of signal generator 714 output first frequencies (F1).Otherwise when VD (Vout) during greater than first limit voltage (Vth1), comparator 718 exportable second level are to signal generator 714, make the sawtooth signal (ramp) and clock signal (CLK) of signal generator 714 output second frequencies (F2).
Please with reference to Figure 10 B, the replacement end (R) that it is depicted as output current (Iout), sensing signal (Vsense), sawtooth signal (ramp), compensating signal (comp) in the DC-DC converter of current control mode, add resultant signal (sum), SR latch and the signal of setting end (S), with the PM signal schematic representation.
Wherein, the zone that output current (Iout) rises is first electric current (I1) of power transistor, and the zone that output current (Iout) descends is down second electric current (I2) of power transistor.Therefore, current sense amplifier 315 gets final product sensing first electric current (I1) and produces sensing signal (Vsense).By knowing that when the setting end (S) of SR latch received a pulse wave, pwm signal was a high level among the figure, when the replacement end (R) of SR latch was received a pulse wave, pwm signal was a low level.Therefore, the pulse bandwidth of pwm signal can change along with first electric current (I1) size.Moreover when sawtooth signal (ramp) and clock signal (CLK) were first frequency (F1), pwm signal operated in first frequency (F1); When sawtooth signal (ramp) and clock signal (CLK) were second frequency (F1), pwm signal operated in second frequency (F2).Therefore, the DC-DC converter of current control mode of the present invention can be controlled the frequency of operation of pwm signal according to the size of VD (Vout).
Please with reference to Figure 11 A, it is depicted as the fixedly DC-DC converter of opening time control model of third embodiment of the invention.Fixedly the DC-DC converter of opening time control model comprises: control circuit 810, a grid drive circuit 820, a power stage circuit 830.Wherein, control circuit 810 comprises: a loop comparator 812, a SR latch 814, an opening time timer 816, with a comparator 818.Wherein, opening time timer 816 is one first constant current source (Ion1) capable of using or one second constant current source (Ion2) to a capacitor (Con) action of charging, and wherein first constant current source (Ion1) is less than second constant current source (Ion2).And the relation between charging voltage (Vcharge) and first constant current source (Ion1) is:
Relation between charging voltage (Vcharge) and second constant current source (Ion2) is:
That is to say; When opening time timer 816 starts each time; First constant current source capable of using (Ion1) or second constant current source (Ion2) come a capacitor (Con) action that begins to charge; When charging voltage arrived a scheduled voltage (predetermined voltage), opening time timer 816 can be exported the replacement end (R) of a pulse wave to SR latch 814.Clearly, when charging, the time of charging voltage (Vcharge) arrival scheduled voltage is all the fixedly opening time of Ton1 by first constant current source (Ion1); In like manner, when charging, the time of charging voltage (Vcharge) arrival scheduled voltage is all the fixedly opening time of Ton2 by second constant current source (Ion2).
Moreover loop comparator 812 receives VDs (Vout) and reference voltages (Vref), and when VD (Vout) during less than reference voltage (Vref), loop comparator 812 can be exported the setting end (S) of a pulse wave to SR latchs 814.Pick up counting and when the setting end (S) of loop comparator 812 output pulse wave to SR latchs 814, also can control opening time timer 816, and export the replacement end (R) of a pulse wave to SR latch 814 after the time in Ton1 or Ton2.And can produce pwm signal with the signal variation of setting end (S) according to the replacement end (R) of SR latch 814.
Moreover comparator 818 can receive first limit voltage (Vth1) and VD (Vout).When VD (Vout) during less than first limit voltage (Vth1), comparator 818 exportable first level can charge the current source of winning (Ion1) to capacitor (Con) in order to control switch (SW); Otherwise when VD (Vout) during greater than first limit voltage (Vth1), comparator 818 exportable second level make second current source (Ion2) to charge to capacitor (Con) in order to control switch (SW).
Please with reference to Figure 11 B, its replacement end (R) that is depicted as output voltage (Vout) in the DC-DC converter of fixing opening time control model, SR latch and the signal of setting end (S), with the pwm signal sketch map.
Wherein, when output voltage (Vout) during less than reference voltage, the setting end (S) of SR latch receives pulse wave.When switch (SW) switched to first constant current source (Ion1), through after the time of Ton1, opening time timer 816 produced the replacement end (R) of a pulse wave to SR latch; Otherwise when switch (SW) switched to second constant current source (Ion2), through after the time of Ton2, opening time timer 816 produced the replacement end (R) of a pulse wave to SR latch.By knowing that when the setting end (S) of SR latch received a pulse wave, pwm signal was a high level among the figure, when the replacement end (R) of SR latch was received a pulse wave, pwm signal was a low level.Clearly, control first current source (Ion1) or second current source (Ion2) to capacitor (Con) charging can select the fixedly opening time of Ton1 or the fixedly opening time of Ton2.And the frequency of pwm signal is lower when selecting fixedly opening time of Ton1; The frequency of pwm signal is higher during fixedly opening time of selecting Ton2.Therefore, the DC-DC converter of fixedly opening time control model of the present invention can be controlled the frequency of operation of pwm signal according to the size of VD (Vout).
Shown in figure 12; A third embodiment in accordance with the invention; When the fixing frequency of operation of the pwm signal of the DC-DC converter of opening time control model is 276KHz and the VD of stable state is 1.96V is example, when output current sharply is reduced to 1.5A by 25A, pwm signal is adjusted into second frequency (342KHz) can make the VD of transient state can increase to 2.01V; That is overshoot voltage is 50mV.Therefore can suppress overshoot voltage effectively.
Moreover, adjusting the frequency of pwm signal except utilizing VD (Vout), the designer who is familiar with this memory also can overcharge the judgement of phenomenon according to the variation situation of output current (Iout), and reduces overcharged voltage.Please with reference to Figure 13, it is depicted as the DC-DC converter of voltage mode control.The DC-DC converter of this voltage mode control comprises: a control circuit 610, a grid drive circuit 620, a power stage circuit 630, mend voltage (Voffset), a sensing impedance 642 and a load 640 partially.As shown in the figure, control circuit 610 comprises: an error amplifier 612, a modulation unit 614, with a signal generator 616 and a hysteresis comparator (hysteresiscomparator) 619.
Moreover; Signal generator 616 is optionally exported the sawtooth signal (ramp) of first frequency (F1) or second frequency (F2) to modulation unit 614, makes modulation unit 614 to produce pwm signal according to compensating signal (comp) and sawtooth signal (ramp).
According to this embodiment, sensing impedance 642 can be an inductive impedance.When output current when output current (Iout) when sharply diminishing, the load voltage (Vload) of load 640 ends sharply descends.At this moment, because the impedance effect of sensing impedance 642 self can make VD (Vout) can not change at once, therefore, can produce sensing voltage (Δ V, sense voltage) in the sensing impedance 642.
When sensing voltage (Δ V) when partially mending voltage (Voffset), represent can overcharge phenomenon at this moment, and hysteresis comparator 619 may command signal generators 616 rise to second frequency (F2) by first frequency (F1).That is to say that when sensing voltage (Δ V) was very little, hysteresis comparator 6 19 exportable first level were to signal generator 616, make the sawtooth signal (ramp) of signal generator 616 output first frequencies (F1) to modulation unit 614.Otherwise; When output current (Iout) sharply reduces the result who makes sensing voltage (Δ V) deduct inclined to one side benefit voltage (Voffset) and arrives the level translation point of hysteresis comparator 619; Hysteresis comparator 619 exportable second level are to signal generator 616, make the sawtooth signal (ramp) of signal generator 616 output second frequencies (F2) to modulation unit 614.
Moreover the comparator 618,718,818 among above-mentioned three embodiment also can use hysteresis comparator, in order to prevent the disturbance of VD, makes the operation that the DC-DC converter can be more stable.
In sum; Though the present invention discloses as above with preferred embodiment; Right its is not in order to limiting the present invention, anyly has the knack of this operator, do not breaking away from the spirit and scope of the present invention; When can doing various changes and retouching, so protection scope of the present invention is when looking being as the criterion that claims define.
Claims (3)
1. a DC-DC converter is characterized in that, comprising:
Control circuit; Reception is also compared VD; When above-mentioned VD does not surpass first limit voltage, the pulse wave width modulation signal of output first frequency, and when above-mentioned VD during above above-mentioned first limit voltage; The above-mentioned pulse wave width modulation signal of output second frequency, and above-mentioned second frequency is greater than above-mentioned first frequency;
The grid drive circuit receives above-mentioned pulse wave width modulation signal and is converted into first drive signal and second drive signal; And
Power stage circuit converts DC input voitage to above-mentioned VD according to above-mentioned first drive signal and above-mentioned second drive signal,
Wherein above-mentioned control circuit comprises:
The loop comparator receives above-mentioned VD and reference voltage, and produces first pulse wave;
Comparator; Receive above-mentioned first limit voltage and above-mentioned VD, when above-mentioned VD during less than above-mentioned first limit voltage, above-mentioned comparator is exported first level; When above-mentioned VD during greater than above-mentioned first limit voltage, above-mentioned comparator is exported second level;
The opening time timer; When above-mentioned comparator is exported above-mentioned first level, produce second pulse wave, and first pulse wave and above-mentioned second pulse wave differed for first opening time; And when above-mentioned comparator is exported above-mentioned second level; Produce the 3rd pulse wave, and first pulse wave and above-mentioned the 3rd pulse wave differed for second opening time, and above-mentioned first opening time is greater than above-mentioned second opening time; And
The SR latch produces above-mentioned pulse wave width modulation signal according to above-mentioned first pulse wave and above-mentioned second pulse wave, perhaps produces above-mentioned pulse wave width modulation signal according to above-mentioned first pulse wave and above-mentioned the 3rd pulse wave.
2. DC-DC converter according to claim 1; It is characterized in that; Wherein above-mentioned opening time timer utilizes first constant current source and second constant current source to charge and obtains above-mentioned first opening time and above-mentioned second opening time in capacitor, and above-mentioned first constant current source is less than above-mentioned second constant current source.
3. DC-DC converter according to claim 1 is characterized in that, wherein above-mentioned comparator is a hysteresis comparator.
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| CN101924469B (en) | 2010-08-06 | 2012-10-24 | 东南大学 | Switching power supply with fast transient response |
| TWI449311B (en) * | 2010-12-31 | 2014-08-11 | Hanergy Technologies Inc | Methology of on-chip soft-start circuits for switching mode dc/dc converter |
| US8742741B2 (en) * | 2011-03-30 | 2014-06-03 | Fairchild Semiconductor Corporation | Apparatus and methods of soft-start in a hysteretic power converter |
| TWI477048B (en) * | 2011-07-27 | 2015-03-11 | Upi Semiconductor Corp | Dc-dc converter and voltage conversion method thereof |
| US9178417B2 (en) | 2011-07-27 | 2015-11-03 | Upi Semiconductor Corp. | DC-DC converter and voltage conversion method thereof |
| US9164528B2 (en) * | 2012-10-17 | 2015-10-20 | Texas Instruments Incorporated | Apparatus and method for controlling inductor current in a switch mode power supply |
| US9973078B2 (en) * | 2016-09-13 | 2018-05-15 | Kabushiki Kaisha Toshiba | Power conversion apparatus and method of using the apparatus |
| CN108631575B (en) * | 2018-06-27 | 2023-11-28 | 裕太微电子股份有限公司 | Soft start circuit applied to switching power supply |
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