CN101477967A - Process for preparing vertical structure phase-change memory - Google Patents
Process for preparing vertical structure phase-change memory Download PDFInfo
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- CN101477967A CN101477967A CNA200910029174XA CN200910029174A CN101477967A CN 101477967 A CN101477967 A CN 101477967A CN A200910029174X A CNA200910029174X A CN A200910029174XA CN 200910029174 A CN200910029174 A CN 200910029174A CN 101477967 A CN101477967 A CN 101477967A
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- 230000015654 memory Effects 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000009413 insulation Methods 0.000 claims abstract description 31
- 238000005498 polishing Methods 0.000 claims abstract description 16
- 238000007747 plating Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 238000001704 evaporation Methods 0.000 claims description 25
- 230000008020 evaporation Effects 0.000 claims description 21
- LDMJFDJYOVHUMJ-UHFFFAOYSA-N stibanylidynesilicon Chemical compound [Sb]#[Si] LDMJFDJYOVHUMJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052714 tellurium Inorganic materials 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 239000004793 Polystyrene Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229920002223 polystyrene Polymers 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000005566 electron beam evaporation Methods 0.000 claims description 3
- 239000003960 organic solvent Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000008367 deionised water Substances 0.000 claims description 2
- 229910021641 deionized water Inorganic materials 0.000 claims description 2
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 claims description 2
- 238000009826 distribution Methods 0.000 claims description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 239000012782 phase change material Substances 0.000 abstract description 7
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000003860 storage Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 4
- 239000011241 protective layer Substances 0.000 abstract 1
- 238000011536 re-plating Methods 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 9
- -1 chalcogenide compound Chemical class 0.000 description 7
- 230000009466 transformation Effects 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000002096 quantum dot Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- WYURNTSHIVDZCO-UHFFFAOYSA-N Tetrahydrofuran Chemical compound C1CCOC1 WYURNTSHIVDZCO-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000002077 nanosphere Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 101100493820 Caenorhabditis elegans best-1 gene Proteins 0.000 description 1
- 229910000618 GeSbTe Inorganic materials 0.000 description 1
- BLOIXGFLXPCOGW-UHFFFAOYSA-N [Ti].[Sn] Chemical compound [Ti].[Sn] BLOIXGFLXPCOGW-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002061 nanopillar Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
The invention relates to a method for preparing a phase change memory with a vertical structure, and belongs to the technical field of nano-electronic and nano-optoelectronic devices. The method comprises the steps of substrate preparing, thermal protective layer plating, thin layer plating, template laying, ion etching, template removing, thermal insulation layer plating, polishing and planishing, photoengraving and corroding, thermal insulation layer re-plating, re-polishing and planishing, and electrode manufacturing. The method adopts nano-array phase change material as a carrier for information storage, improves the thermal efficiency of the phase change active region through introducing a proper dielectric layer between the electrode and the phase change material, ensures that the operating current and the power consumption of the memory device are effectively reduced, and has the advantages of simple process and low cost, thereby providing the foundation for the commercial memory which is suitable for PCRAM.
Description
Technical field
The present invention relates to a kind of method for preparing vertical structure phase-change memory, be that a kind of photoetching and nanosphere lithographic technique of utilizing combines, preparation is inferior 30 nano level, with the method for chalcogenide compound nano-dot matrix as the vertical structure phase-change memory of active layer, belong to nanoelectronic and nano photoelectronic devices technical field.
Background technology
Chalcogenide compound Ge-Sb-Te or silicon antimony tellurium (GexSbyTez) (SixSbyTez) inversion of phases semiconductor memory (being called for short PCRAM) are a kind of emerging semiconductor memories, compare with present existing multiple semiconductor memory technologies, have non-volatile, have extended cycle life, low in energy consumption, can multistagely store, read at a high speed, advantage such as anti-interference.Yet make the PCRAM device compare and embody superiority and competitiveness with the commercialization memory, just must make nanometer electronic device, especially the size as the most crucial phase transformation active area of memory must reach tens nanometers to several nanometers, just can make material undergo phase transition required voltage and power consumption reduces greatly, thereby realize nanometer electronic device truly.Understand according to the applicant, still do not have the method for preparing chalcogenide compound nano-dot matrix vertical structure phase-change memory of suitable suitability for industrialized production so far.
Retrieval finds that application number is that the Chinese patent application of 200510110783.X discloses the method that adopts chalcogenide compound nanometer material to prepare phase transformation memory device unit, and used phase transformation active layer is the chalcogenide compound film of two dimension, so power consumption is bigger.In addition, application number is the preparation method that 200410015743 Chinese patent application discloses phase-change memory unit element, this method adopts mechanical means, promptly use pressure head eyeletting on film of multiple shapes such as triangular pyramid, circular cone and different materials such as diamond, diamond, make aperture penetrate dielectric layer, the method that pointed nose contacts with the hearth electrode material, the deposit phase-change material is as active layer in aperture then, and obviously its technology is comparatively complicated.
Summary of the invention
The objective of the invention is to: propose a kind of method for preparing vertical structure phase-change memory of suitable suitability for industrialized production, thereby lay the foundation for producing the commercialization memory that is fit to PCRAM.
In order to reach above purpose, applicant is that the disclosed high density of constructing at normal temperatures of 200610085300X Chinese patent evenly distributes on the method basis of silicon nano dots, nano wire in the patent No., further go deep into experimental study, propose the method that the present invention prepares vertical structure phase-change memory, may further comprise the steps:
The first step, preparing substrate---the silicon chip of selecting n+ or p+ type single-sided polishing for use cleans the back oven dry as substrate;
Second step, plating thermal insulation layer---the thermal insulation layer of evaporation 50-100 nanometer on substrate (for example TiN titanium nitride or W tungsten thermal insulation layer);
The 3rd step, plating thin layer---the Ge-Sb-Te or the silicon antimony tellurium thin films layer of evaporation thickness 100-150 nanometer on thermal insulation layer;
The 4th step, laying template---the laying diameter is the individual layer polystyrene sphere of 50-100 nanometer on thin layer;
The 5th step, ion etching---to be attached to individual layer polystyrene sphere on the thin layer as mask, silicon substrate is carried out reactive ion etching, obtain Ge-Sb-Te or silicon antimony tellurium nano-array (preferably its top dimension less than 30 nanometers, highly be 100 ± 10 nanometers);
The 6th step, removal template---soak (for example oxolane soaked 5-10 minute) with organic solvent, remove polystyrene sphere;
The silicon dioxide of the 7th step, plating heat insulation layer---evaporation 300-500 nanometer or silicon nitride are as Ge-Sb-Te or silicon antimony tellurium nano-array insulated thermal insulating layer each other;
The 8th step, polishing polish---and polishing grinds off the surface insulation thermal insulation layer, exposes the Ge-Sb-Te or the silicon antimony tellurium nano-array termination of filling silicon dioxide or silicon nitride;
The 9th step, photoetching corrosion---the Lithographic template that will be distributed with micropore (aperture preferably is controlled at the 1-5 micron) covers polished surface, and Ge-Sb-Te or silicon antimony tellurium nano-array are carried out photoetching, makes substrate surface form the cross section and is circular column memory cell;
The tenth step, plating heat insulation layer again---the silicon dioxide layer of evaporation 300-500 nanometer or silicon nitride are as the insulated thermal insulating layer between the cylindric memory cell;
The 11 step, multiple rubbing down are put down---and polishing grinds off the surface insulation thermal insulation layer, exposes the cylindric memory cell termination of filling silicon dioxide or silicon nitride;
The 12 step, make electrode---successively at upper and lower surface evaporation metal electrode layer, and the metal electrode layer of upper surface is carried out photoetching, obtain the top electrode of required figure by the Lithographic template of above-mentioned distribution micropore (best 1 to 5 micron of aperture).
Said method of the present invention has the following advantages:
1, the nano-array minimum feature in the nano-array vertical structure phase-change memory of preparing can be less than 30 nanometers; And nano-array is filled, is surrounded by dielectric (SiO2), and the sectional area of single nano-pillar is very little, and current vertical is passed through, can produce very high current density, and because the thermal conductivity of silicon dioxide is less relatively, thereby make the heat efficiency of phase transformation active area improve, power consumption reduces;
2, can be easily cycle of forming of the condition control phase-change material nano-array of size by regulating the template polystyrene sphere and reactive ion etching, regulate pattern, size, to reach the heat efficiency of regulating phase transition storage and the purpose of power consumption;
Only need use single Lithographic template when 3, preparing nano phase change material array memory, technology is simple, avoided adopting the FIB technology with the cost costliness, compatible mutually with traditional semiconductor silicon technology-CMOS technology, the large tracts of land that is suitable for memory cell is produced in batches.
Compare for the chalcogenide compound film of two dimension with the phase transformation active layer, the present invention has adopted lattice structure, makes material all reach nanoscale on three-dimensional, thereby can reduce power consumption in application to the utmost; Compare with mechanical means eyeletting on film, the present invention has used nanosphere lithographic technique and photoetching process, with CMOS technology favorable compatibility is arranged, and technology is simple, cost of manufacture is cheap, can obtain the nano dot of live width littler (being lower than 30 nanometers).
In a word, the present invention adopts the carrier of the phase-change material of nano-array as stored information, by between electrode and phase-change material, importing suitable dielectric layer, improved the heat efficiency of phase transformation active area, make that the operating current and the power consumption of memory device are effectively reduced, and technology is simple, with low cost, thereby lays a good foundation for producing the commercialization memory that is fit to PCRAM.
Description of drawings
The present invention is further illustrated below in conjunction with accompanying drawing.
Fig. 1 is the preparation process schematic diagram of one embodiment of the invention, and wherein (1-3) are evaporation TiN and GeSbTe film on silicon substrate; (4) lay the PS bead; (5) reactive ion etching; (6) remove the PS bead; (7) steam coating silicon dioxide; (8) polishing polishes; (9) photoetching obtains cylindric memory cell; (10) evaporation heat insulation layer silicon dioxide once more; (11) polishing polishes; (12) evaporation top electrode; (13) photoetching top electrode; (14) evaporation bottom electrode.
Embodiment
Embodiment one
The method that present embodiment prepares inferior 30 nanoscale chalcogenide compound nano-dot matrix vertical structure phase-change memories may further comprise the steps as shown in Figure 1
1, preparing substrate---the silicon chip of selecting n+ or p+ type single-sided polishing for use is as substrate, and the method that at first adopts sulfuric acid+hydrogen peroxide to boil is cleaned, then with rinsed with deionized water and oven dry.
2, the plating thermal insulation layer---the TiN layer of using magnetron sputtering method (sputtering condition: pressure: 0.2Pa, underlayer temperature: 550 ℃) evaporation 50-100 nanometer is as thermal insulation layer.
3, thin layer---(condition is: vacuum degree: 2 * 10 with magnetron sputtering method in plating
-4Pa; Sputter pressure: 0.15Pa) evaporation thickness 100-150 nanometer Ge-Sb-Te or silicon antimony tellurium thin films material.
4, lay template---on Ge-Sb-Te or silicon antimony tellurium thin films, lay individual layer polystyrene sphere (diameter is 50 to 100 nanometers).
5, ion etching---utilize the individual layer polystyrene sphere (PS) that is attached to Ge-Sb-Te or silicon antimony tellurium thin films as mask, adopt carbon tetrafluoride (CF
4) or F-12 (CF
2Cl
2) or fluoroform (CHF
3) gas carried out reactive ion etching (RIE) 2-5 minute to silicon substrate, obtained top dimension less than 30 nanometers, highly be about the Ge-Sb-Te or the silicon antimony tellurium nano-array of 100 nanometers.
6, remove template---sample is put into organic solvent (for example oxolane etc.) immersion polystyrene sphere can be removed fully in 5-10 minute.
7, plating heat insulation layer---deposited by electron beam evaporation equipment (condition: vacuum degree: 4.5 * 10
-4Pa; Underlayer temperature: 50-60 ℃; Electron accelerating voltage: 6-8kV; Evaporation pressure: 3.5 * 10
-3Pa) silicon dioxide of evaporation 300-500 nano thickness (also can be silicon nitride) layer is as Ge-Sb-Te or silicon antimony tellurium nano-array insulated thermal insulating layer each other.
8, polishing polishes---and polishing grinds off the surface insulation thermal insulation layer, exposes the Ge-Sb-Te or the silicon antimony tellurium nano-array termination of filling silicon dioxide (or silicon nitride).
9, photoetching---utilize the Lithographic template that is distributed with 1 to the 5 micron aperture in aperture on it to cover polished surface, Ge-Sb-Te or silicon antimony tellurium nano-array layer (nano-array is filled by dielectric silicon dioxide) are carried out photoetching, obtain sectional area and be circular column memory cell.
10, plate heat insulation layer again---with reference to step 7, the silicon dioxide (or silicon nitride) of deposited by electron beam evaporation equipment evaporation 300-500 nano thickness layer is as the insulated thermal insulating layer of cylindric memory cell.
11, multiple rubbing down is flat---and grind off the surface insulation thermal insulation layer with the nanometer burnishing liquid polishing, expose the cylindric memory cell termination of filling silicon dioxide or silicon nitride.
12, electrode---evaporation metal nickel or tungsten are as top electrode on memory cell in making;
13, the Lithographic template that utilizes step 9 again carries out photoetching to the metal level of sample, obtains the figure of top electrode;
14, at last at the back side of sample evaporation nickel or tungsten as bottom electrode.
In addition to the implementation, the present invention can also have other execution modes.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection range of requirement of the present invention.
Claims (10)
1. method for preparing vertical structure phase-change memory may further comprise the steps:
The first step, preparing substrate---the silicon chip of selecting n+ or p+ type single-sided polishing for use cleans the back oven dry as substrate;
Second step, plating thermal insulation layer---the thermal insulation layer of evaporation 50-100 nanometer on substrate;
The 3rd step, plating thin layer---the Ge-Sb-Te or the silicon antimony tellurium thin films layer of evaporation thickness 100-150 nanometer on thermal insulation layer;
The 4th step, laying template---the laying diameter is the individual layer polystyrene sphere of 50-100 nanometers on thin layer;
The 5th step, ion etching---to be attached to individual layer polystyrene sphere on the thin layer, silicon substrate is carried out reactive ion etching, obtain Ge-Sb-Te or silicon antimony tellurium nano-array as mask;
The 6th step, removal template---soak with organic solvent, remove polystyrene sphere;
The silicon dioxide of the 7th step, plating heat insulation layer---evaporation 300-500 nanometer or silicon nitride are as Ge-Sb-Te or silicon antimony tellurium nano-array insulated thermal insulating layer each other;
The 8th step, polishing polish---and polishing grinds off the surface insulation thermal insulation layer, exposes the Ge-Sb-Te or the silicon antimony tellurium nano-array termination of filling silicon dioxide or silicon nitride;
The 9th step, photoetching corrosion---the Lithographic template that will be distributed with micropore covers polished surface, and Ge-Sb-Te or silicon antimony tellurium nano-array are carried out photoetching, makes substrate surface form the cross section and is circular column memory cell;
The tenth step, plate the silicon dioxide layer of heat insulation layer one-evaporation 300-500 nanometer or silicon nitride as the insulated thermal insulating layer between the cylindric memory cell again;
The 11 step, multiple rubbing down are put down---and polishing grinds off the surface insulation thermal insulation layer, exposes the cylindric memory cell termination of filling silicon dioxide or silicon nitride;
The 12 step, make electrode---successively at upper and lower surperficial evaporation metal electrode layer, and the metal electrode layer of upper surface is carried out photoetching, obtain the top electrode of required figure by the Lithographic template of above-mentioned distribution micropore.
2. the method for preparing vertical structure phase-change memory according to claim 1 is characterized in that: the method that adopts sulfuric acid+hydrogen peroxide to boil in the described first step is cleaned, then with rinsed with deionized water and oven dry.
3. the method for preparing vertical structure phase-change memory according to claim 2 is characterized in that: described second step is used magnetron sputtering method evaporation titanium nitride or tungsten thermal insulation layer.
4. the method for preparing vertical structure phase-change memory according to claim 3 is characterized in that: the sputtering condition of described magnetron sputtering method is pressure 0.2Pa, 550 ℃ of underlayer temperatures.
5. the method for preparing vertical structure phase-change memory according to claim 3 is characterized in that: described the 3rd step is used magnetron sputtering method evaporation nanometer Ge-Sb-Te or silicon antimony tellurium thin films layer.
6. the method for preparing vertical structure phase-change memory according to claim 5 is characterized in that: the sputtering condition of described magnetron sputtering method is a vacuum degree 2 * 10
-4Pa; Sputter pressure 0.15Pa.
7. the method for preparing vertical structure phase-change memory according to claim 6 is characterized in that: described the 5th step adopts one of carbon tetrafluoride, F-12 or fluoroform that silicon substrate is carried out reactive ion etching.
8. according to claim 1 or the 7 described methods that prepare vertical structure phase-change memory, it is characterized in that: in described the 5th step top dimension of Ge-Sb-Te or silicon antimony tellurium nano-array less than 30 nanometers, highly be 100 ± 10 nanometers.
9. the method for preparing vertical structure phase-change memory according to claim 8 is characterized in that: described the 7th step is adopted electron beam evaporation equipment evaporation insulated thermal insulating layer, and process conditions are controlled to be vacuum degree 4.5 * 10
-4Pa; Underlayer temperature 50-60 ℃; Electron accelerating voltage 8kV; Evaporation pressure 3.5 * 10
-3Pa.
10, the method for preparing vertical structure phase-change memory according to claim 9 is characterized in that: the micropore size in described the 9th step is the 1-5 micron.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136548A (en) * | 2010-12-31 | 2011-07-27 | 中国科学院上海微系统与信息技术研究所 | Dry etching method for phase-change materials |
| CN102427024A (en) * | 2011-12-15 | 2012-04-25 | 复旦大学 | Preparation method of metal-semiconductor contact structure with optimized process |
| CN102543690A (en) * | 2012-01-09 | 2012-07-04 | 复旦大学 | Method for optimizing metal half contact structure by level de-pinning on local surface of N-type semi-conductor |
| CN103296202A (en) * | 2012-03-02 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory and manufacturing method thereof |
| CN104037069A (en) * | 2014-06-16 | 2014-09-10 | 曲阜师范大学 | Method for self-assembling and preparing high-density nanometer phase change structure |
| CN111367146A (en) * | 2020-04-17 | 2020-07-03 | 苏州科技大学 | Nano photoetching method of phase change-thermal decomposition type composite photoresist |
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| KR100674144B1 (en) * | 2006-01-05 | 2007-01-29 | 한국과학기술원 | Phase change memory using carbon nano tube and method for fabricating thereof |
| CN101226990A (en) * | 2008-02-04 | 2008-07-23 | 中国科学院上海微系统与信息技术研究所 | Oxide heat insulation layer for reducing phase-change memory cell power consumption and implementation method thereof |
| CN100569631C (en) * | 2008-03-20 | 2009-12-16 | 南京大学 | A kind of method for preparing alloy phase change material nano-dot matrix |
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| CN102136548A (en) * | 2010-12-31 | 2011-07-27 | 中国科学院上海微系统与信息技术研究所 | Dry etching method for phase-change materials |
| CN102427024A (en) * | 2011-12-15 | 2012-04-25 | 复旦大学 | Preparation method of metal-semiconductor contact structure with optimized process |
| CN102543690A (en) * | 2012-01-09 | 2012-07-04 | 复旦大学 | Method for optimizing metal half contact structure by level de-pinning on local surface of N-type semi-conductor |
| CN103296202A (en) * | 2012-03-02 | 2013-09-11 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory and manufacturing method thereof |
| CN103296202B (en) * | 2012-03-02 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory and manufacturing method thereof |
| CN104037069A (en) * | 2014-06-16 | 2014-09-10 | 曲阜师范大学 | Method for self-assembling and preparing high-density nanometer phase change structure |
| CN111367146A (en) * | 2020-04-17 | 2020-07-03 | 苏州科技大学 | Nano photoetching method of phase change-thermal decomposition type composite photoresist |
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