CN101475140B - Giant piezoresistance effect generated by nanometer scale interface trap and method for manufacturing the same - Google Patents
Giant piezoresistance effect generated by nanometer scale interface trap and method for manufacturing the same Download PDFInfo
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- CN101475140B CN101475140B CN2009100455561A CN200910045556A CN101475140B CN 101475140 B CN101475140 B CN 101475140B CN 2009100455561 A CN2009100455561 A CN 2009100455561A CN 200910045556 A CN200910045556 A CN 200910045556A CN 101475140 B CN101475140 B CN 101475140B
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Abstract
The invention relates to huge piezoresistive effect generated by interface trap action in nano scale and a method for manufacturing a nano huge piezoresistor, and belongs to the field of micro electromechanical systems. The huge piezoresistor is specifically characterized in that the thickness of the piezoresistor is nano-scale, and the piezoresistive effect comes from electron trap effect at the interface of silicon and silicon dioxide. The prior piezoresistive effect of the silicon comes from the change of mobility ratio of stressed current carriers, while the huge piezoresistance in the nano scale is generated by changing the concentration of the current carriers under the electron trap effect at the interface of the silicon and the silicon dioxide by the action of stress. Along with the reduction of the thickness of the piezoresistor, the interface effect accounts for larger proportion, and the piezoresistive effect generated by the interface trap is more obvious. The piezoresistor manufactured by the method has the advantages of large piezoresistive coefficient, same resistance value change of transverse piezoresistance and the longitudinal piezoresistance, and compatibility with a semiconductor process, and can be applied to sensors and micro electromechanical systems.
Description
Technical field
The present invention relates to the huge pressure drag of interface trap effect generation under the nanoscale and the preparation method of the huge pressure drag of nanometer, belong to the microelectromechanical systems field.
Background technology
1954, U.S. scientist Smith found the piezoresistive effect (C.S.Smith, " Piezoresistance Effect in Germanium and Silicon, " Physical Review, vol.94, p.42,1954.) of semi-conducting material.Subsequently, scientist has carried out deep research to the piezoresistive effect of silicon materials.Because the silicon pressure drag has high piezoresistance coefficient and makes compatible advantage with semiconductor, the piezoresistive effect of silicon materials is widely used in the sensor of microelectromechanical systems as a kind of detection mode at present, as pressure sensor, the biochemical sensor of acceleration transducer and various cantilever beam structures.
Though the piezoresistance coefficient of silicon improves a lot (be metal strain plate more than 100 times) with respect to metal strain plate, the variation of its resistance value still very little (usually less than 5%).In recent years, along with the development of nanosecond science and technology, scientist wishes to obtain higher piezoresistance coefficient by nano effect.People such as yellow Qingan County study the piezoresistive effect of P type nano thickness resistance, yet theoretical result of calculation shows piezoresistance coefficient and can only improve doubly (J.Zhang of 3-4, Q.a.Huang, H.Yu, and S.Lei, " A Theoretical Study ofthe Piezoresistivity of a p-Type Silicon Nanoplate; " Chinese Journal ofSemiconductors, vol.29, pp.970-974,2008.).For the nanometer pressure drag of N type, result of calculation shows that the piezoresistive effect that reduces along with thickness goes to zero.In view of this, nano effect can not improve the piezoresistive effect of silicon materials to a great extent.
In the microelectromechanical systems field, nearly all silicon pressure drag resistance is all wrapped up with external environment by silica and insulate.Have a large amount of electron traps at the interface of silicon and silica, these traps can be captured the electronics in the silicon layer, thereby change the number of carrier.Studies show that, mechanical stress can play the effect that influences the interface electron trap, thereby by changing electric conductivity (J.Boch, the D.M.Fleetwood of the carrier concentration change silicon pressure drag in the silicon layer, R.D.Schrimpf, R.R.Cizmarik, andF.Saigne, " Impact of mechanical stress on total-dose effects in bipolar ICs; " IEEE Transactions on Nuclear Science, vol.50, pp.2335-2340, Dec 2003.).The present invention attempts to utilize the electron trap effect at silicon and silica interface, has realized huge piezoresistive effect under nanoscale.
Summary of the invention
The objective of the invention is to the huge piezoresistive effect of interface trap effect generation under the nanoscale and the preparation method of the huge pressure drag of nanometer.
The technical solution adopted in the present invention is to utilize the bigger characteristics of interfacial area relative volume of nano thin-layer pressure drag, changes the interface electron trap by mechanical stress and acts on the huge piezoresistive effect of realization under the nanoscale.Silicon and silica have a large amount of electron traps at the interface, these electron traps can be from silicon layer a trapped electron or electronics of capturing is discharged in the silicon layer, thereby change the concentration of carrier in the silicon layer.As shown in Figure 1, for N type silicon, under the mechanical stress effect, the ability of interface electron trap trapped electron strengthens near the conduction band, thereby has portions of electronics to transfer on the interface energy level from conduction band, causes the number of silicon conduction band electron to reduce, the concentration of carrier reduces, and resistance value increases.As shown in Figure 2, for P type silicon, under the mechanical stress effect, the ability of interface electron trap trapped electron strengthens near the valence band, thereby have portions of electronics to transfer on the interface energy level from valence band, correspondence forms the hole in valence band, cause the data in hole on the silicon valence band to increase, the concentration of carrier increases, and resistance value reduces.For traditional piezoresistive effect, the thickness of silicon is very big, and the carrier number in the silicon layer of pressure drag is a lot, and the number of variations of the carrier that interfacial effect causes is very little, can ignore, so traditional piezoresistive effect is mainly derived from the variation of carrier mobility.Yet for the piezoresistive effect of nano thickness, because the thickness of pressure drag is very little, the number of its carrier is less, but the size at interface is constant substantially, thereby the interface trap effect is constant substantially.Under the mechanical stress effect, the variation of the carrier concentration that interface electron trap effect causes cannot be ignored, thereby changes the resistance value of pressure drag, the huge piezoresistive effect that interface trap produces occurred.Because trap effect is not substantially with the varied in thickness of silicon, and the number of carrier reduces along with the less of thickness, so pressure drag is thin more, it is just obvious more that the carrier number purpose that interface trap causes changes, and the piezoresistive effect that interface trap produces is also just obvious more.
Purpose of the present invention realizes by following manufacture craft:
What (1) the present invention adopted is soi wafer, and the thickness of surface silicon is 100nm-400nm;
(2) surface silicon of soi wafer is carried out repeatedly oxidation, surface silicon is thinned to desired thickness, photoetching keeps the silica in lead-in wire zone, resistance two ends after each oxidation, erode other regional silica, the oxidation post-etching falls silica all on the silicon chip the last time, comprises the silica at resistance two ends;
(3) thermal oxide generates the silica of 60-100nm, and the figure of photoetching resistance is 25% tetramethyl oxyammonia solution wet etching formation resistance with mass percentage concentration;
(4) thermal oxide generates the oxide layer of 80-120nm, makes the side and the external environment insulation of resistance;
(5) ion injects, and injects phosphonium ion for N type pressure drag, injects the boron ion for P type pressure drag;
(6) under 950-1050 ℃ of temperature and nitrogen protection, annealed 25-40 minute;
So far, the huge pressure drag under the nanoscale completes, and for the test that can go between, need do following technology:
(7) photoetching forms fairlead, falls the silica in fairlead zone with the silicon dioxide etching corrosion of buffering;
(8) splash-proofing sputtering metal, photoetching corrosion forms pin interconnection;
(9) scribing, pressure welding.
In described preparation technology, surface silicon is carried out attenuate by oxidation repeatedly.Meeting consume silicon in the process of generation silica can be controlled the thickness of excess silicon by the thickness of control oxidation, thereby determines the thickness of pressure drag.
The silica that in described preparation technology, keeps lead-in wire zone, resistance two ends during attenuate; the lead-in wire zone was owing to there is protect oxide layer when purpose was oxidation once more; newly-generated oxide layer will be lacked than other zones; so just realized the silicon layer thickness of the silicon layer thickness in lead-in wire zone, guaranteed that metal lead wire and the silicon pressure drag made form good electrical contact greater than resistance region.
The oxide layer of removing All Ranges in described preparation technology behind the attenuate is even for the oxidated layer thickness of pressure drag upper surface before ion is injected, and guarantees the quality that ion injects.
In sum, the huge pressure drag that interface trap produces under the nanoscale provided by the invention is characterized in that:
(1) thickness of pressure drag is in nanometer scale, and piezoresistive effect derives from the electron trap effect at silicon and silica interface;
(2) silicon layer thickness of described pressure drag resistance is at nanometer scale (below the 20nm);
(3) silicon layer of described pressure drag resistance forms the interface of silicon and silica by all or part of parcel of silica;
(4) under the mechanical stress effect, changes in resistance is to derive from the carrier concentration variation that interface electron trap effect causes, has identical effect for longitudinal electrical resistance and lateral resistance, and promptly longitudinal electrical resistance and lateral resistance all increase or all reduce;
(5) piezoresistance coefficient is bigger than the piezoresistance coefficient of traditional pressure drag, and the piezoresistance coefficient of the N type nanometer pressure drag that 13nm is thick can reach 400 * 10
-11/ Pa, the piezoresistance coefficient of the P type nanometer pressure drag that 9nm is thick can reach-400 * 10
-11/ Pa;
(6) under tensile stress, interface electron trap effect reduces the number of electrons of N type silicon pressure drag conduction band, and it is big that resistance value becomes, vertically piezoresistance coefficient and laterally piezoresistance coefficient all be on the occasion of;
(7) under tensile stress, interface electron trap effect increases the hole number of P type silicon pressure drag valence band, and resistance value diminishes, and vertically piezoresistance coefficient and horizontal piezoresistance coefficient all are negative value.
This shows that the huge pressure drag of the nanometer of utilizing the present invention to make has the following advantages:
(1) utilized the interfacial effect of silicon and silica, the piezoresistance coefficient that obtains is than the big order of magnitude of body silicon.The numerical value of the piezoresistance coefficient of tradition pressure drag is greatly about 30 * 10
-11/ Pa, the numerical value of the piezoresistance coefficient of the huge pressure drag of nanometer can reach about 400 * 10
-11/ Pa;
(2) change of resistance derives from the change of carrier concentration, so vertically pressure drag is with laterally the pressure drag resistance change is identical, promptly vertically the resistance value of pressure drag and horizontal pressure drag all increases or all reduces;
(3) thinner by oxidation to the surface silicon of soi wafer, can make the thickness of pressure drag reach nanometer scale;
(4) in thinning process, resistance two ends lead district is protected, when resistance is very thin, made the silicon in resistance lead district enough thick, guaranteed that metal lead wire and the good of silicon are connected;
(5) preparation method provided by the invention and semiconductor technology compatibility can apply in sensor and the microelectromechanical systems.
Description of drawings
The invention will be further described below in conjunction with accompanying drawing:
Fig. 1 is the interface electron trap effect schematic diagram of N type pressure drag, Fig. 1-the 1st wherein, and stress T is 0 o'clock electron distributions figure, Fig. 1-2 is that stress T is not 0 o'clock electron distributions figure
Fig. 2 is the interface electron trap effect schematic diagram of P type pressure drag, Fig. 2-the 1st wherein, and stress T is 0 o'clock the electronics and the distribution map in hole, Fig. 2-the 2nd, stress T are not 0 o'clock the electronics and the distribution map in hole
Fig. 3 is the schematic diagram of soi wafer among the embodiment
Fig. 4 is the pressure drag schematic diagram that forms on silicon chip behind the oxidation attenuate among the embodiment
Fig. 5 carries out the schematic diagram that ion injects to pressure drag among the embodiment
Fig. 6 is the schematic diagram of the pressure drag finished among the embodiment
Fig. 7 is the graph of a relation of the huge pressure drag resistance value of N type nanometer with mechanical stress
Fig. 8 is the graph of a relation of N type piezoresistance coefficient along with pressure drag thickness
Fig. 9 is the graph of a relation of the huge pressure drag resistance value of P type nanometer with mechanical stress
Figure 10 is the graph of a relation of P type piezoresistance coefficient along with pressure drag thickness
Numeral is represented respectively among the figure:
1---the silicon conduction band; 2---the silicon valence band; 3---donor band; 4---the interface trap near conduction band can be with; 5---acceptor band; 6---the interface trap near valence band can be with; 7---silicon; 8---silica; 9---the silicon of doping; 10---aluminum conductor.
The specific embodiment
Further set forth the huge piezoresistive effect of nanoscale interfacial effect generation provided by the invention and the substantive distinguishing features and the marked improvement of manufacture method thereof below by specific embodiment.But the present invention only limits to embodiment by no means.
Embodiment 1
1. use the soi wafer of (100), the thickness of its surface silicon is 275nm, and the thickness of buried regions silica is 1.25 μ m, as shown in Figure 3;
2. the dry method thermal oxide generates the oxide layer of 180nm, and the oxide layer in photoetching reserved lead district is removed other regional oxide layers;
3. the dry method thermal oxide generates the oxide layer of 85nm, and the oxide layer in photoetching reserved lead district is removed other regional oxide layers;
4. the dry method thermal oxide generates the oxide layer of 170nm, removes all oxide layers;
5. the dry method thermal oxide generates the oxide layer of 60nm, the photoetching resistance pattern, and the silicon dioxide etching corrosion oxide layer of buffering to buried silicon dioxide layer, forms resistance pattern with tetramethyl oxyammonia solution corrosion silicon;
6. the dry method thermal oxide generates the oxide layer of 50nm, the side of protective resistance and external environment insulation, as shown in Figure 4;
7. phosphonium ion injects, and injects energy 75keV, implantation dosage 2 * 10
14Cm
-3, as shown in Figure 5;
8. the phosphorus master expands, and 1000 ℃, nitrogen protection, 30 minutes;
9. photoetching corrosion forms fairlead;
10. the aluminium of sputter 800nm, photoetching form the aluminum steel interconnection, as shown in Figure 6;
11. aluminium alloy, 450 ℃, nitrogen and hydrogen shield, 30 minutes;
12. scribing, pressure welding;
13. pressure drag is measured, measurement result is as shown in Figure 7 with shown in Figure 8.
Utilize the silicon layer thickness of the huge pressure drag of the N type nano thickness that above method makes to be 13nm, the change in resistance of its longitudinal electrical resistance and lateral resistance with the relation of stress as shown in Figure 7, the resistance of longitudinal electrical resistance and lateral resistance all increases along with the increase of tensile stress.The variation of resistance value surpasses 65%, and the numerical value of corresponding piezoresistance coefficient reaches 450 * 10
-11/ Pa.
By the thickness of control oxidation attenuate, can make the pressure drag of a series of different-thickness, obtain piezoresistance coefficient as shown in Figure 8 with the graph of a relation of varied in thickness, along with reducing of thickness, the interface trap effect is obvious more.When thickness was reduced to 13nm, the piezoresistance coefficient of the huge pressure drag of nanometer that obtains reached 450 * 10
-11/ Pa is bigger one more than the order of magnitude than traditional piezoresistance coefficient.
1. use the soi wafer of (100), the thickness of its surface silicon is 275nm, and the thickness of buried regions silica is 1.25 μ m, as shown in Figure 3;
2. the dry method thermal oxide generates the oxide layer of 180nm, and the oxide layer in photoetching reserved lead district is removed other regional oxide layers;
3. the dry method thermal oxide generates the oxide layer of 85nm, and the oxide layer in photoetching reserved lead district is removed other regional oxide layers;
4. the dry method thermal oxide generates the oxide layer of 170nm, removes all oxide layers;
5. the dry method thermal oxide generates the oxide layer of 100nm, the photoetching resistance pattern, and BOE corrosion oxidation layer, TMAH corrodes to buried silicon dioxide layer, forms resistance pattern;
6. the dry method thermal oxide generates the oxide layer of 80nm, the side of protective resistance and external environment insulation, as shown in Figure 4;
7. the boron ion injects, and injects energy 50keV, implantation dosage 2.6 * 10
14Cm
-3, as shown in Figure 5;
8. the boron master expands, and 1000 ℃, nitrogen protection, 30 minutes;
9. photoetching corrosion forms fairlead;
10. the aluminium of sputter 800nm, photoetching form the aluminum steel interconnection, as shown in Figure 6;
11. aluminium alloy, 450 ℃, nitrogen and hydrogen shield, 30 minutes;
12. scribing, pressure welding;
13. pressure drag is measured, measurement result such as Fig. 9 and shown in Figure 10;
Utilize the silicon layer thickness of the huge pressure drag of the P type nano thickness that above method makes to be 9nm, the change in resistance of its longitudinal electrical resistance and lateral resistance with the relation of stress as shown in Figure 9, the resistance of longitudinal electrical resistance and lateral resistance all reduces along with the increase of tensile stress.The variation of resistance value surpasses-50%, and the numerical value of corresponding piezoresistance coefficient reaches-400 * 10
-11/ Pa.
By the thickness of control oxidation attenuate, can make the pressure drag of a series of different-thickness, obtain piezoresistance coefficient as shown in figure 10 with the graph of a relation of thick variation, along with reducing of thickness, the interface trap effect is obvious more.When thickness was reduced to 9nm, the piezoresistance coefficient of the huge pressure drag of nanometer that obtains reached-400 * 10
-11/ Pa is bigger one more than the order of magnitude than traditional piezoresistance coefficient.
Claims (10)
1. the huge pressure drag that interface trap produces under the nanoscale is characterized in that described huge pressure drag is under the mechanical stress effect, is changed by P type or N type silicon and silica electron trap effect at the interface that the concentration of carrier produces; The P type of the huge pressure drag of described generation or N type silicon layer thickness are the following nanometer scale of 20nm.
2. the huge pressure drag that produces by interface trap under the described nanoscale of claim 1, the N type or the P type silicon layer that it is characterized in that producing huge pressure drag are by all or part of parcel of silica, form the interface of N type or P type silicon and silica.
3. by the huge pressure drag of interface trap generation under claim 1 or the 2 described nanoscales, it is characterized in that:
(1) for N type silicon, under the mechanical stress effect, the ability of interface electron trap trapped electron strengthens near the conduction band, thereby has portions of electronics to transfer on the interface energy level from conduction band, causes the number of silicon conduction band electron to reduce, and the concentration of carrier reduces, and resistance value increases;
(2) for P type silicon, under stress, the ability of interface electron trap trapped electron strengthens near the valence band, have portions of electronics to transfer on the interface energy level from valence band, correspondence forms the hole in valence band, cause the data in hole on the silicon valence band to increase, the concentration of carrier increases, and resistance value reduces.
4. the huge pressure drag that produces by interface trap under the described nanoscale of claim 1 is characterized in that the variation of carrier concentration has identical effect to longitudinal electrical resistance or lateral resistance, also promptly longitudinal electrical resistance or lateral resistance is all increased or reduces.
5. by the huge pressure drag of interface trap generation under the described nanoscale of claim 1, it is characterized in that:
(1) for vertical piezoresistance coefficient of N type silicon pressure drag and laterally piezoresistance coefficient be on the occasion of;
(2) vertical piezoresistance coefficient and the horizontal piezoresistance coefficient for P type silicon pressure drag is negative value.
6. make the method for the huge pressure drag that interface trap produces under the nanoscale as claimed in claim 1 or 2, it is characterized in that step is:
What (1) adopt is soi wafer, and the thickness of surface silicon is 100nm-400nm;
(2) surface silicon of soi wafer is carried out repeatedly oxidation surface silicon is thinned to desired thickness, photoetching keeps the silica in lead-in wire zone, resistance two ends after each oxidation, erode other regional silica, the oxidation post-etching falls silica all on the silicon chip the last time, comprises the silica at resistance two ends;
(3) thermal oxide generates the silica of 60-100nm, and the figure of photoetching resistance is 25% tetramethyl oxyammonia solution wet etching formation resistance with mass percentage concentration;
(4) thermal oxide generates the oxide layer of 80-120nm, makes the side and the external environment insulation of resistance;
(5) ion injects, and injects phosphonium ion for N type pressure drag, injects the boron ion for P type pressure drag;
(6) under 950-1050 ℃ of temperature and nitrogen protection, anneal.
7. by the described preparation method of claim 6, it is characterized in that the described repeatedly oxidation of step (2) is a thickness by oxidation to the surface silicon attenuate, the thickness of control excess silicon, thereby the thickness of decision pressure drag.
8. by the described preparation method of claim 6, the silicon layer thickness in the zone that it is characterized in that going between electrically contacts the metal lead wire of making and the formation of silicon pressure drag greater than the silicon layer thickness of resistance region.
9. by the described preparation method of claim 6, it is characterized in that annealing time is 25-40 minute.
10. by right 6 described preparation methods, it is characterized in that the piezoresistance coefficient big order of magnitude of the piezoresistance coefficient of the huge pressure drag of nanometer made than body silicon.
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| CN2572374Y (en) * | 2002-12-20 | 2003-09-10 | 上海鸿宇纳米科技发展有限公司 | Semiconductor pressure sensor |
| US20080068000A1 (en) * | 2006-09-19 | 2008-03-20 | Igor Bargatin | Thermoelastic self-actuation in piezoresistive resonators |
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| CN2572374Y (en) * | 2002-12-20 | 2003-09-10 | 上海鸿宇纳米科技发展有限公司 | Semiconductor pressure sensor |
| US20080068000A1 (en) * | 2006-09-19 | 2008-03-20 | Igor Bargatin | Thermoelastic self-actuation in piezoresistive resonators |
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