CN101471251A - Methods for forming quantum dots and forming gate using the quantum dots - Google Patents
Methods for forming quantum dots and forming gate using the quantum dots Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 52
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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Abstract
Methods for forming a gate using quantum dots are disclosed. More particularly, the present invention relates to a method for forming quantum dots for fabrication of an ultrafine semiconductor device comprising a gate with quantum dots. The present invention is capable of forming quantum dots in uniform sizes and at uniform intervals so as to achieve an electrically stable device.
Description
The cross reference of related application
The application requires the priority of the korean patent application submitted on December 26th, 2007 10-2007-0137081 number, and its full content is hereby expressly incorporated by reference.
Technical field
The present invention relates to semiconductor technology.More specifically, the present invention relates to a kind of quantum dot that is used to form to be used to make method and a kind of method that is used to use this quantum dot formation grid of advanced micro devices device.
Background technology
Along with the development of the semiconductor device of the big capacity storage capability with high-speed computation ability and growth, manufacturing technology has been developed so that make the semiconductor device with improved integrated level, reliability and response speed.
An example of general semiconductor device is a flash memory, its by the total grid (general gate) that comprises the tunnel dielectric layer (tunneling dielectric layer) that is formed on the semiconductor device substrates, be formed at floating boom (floating gate) on the tunnel dielectric layer, be formed at oxide-nitride thing-oxide (ONO) layer on the floating boom and be formed at that control grid (control gate) on the ONO layer forms.In the at present known in the art device, the minimum vertical thickness of total grid is limited, makes it be difficult to form raceway groove in total grid of said structure.Unfortunately, this restriction integrated level that hindered device.In addition, the thickness requirement of total grid structure can not be applied to embedded flash memory.
In order to alleviate these difficulties, advised recently the substitute of silicon (Si) quantum dot as floating boom.For example, Fig. 1 shows the cross-sectional view of the structure of the at present known in the art common traditional grid that contains quantum dot.With reference to figure 1, on Semiconductor substrate 1, form separator 2 so that the active area and the passive region of definition Semiconductor substrate 1.Next, vapour deposition oxide on the whole surface of Semiconductor substrate 1, thus form first grid dielectric layer 3, or tunnel dielectric layer.By will to first grid dielectric layer 3, forming second grid dielectric layer 4 such as the nitride vapour deposition of SiON.This second grid dielectric layer 4 comprises too much silicon atom, and it is easy to combine so that form the Si-O structure with oxygen atom.Second grid dielectric layer 4 is formed than the bed thickness that comprises quantum dot that forms in subsequent process.
In addition, the conductive metal layer (not shown) is deposited on the second grid, and this conductive metal layer is carried out heat treatment.Because heat treatment, the metallic atom of the silicon atom of second grid dielectric layer 4 and conductive metal layer (not shown) is moved to close to each other, thereby forms quantum dot 6 on second grid dielectric layer 4.Then, remove the conductive metal layer (not shown), and gate material 5 is deposited on the second grid dielectric layer 4 that comprises quantum dot 6.
Then, form gate pattern, and form source electrode and drain electrode at the place, bottom of the Semiconductor substrate 1 of the position of contiguous this grid by carrying out etch processes.Therefore, finish structure to the grid of semiconductor device.
In addition, although top description according to conventional method, makes the dielectric layer insulation with quantum dot by the dielectric material such as oxide or nitride, vapour deposition is used to control the grid polycrystalline silicon (gate poly) of grid then.
In this structure, need form quantum dot with consistent spacing with the size of unanimity.Yet this is difficult to accomplish, because conventional method typically uses cohesion (agglomeration) to form quantum dot by vapour deposition amorphous polysilicon (amorphous poly) and by Technology for Heating Processing, make to be difficult in and realize consistent spacing between the quantum dot.
Summary of the invention
Therefore, the present invention is intended to form quantum dot and uses this quantum dot to form the method for grid, and these methods have been avoided one or more problems, restriction or the shortcoming of correlation technique fully.
The purpose of this invention is to provide a kind of method that is used to form the grid that comprises quantum dot, these quantum dots form so that realize electric stabilizing device with consistent shape with the spacing of unanimity.
In order to reach these purposes and other advantages, and according to purpose of the present invention, one aspect of the present invention is a kind of method that is used to form the grid that comprises quantum dot.This method comprises: form the photoresist pattern on wafer surface; By making the etch processes of pattern execution with photoresist spacing with unanimity on wafer surface form a plurality of little holes (micro pit); Be formed with formation silicon dielectric layer on the wafer surface in little hole; Conductive metal deposition layer on the silicon dielectric layer, and to this conductive metal layer execution heat treatment; Form quantum dot by the metallic atom of on the silicon dielectric layer, arranging conductive metal layer with corresponding position, little hole; Remove conductive metal layer from the silicon dielectric layer that is formed with quantum dot; On the silicon dielectric layer, form dielectric layer; And on this dielectric layer, form grid polycrystalline silicon.
Another aspect of the present invention is a kind of method that is used to use quantum dot formation grid, is included in and forms the photoresist pattern on the wafer surface in the unit area; By making the etch processes of pattern execution with photoresist spacing with unanimity on wafer surface form a plurality of little holes; Be formed with formation first dielectric layer on the wafer surface in little hole; Silica-based second dielectric layer of deposition on first dielectric layer; Conductive metal deposition layer and conductive metal layer carried out heat treatment on second dielectric layer; Form quantum dot by the metallic atom of on second dielectric layer, arranging conductive metal layer with corresponding position, little hole; Remove conductive metal layer from second dielectric layer that is formed with quantum dot; On second dielectric layer, form dielectric layer; And on this dielectric layer, form grid polycrystalline silicon.
Another aspect of the present invention is a kind of method that is used to use a plurality of quantum dots formation grids, is included in and forms first dielectric layer on the wafer surface in the unit area; On first dielectric layer, form the photoresist pattern; By making the etch processes of pattern execution with photoresist spacing with unanimity on first dielectric layer form a plurality of little holes; On the surface of first dielectric layer that is formed with little hole, form seed crystal silicon layer (seed Si layer); Conductive metal deposition layer and conductive metal layer carried out heat treatment on the seed crystal silicon layer; Form quantum dot by the metallic atom of on the seed crystal silicon layer, arranging conductive metal layer with corresponding position, little hole; Remove conductive metal layer from the seed crystal silicon layer that is formed with quantum dot; On the seed crystal silicon layer, form dielectric layer; And on this dielectric layer, form grid polycrystalline silicon.
Other advantages of the present invention, purpose and feature, a part will be set forth hereinafter, and a part is by to hereinafter analysis, is conspicuous for the ordinary skill in the art or can obtains from enforcement of the present invention.The structure that can pass through to particularly point out in the specification write and claim and the accompanying drawing realizes and reaches purpose of the present invention and other advantages.
Be understandable that above-mentioned describe, in general terms of the present invention and the following detailed description all are exemplary with illustrative, and aim to provide further explanation as the present invention for required protection.
Description of drawings
Accompanying drawing (it is involved to provide a further understanding of the present invention and the part that is merged in and constitutes the application), accompanying drawing show (a plurality of) of the present invention embodiment, and are used from specification one and set forth principle of the present invention.In the accompanying drawings:
Fig. 1 is the cross-sectional view that the structure of traditional grid of using quantum dot is shown;
Fig. 2 illustrates according to the embodiment of the invention and is used in the photoresist pattern that produces the hole that is used to form quantum dot;
Fig. 3 illustrates according to the embodiment of the invention according to the wafer surface after the pattern etching of Fig. 2; And
Fig. 4 illustrates according to the embodiment of the invention and is formed at quantum dot in the Wei Keng district.
Embodiment
Extra purpose, feature and advantage are from below in conjunction with becoming apparent the detailed description of preferred embodiment of accompanying drawing.
Structure and operation now with reference to the preferred embodiments of the present invention.In addition, what can be expressly understood is, only describes structure and operation in this specification by example, and not as limitation of the scope of the invention.
Hereinafter, describe in detail according to the method that is used to form quantum dot of the embodiment of the invention with reference to the accompanying drawings and be used to use this quantum dot to form the method for grid.
At first, on wafer, form separator so that the definition unit zone.Then, as shown in Figure 2, photoresist pattern 20 is formed with the pattern that is designed to form with the spacing of unanimity little hole on wafer surface.Fig. 2 illustrates the photoresist pattern that is used to produce the hole that is used to form quantum dot according to the embodiment of the invention.Photoresist pattern 20 comprises a plurality of openings, is used for exposing wafer surface with the spacing of unanimity, so that form the hole pattern with the spacing distribution of unanimity.
In an example shown in Fig. 2, patterns of openings can comprise the open region 10 with diamond shape, and it spreads all over the spacing arrangement of wafer surface with unanimity.
Next, make the etch processes of pattern execution with photoresist so that produce a plurality of little holes 30, this spacing of cheating slightly with unanimity is distributed on the wafer surface, as shown in Figure 3.More specifically, in one embodiment, can carry out Secco etching (Secco etching) so that form little hole 30.In such an embodiment, such as comprising KON, the Secco etchant of the compound solution of NaOH etc. can be used as etchant.Therefore, on the layer in the unit area of wafer or on the wafer, form little hole 30.In the preferred embodiment that uses the Secco etchant, this etchant produces the pattern that is used for little hole 30 by crystallization process (crystallization process).
Fig. 3 shows the wafer surface of the pattern that uses Fig. 2 after etched.Here, the size in little hole 30 has width that is less than or equal to 10nm and the degree of depth that is less than or equal to 10nm.In the present embodiment, adjustment comprises the condition of etch temperature and time, thereby makes the width and the degree of depth in hole 30 all be less than or equal to 10nm.Yet this condition is not limited to special value, therefore will omit the explanation about instantiation in this article.
Next, as shown in Figure 3, on wafer, form silicon (Si) dielectric layer that will be formed with quantum dot thereon with little hole 30.
Conductive metal deposition layer on the silicon dielectric layer, and to wafer execution heat treatment.During this technology, the silicon atom of silicon dielectric layer and the metallic atom of conductive metal layer move relative to each other, and a plurality of quantum dots 40 are formed on the silicon dielectric layer.More specifically, the metallic atom of conductive metal layer is injected on the silicon dielectric layer and is formed in the corresponding position, position in the little hole 30 on the wafer surface.Therefore, form a plurality of quantum dots 40 as shown in Figure 4.
Then, remove conductive metal layer from the silicon dielectric layer that is formed with quantum dot 40.
Then, use dielectric material to make silicon dielectric layer insulation with quantum dot such as oxide or nitride.Then, on dielectric material, form the control grid so that form grid with quantum dot 40.
In the foregoing description, although little hole 30 is formed on the wafer surface, the present invention is not limited to this structure.Therefore, can on other layers, form little hole so that can form quantum dot on each layer at other.
For example, can with such as the dielectric layer of tunnel oxide at first vapour deposition on wafer surface, and can on the surface of dielectric layer, form as shown in Figure 2 photoresist pattern so that on the surface of dielectric layer, form little hole according to the photoresist pattern.
According to another example, on wafer surface, form little hole, and will be such as the dielectric layer vapour deposition of tunnel oxide to the wafer with the little hole that forms thereon.Then, can on dielectric layer, be formed for forming the silicon dielectric layer of quantum dot.
Hereinafter, will a kind of method that forms quantum dot on floating boom be described in more detail.
At first, on wafer, be formed for the separator in definition unit zone.Then, form the photoresist pattern of the pattern shown in Fig. 2 on the wafer surface in cellular zone, so that form little hole with the spacing of unanimity.Then, make with photoresist pattern carry out etch processes, be distributed in little hole on the wafer surface so that form spacing with unanimity.Then, by the oxide vapour deposition is formed tunnel dielectric layer to the wafer that is formed with little hole.
After this, by will on tunnel dielectric layer, forming silica-based floating boom, and conducting metal is deposited on the floating boom such as Si oxide or the silicon nitride vapour deposition of SiON.
Then, if carry out heat treatment about wafer, then the metallic atom of the silicon atom of floating boom and conductive metal layer moves relative to each other.More particularly, the metallic atom of conductive metal layer is injected in the floating boom, and with the metallic atom that injects be arranged on the floating boom with wafer on corresponding position, little hole.Therefore, on floating boom, form quantum dot with corresponding with little hole.
As shown in Figure 4, all quantum dots are arranged in the zone in little hole, and this is because therefore the stress maximum in little hole in the position corresponding to little hole cohesion takes place.Fig. 4 shows the state that forms quantum dot in the zone in little hole.
Next, from the floating boom that is formed with quantum dot, remove conductive metal layer.Then, on floating boom, form as mentioned above after the quantum dot, by to floating boom, making the floating boom insulation oxide or nitride vapour deposition so that make other grid structures.Then, vapour deposition is used to control the grid polycrystalline silicon of grid, thereby finishes the grid structure of using quantum dot.
Hereinafter, another example that forms quantum dot will be described in detail.At first, on wafer, be formed for the separator in definition unit zone.Next, by the oxide vapour deposition is formed tunnel dielectric layer to wafer.Then, form the photoresist pattern of the pattern shown in Fig. 2 on the surface of the tunnel dielectric layer in the unit area, thereby form little hole with the spacing of unanimity.Then, make the etch processes of pattern execution with photoresist so that form a plurality of little holes, this spacing (spacing as shown in Figure 3) of cheating slightly with unanimity is distributed on the surface of tunnel dielectric layer.Then, with amorphous seed crystal silicon layer (amorphous seed Si layer) vapour deposition on tunnel dielectric layer with little hole formed thereon.In this article, under the treatment temperature between 530 degrees Fahrenheits, form the seed crystal silicon layer, make it have the thickness of maximum 20nm in about 470 degrees Fahrenheits.
Alternatively, can before the conductive metal deposition layer with the oxide skin(coating) vapour deposition to the seed crystal silicon layer.
Simultaneously, will be deposited on the seed crystal silicon layer, under the N2 environment, carry out heat treatment such as the conducting metal of phosphorus (P).Especially, carry out heat treatment so that with the preset time cycle phosphorus atoms is injected in the seed crystal silicon layer according to input pulse.According to this method, can realize more effective charge trap (charge trap).
During heating treatment, the phosphorus atoms of the silicon atom of seed crystal silicon layer and conductive metal layer moves relative to each other.More specifically, the conducting metal that can comprise a plurality of phosphorus atoms be injected in the seed crystal silicon layer and be arranged on the seed crystal silicon layer with tunnel oxide in corresponding position, little hole.Therefore, on position, form quantum dot corresponding to the seed crystal silicon layer in little hole.
As shown in Figure 4, all quantum dots are arranged in the zone in little hole, and this is maximum because of stress in little hole, therefore in the cohesion that electric conducting material takes place corresponding to the position in little hole.Fig. 4 shows quantum dot and is formed at the interior state in zone, little hole.
Next, from the seed crystal silicon layer, remove conductive metal layer, and by oxide or nitride vapour deposition are made the seed crystal silicon layer insulation with quantum dot to the seed crystal silicon layer, so that form other grid structure.After this, the vapour deposition grid polycrystalline silicon, thus finish the grid structure of having used quantum dot.
As above above-mentioned apparent, and according to embodiments of the invention, because form silicon quantum dot with consistent size with the spacing of unanimity, thus can realize the device that electricity is stable, thus guaranteed the reliability of device.
Although illustrated and described embodiments of the invention, but it will be appreciated by those skilled in the art that, can change embodiments of the invention under the situation that does not deviate from principle of the present invention and spirit, scope of the present invention is limited in claims and the equivalent thereof.
Claims (20)
1. method that is used to form the grid with quantum dot comprises:
On wafer surface, form the photoresist pattern, so that form a plurality of little holes with the spacing of unanimity;
The described photoresist pattern of etching is so that form a plurality of little holes with the spacing of unanimity;
Has formation silicon dielectric layer on the described wafer surface in described little hole;
Conductive metal deposition layer and described conductive metal layer and described silicon dielectric layer carried out heat treatment on described silicon dielectric layer;
Be arranged on the described silicon dielectric layer and corresponding position, described little hole by metallic atom, in described silicon dielectric layer, form quantum dot described conductive metal layer;
Remove described conductive metal layer from described silicon dielectric layer with described quantum dot;
Form dielectric layer being formed with on the described silicon dielectric layer of described quantum dot; And
On described dielectric layer, form grid polycrystalline silicon.
2. the method that is used to form the grid with quantum dot according to claim 1 wherein, forms described little hole and makes the width in described little hole and the degree of depth all be less than or equal to 10nm.
3. the method that is used to form the grid with quantum dot according to claim 1 wherein, deposits tunnel oxide on described wafer surface, and forms described photoresist pattern on described tunnel oxide.
4. the method that is used to form grid according to claim 1 with quantum dot, wherein, described photoresist pattern comprises a plurality of open regions with diamond shape, described a plurality of open region spreads all over the entire wafer surface with the spacing of unanimity to be arranged, and makes it possible to spacing with the unanimity described little hole that distributes.
5. the method that is used to form the grid with quantum dot according to claim 1, wherein, described etch processes is included in and uses KOH or NaOH etchant on the described photoresist pattern.
6. the method that is used to form the grid with quantum dot according to claim 1, wherein, the described dielectric layer that is formed on the described silicon dielectric layer comprises oxide layer or nitration case.
7. the method that is used to form the grid with quantum dot according to claim 1 wherein, forms silica-based second dielectric layer by forming the amorphous seed crystal silicon layer with about 20nm thickness under the temperature between 530 degrees Fahrenheits in 470 degrees Fahrenheits.
8. method that is used to form the grid with quantum dot comprises:
On wafer surface, form the photoresist pattern in the unit area, so that form little hole with the spacing of unanimity;
Use described photoresist pattern to carry out etching, so that the spacing with unanimity forms a plurality of little holes on described wafer surface;
Be formed with formation first dielectric layer on the described wafer surface in described little hole;
Silica-based second dielectric layer of deposition on described first dielectric layer;
Conductive metal deposition layer and described conductive metal layer carried out heat treatment on described second dielectric layer;
The described metallic atom of described conductive metal layer is arranged on described second dielectric layer and corresponding position, described little hole, so that form quantum dot;
Remove described conductive metal layer from described second dielectric layer that is formed with described quantum dot;
Form dielectric layer being formed with on described second dielectric layer of described quantum dot; And
On described dielectric layer, form grid polycrystalline silicon.
9. the method that is used to form the grid with quantum dot according to claim 8 wherein, forms described first dielectric layer and comprises the oxide vapour deposition on described wafer surface being formed with on the described wafer surface in described little hole.
10. the method that is used to form the grid with quantum dot according to claim 8, wherein, described etch processes is included in and uses KOH or NaOH etchant on the described photoresist pattern.
11. the method that is used to form the grid with quantum dot according to claim 8, wherein, the described dielectric layer that is formed on described second dielectric layer comprises oxide layer or nitration case.
12. the method that is used to form the grid with quantum dot according to claim 8 wherein, by forming the amorphous seed crystal silicon layer with about 20nm thickness in 470 degrees Fahrenheits under the temperature between 530 degrees Fahrenheits, forms described silica-based second dielectric layer.
13. the method that is used to form the grid with quantum dot according to claim 8 wherein, forms described little hole, makes the width in described little hole and the degree of depth all be less than or equal to 10nm.
14. the method that is used to form grid according to claim 8 with quantum dot, wherein, described photoresist pattern comprises a plurality of open regions with diamond shape, described a plurality of open region with the spacing arrangement of unanimity, makes it possible to form described little hole with the spacing of unanimity on described wafer surface.
15. a method that is used to form the grid with quantum dot comprises:
On wafer surface, form first dielectric layer in the unit area;
On described first dielectric layer, form the photoresist pattern, so that form a plurality of little holes with the spacing of unanimity;
Use described photoresist pattern that described first dielectric layer is carried out etch processes, so that on described first dielectric layer, form a plurality of little holes with the spacing of unanimity;
On the surface of described first dielectric layer, form the seed crystal silicon layer with described little hole;
Conductive metal deposition layer on described seed crystal silicon layer, and to described conductive metal layer execution heat treatment;
Be arranged on the described seed crystal silicon layer by metallic atom and form quantum dot with corresponding position, described little hole with described conductive metal layer;
Remove described conductive metal layer from the described seed crystal silicon layer that is formed with described quantum dot;
Form dielectric layer being formed with on the described seed crystal silicon layer of described quantum dot; And
On described dielectric layer, form grid polycrystalline silicon.
16. the method that is used to form the grid with quantum dot according to claim 15, wherein, described photoresist pattern comprises a plurality of open regions with diamond shape, described a plurality of open regions with the spacing arrangement of unanimity on described wafer surface.
17. the method that is used to form the grid with quantum dot according to claim 15 wherein, forms described little hole, makes the width and the degree of depth all be less than or equal to 10nm.
18. the method that is used to form the grid with quantum dot according to claim 15, wherein, described etch processes is included in and uses KOH or NaOH etchant on the described photoresist pattern.
19. the method that is used to form the grid with quantum dot according to claim 15 wherein, comprises the oxide vapour deposition on described wafer surface at described first dielectric layer of formation on the described wafer surface.
20. the method that is used to form the grid with quantum dot according to claim 15 wherein, by forming the amorphous seed crystal silicon layer with about 20nm thickness in 470 degrees Fahrenheits under the temperature between 530 degrees Fahrenheits, forms silica-based second dielectric layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2007-0137081 | 2007-12-26 | ||
| KR1020070137081 | 2007-12-26 | ||
| KR1020070137081A KR100971210B1 (en) | 2007-12-26 | 2007-12-26 | Method of forming quantum dot, and forming gate using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101471251A true CN101471251A (en) | 2009-07-01 |
| CN101471251B CN101471251B (en) | 2011-02-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101312043A Expired - Fee Related CN101471251B (en) | 2007-12-26 | 2008-07-30 | Methods for forming quantum dots and forming gate using the quantum dots |
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| Country | Link |
|---|---|
| US (1) | US7829413B2 (en) |
| KR (1) | KR100971210B1 (en) |
| CN (1) | CN101471251B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114435755A (en) * | 2020-11-02 | 2022-05-06 | 株式会社村田制作所 | Multilayer ceramic capacitor package |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8470693B2 (en) * | 2008-03-31 | 2013-06-25 | Hiroshima University | Method for manufacturing quantum dot |
| KR20140015763A (en) | 2012-07-24 | 2014-02-07 | 삼성디스플레이 주식회사 | Light-emitting diode package and display apparatus having the same |
| CN105098002B (en) * | 2015-06-16 | 2018-04-03 | 京东方科技集团股份有限公司 | A kind of photoresist, the method and QLED of quantum dot layer patterning, quantum stippling film and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2002360361A1 (en) * | 2001-11-09 | 2003-06-10 | Biomicroarrays, Inc. | High surface area substrates for microarrays and methods to make same |
| KR100866948B1 (en) * | 2003-02-07 | 2008-11-05 | 삼성전자주식회사 | Single electron transistor having memory function and method for manufacturing the same |
| KR100521433B1 (en) | 2003-08-12 | 2005-10-13 | 동부아남반도체 주식회사 | Method for forming Silicon quantum dot and the method for fabricating semiconductor memory device using the same |
| KR100602084B1 (en) | 2003-12-31 | 2006-07-19 | 동부일렉트로닉스 주식회사 | Method for forming Silicon quantum dot and the method for fabricating semiconductor memory device using the same |
| KR100789988B1 (en) * | 2006-06-01 | 2008-01-02 | 성균관대학교산학협력단 | Method for fabricating Nano structures on silicon wafer using silicon dry etching and method for manufacturing Non- volatile memory using the structure |
-
2007
- 2007-12-26 KR KR1020070137081A patent/KR100971210B1/en not_active IP Right Cessation
-
2008
- 2008-06-27 US US12/163,859 patent/US7829413B2/en not_active Expired - Fee Related
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114435755A (en) * | 2020-11-02 | 2022-05-06 | 株式会社村田制作所 | Multilayer ceramic capacitor package |
| CN114435755B (en) * | 2020-11-02 | 2024-01-02 | 株式会社村田制作所 | Laminated ceramic capacitor package |
Also Published As
| Publication number | Publication date |
|---|---|
| US7829413B2 (en) | 2010-11-09 |
| CN101471251B (en) | 2011-02-16 |
| KR100971210B1 (en) | 2010-07-20 |
| US20090170303A1 (en) | 2009-07-02 |
| KR20090069427A (en) | 2009-07-01 |
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