CN101470663B - Method for processing address discontinuity in MTD design of NAND flash memory - Google Patents
Method for processing address discontinuity in MTD design of NAND flash memory Download PDFInfo
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- CN101470663B CN101470663B CN2007100330158A CN200710033015A CN101470663B CN 101470663 B CN101470663 B CN 101470663B CN 2007100330158 A CN2007100330158 A CN 2007100330158A CN 200710033015 A CN200710033015 A CN 200710033015A CN 101470663 B CN101470663 B CN 101470663B
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Abstract
The invention discloses a method of unconsciously processing addresses in an MTD design which supports a multi-plane type NAND flash memory, which comprises dividing the whole NAND flash memory space into a plurality of regions, managing each region according to an MTD, abstracting each physical plane in each region into a logical plane, calculating the related logical block numbers by the MTD according to logical sector numbers transmitted from the upper application, then addressing according to the logical block numbers, corresponding the logical block numbers to false physical block number one by one through a mapping table, and finally realizing the access of MTD to a physical block number through related algorithm according to the false physical block numbers. The method facilitates the MTD to support an NAND flash memory comprising a plurality of physical planes, and to be independent from a changing MLC.
Description
Technical field
The present invention relates to handle the discontinuous method in address in a kind of MTD design of the nand flash memory of supporting many plane types.
Background technology
Various nand flash memories have been widely used in terminal consumption products such as mobile phone, number, its capacity is increasing, multilevel MLC (Multi-Level Cell, multi-layered unit flash memory) just progressively replaces SLC (Single-Level Cell, single layer cell flash memory) becomes the market mainstream.Multilevel MLC has a lot of new characteristics, the block address on each plane no longer be continuous be one of maximum variation that influence MTD (Memory Technology Device, memory techniques equipment) design.
Because most of SLC are the designs of monoplane, a lot of original MTD designs all are not support multilevel nand flash memory.Simultaneously, because the renewal of the manufacturing process of MLC is very fast, the method on various divisions plane is also being brought in constant renewal in, and original MTD design is can't adapt to these new variations.
Summary of the invention
For overcoming above-mentioned deficiency, the object of the present invention is to provide in a kind of MTD design of the nand flash memory of supporting many plane types and handle the discontinuous method in address, make its nand flash memory that can support to comprise a plurality of physical planes, adapt to the continuous variation of MLC.
For finishing the foregoing invention purpose, the technical scheme that the present invention takes comprises following steps:
A. be whole nand flash memory spatial division a plurality of zones, each zone manages by a MTD, and MTD writes down the physical plane that first piece was positioned at number of its management area and this piece side-play amount with respect to this physical plane;
B. each physical plane in each zone is all abstract is a logic plane, and each logic plane all has independently to distribute to be distinguished;
The logic sector number that c.MTD transmits according to upper layer application calculates corresponding logical block number (LBN), carries out addressing according to logical block number (LBN) then;
D. the described logical block number (LBN) of above-mentioned steps c is by the corresponding one by one pseudo-physical block number of mapping table;
E.MTD realizes visit to physical block number according to pseudo-physical block number by corresponding mapping algorithm.
Wherein, the described mapping table of steps d is target array under being with logical block number (LBN), and the content of array is the pseudo-physical block number of logical block number (LBN) correspondence.
The present invention supports the MTD of the nand flash memory of many plane types to handle the discontinuous method in address in designing, and makes its nand flash memory that can support to comprise a plurality of physical planes, can not be subjected to the influence of the continuous variation of MLC.
Description of drawings
Fig. 1 divides the situation of physical plane for the address, front and back;
Fig. 2 wherein, distributes the district that 4 pieces are arranged corresponding to the two-layer address translation process synoptic diagram of Fig. 1;
The Nand flash memory of Fig. 3 list physical plane (two chips) area dividing and address mapping relation synoptic diagram;
The area dividing and the address mapping relation synoptic diagram of the twin-core sheet nand flash memory of two physical planes divided in Fig. 4 odd even address;
The area dividing and the address mapping relation synoptic diagram of the single-chip nand flash memory of four physical planes that the address was divided before and after the existing odd even of Fig. 5 had again.
Dash area is a zoning among above-mentioned Fig. 1, Fig. 3, Fig. 4 and Fig. 5.
Embodiment
1, according to the real needs of upper layer application such as the requirement of memory contents security, be whole nand flash memory spatial division several different zones, a plurality of physical planes may be crossed in a zone, even a plurality of nand flash memory chip.Each zone of dividing like this all manages by a MTD.MTD need write down the physical plane that first physical block was positioned at number of its management area and this physical block side-play amount with respect to this physical plane.Fig. 1 is the dividing condition of two nand flash memory chips, and two physical planes are divided in the address, front and back, and three logic plane Plane0, Plane1 and the common part that constitutes of Plane2 are exactly a zone that MTD will administer.Three column of figures on this left side, zone from left to right as shown in the figure, represent physical block number, pseudo-physical block number and logical block number (LBN) respectively, each column of figure all is to be each defined among three logic plane Plane0, Plane1 and the Plane2, for example, the logical block number (LBN) 0 of logic plane Plane0 is different from the logical block number (LBN) 0 among the logic plane Plane1.There is not this piece number in "--" presentation logic piece number.The beginning in whole nand flash memory space partly can be used as specific use, and such as the bad block message of depositing nand flash memory, it can not return any MTD management.If be divided into last physical plane, the also not enough piece number that distributes the district of its remaining number, then these pieces are discarded can not use.2 nand flash memory chip CHIP0 and CHIP1 have been crossed in this zone, totally 3 physical plane CHIP0_LANE0, CHIP0_PLANE1 and CHIP1_PLANE0, as seen from Figure 1, first physical plane of MTD management is CHIP0_PLANE0, and first physical block is 4 with respect to the side-play amount of this physical plane.
2, the physical plane number of crossing over according to the zone, the part that each physical plane is positioned at this zone all is abstracted into a logic plane, as 3 logic plane: Plane0 among Fig. 1, Plane1, Plane2.Each logic plane writes down each self-contained number, and keeps the invalid block of some, and invalid block is not deposit the piece of valid data, their not corresponding any logical block number (LBN)s, and the set of these pieces is called and distributes the district.For each physical block, select the additional zone of its some page or leaf to write down its logical block number (LBN) with respect to this logic plane, for the piece that distributes in the district, the logical block number (LBN) of its record is invalid.
3, the set meeting of the logical block number (LBN) of MTD upper strata use is less than the set of pseudo-physical block number composition, because distribute the piece in the district and do not correspond to any logical block number (LBN).Scanning whole zone just can set up logical block number (LBN) to the mapping relations of pseudo-physical block number.Each logic plane records this mapping relations among its mapping table Log2Fake that has separately, as shown in Figure 2.Mapping table Log2Fake can be an array, the subscript presentation logic piece of array number, and the corresponding pseudo-physical block number of its content representation so just can promptly be found out the pseudo-physical block number of its correspondence by logical block number (LBN).
4, in fact, reading and writing data is substantially all carried out by logic sector number SectorNum in the MTD upper strata.According to the size of the physical plane of regional starting position, area size and the nand flash memory of MTD record, can calculate and the corresponding logical block number (LBN) of logic sector number SectorNum and logic plane number.Computing method are as follows:
At first be offset 1 LogOffset1 with regard to representing this piece with respect to the logic of whole nand flash memory address space divided by the merchant of sector that piece comprised sum gained by logic sector number SectorNum; And then be offset 1 LogOffset1 according to logic, be offset 2 LogOffset2 by each regional reference position and size just can calculate that this sector is positioned at regional and with respect to this regional logic; Be offset 2 LogOffset2 by logic then, the number of the logical block number (LBN) that comprises according to the size of distributing the district and each logic plane is again tried to achieve logic plane that this piece is positioned at number and corresponding logical block number (LBN); At last,, just can directly obtain out pseudo-physical block number, change by mapping table Log2Fake to the conversion in middle layer as the superiors among Fig. 2 according to this logic plane corresponding mapping table Log2Fake.
5, the needed address of visit nand flash memory is the skew page number Page in phy chip Chip, physical block number and the piece, and they can obtain by corresponding mapping algorithm Fake2Rea1.Pseudo-code with the C language provides 4 kinds of mapping algorithm Fake2Rea1 that divide the physical plane method corresponding to difference respectively below, this algorithm is the universal law that obtains by each piece corresponding relation among summary Fig. 1, Fig. 3, Fig. 4 and Fig. 5 respectively, and the mode of being divided physical plane by area dividing and nand flash memory determines.
The implication that the variable that pseudo-code is used is represented is as follows:
Chip is a phy chip number;
FstPlane represents the physical plane that first physical block was positioned at number of MTD management;
StartBlkOfFstPlane represents the side-play amount of first physical block of MTD management with respect to this physical block of FstPlane;
PlaneNum presentation logic plane number;
Fake represents pseudo-physical block number;
Phy represents physical block number;
PlanePerChip represents the physical plane number that each phy chip is divided;
BlockPerPlane represents the total block data that a physical plane comprises;
Page is the skew page number in the piece;
SecPerBlk represents the sector sum in the physical block.
Wherein, the logic plane PlaneNum of logic sector number SectorNum correspondence and pseudo-physical block number Fake are calculated by the method in above-mentioned the 4th step.
No matter the method for the skew page number Page in the division methods of any physical plane, computational physics chip Chip and piece is:
Chip＝(PlaneNum+FstPlane)/PlanePerChip；
Page＝SectorNum％SecPerBlk；
In addition, computational physics piece Phy need be different and different at the mode of concrete division physical plane: the 1) situation of single physical plane, as shown in Figure 3:
If (PlaneNum equals 0) // whether be positioned at first logic plane in this zone
{
Fake＝Fake+StartBlkOfFstPlane；
}
Phy＝Fake；
2) situation of physical plane is divided in the address before and after, as shown in Figure 1:
If (PlaneNum equals 0) // whether be positioned at first logic plane in this zone
{
Fake=Fake+StartBlkOfFstPlane; // need increase this regional side-play amount
}
PlaneNum＝(PlaneNum+FstPlane)％PlanePerChip；
Phy＝Fake+PlaneNum*BlockPerPlane；
3) situation of physical plane is divided in the odd even address, as shown in Figure 4:
If (PlaneNum equals 0) // whether be positioned at first logic plane in this zone
{
Fake=Fake+StartBlkOfFstPlane; // need increase this regional side-play amount
}
PlaneNum＝(PlaneNum+FstPlane)％PlanePerChip；
Phy＝Fake*PlanePerChip+PlaneNum；
4) situation that physical plane was divided in the address before and after existing odd even had again, as shown in Figure 5:
If (PlaneNum equals 0) // whether be positioned at first logic plane in this zone
{
Fake=Fake+StartBlkOfFstPlane; // need increase this regional side-play amount
}
PlaneNum＝(PlaneNum+FstPlane)％PlanePerChip；
Phy＝Fake*2+(PlaneNum/2)*BlockPerPlane*2+(PlaneNum％2)；
According to the area dividing of Fig. 1, illustrate the process of two-layer map addresses below.
Among Fig. 1, the total block data that the zone is comprised is: 37, and wherein logic plane Plane0 comprises 12, and logic plane Plane1 comprises 16, and logic plane Plane2 comprises 9.The logical block number of depositing valid data is total up to: 25, because three logic planes all contain the distribution district of 4 pieces.The piece of supposing this nand flash memory comprises 128 pages or leaves, and each page or leaf has only a sector, and promptly the block size of nand flash memory is 128 sectors, and PlanePerChip equals 2.Wherein FstPlane equals 0, and StartBlkOfFstPlane equals 4.The logic sector SectorNum that present upper strata need be visited is 3002, at this moment Plane1_Log2Fake[10]=5, Plane1_Log2Fake[11]=13, Plane1_Log2Fake[12]=15.
At first according to the 4th computing method that provide of step, be not difficult to obtain this logic sector SectorNum and be positioned at the zone, and try to achieve logic skew 1LogOffsetl and equal 23, promptly 3002 divided by 128 merchants that obtain, and logic skew 2LogOffset2 equals 19.Because the distribution district of each logic plane is 4, promptly the logical block number of the valid data deposited that comprise of Plane0, Plane1 and Plane2 is respectively 8,12 and 5, so the position of LogOffset2 is arranged in logic plane Plane1, and LogAddr equals 11.
Can directly obtain pseudo-physical block number by the mapping table of this logic plane Plane1 and just equal 13 (Plane1_Log2Fake[11]), as one of the input in the 5th step.Divide physical plane because this nand flash memory is the address, front and back, second layer mapping relations are by the 2nd in the 5th step) decision of kind situation.All of mapping relations are input as: PlanePerChip=2, SecPerBlk=128, plane=1, Fake=13, StartBlkOfFstPlane=4, FstPlane=0, so SectorNum=3002., bring for the 2nd in top the 5th step into) plant the computing method of situation, can obtain: Chip=0, Page=58, Phy=29.The result who calculates is consistent with the corresponding relation of Fig. 1 synoptic diagram.
Fig. 3, Fig. 4, Fig. 5 corresponding respectively single physical plane, odd even address divide physical plane and existing odd even have again before and after the address area dividing and the address mapping relation example of dividing the nand flash memory of physical plane.Can be for these three kinds of its account forms of situation with reference to above-mentioned illustrating about Fig. 1.When actual Project Realization, in fact the piece number in the distribution district is far smaller than the total block data of each physical plane, this information is not depicted for convenience of description in the diagram.
Claims (2)
1. handle the discontinuous method in address in the MTD of the nand flash memory design, it is characterized in that it comprises following steps:
A. be whole nand flash memory spatial division a plurality of zones, each zone manages by a MTD, and MTD writes down the physical plane that first piece was positioned at number of its management area and this piece side-play amount with respect to this physical plane;
B. each physical plane in each zone is all abstract is a logic plane, and each logic plane all has independently to distribute to be distinguished;
The logic sector number SectorNum that c.MTD transmits according to upper layer application calculates corresponding logical block number (LBN) and logic plane PlaneNum, and concrete steps are as follows: at first just represent the logic skew 1LogOffsetl of this piece with respect to whole nand flash memory address space by logic sector number SectorNum divided by the merchant of sector that piece comprised sum gained; And then, just can calculate zone that this sector is positioned at and be offset 2LogOffset2 with respect to this regional logic by each regional reference position and size according to logic skew 1LogOffsetl; Then by logic skew 2LogOffset2, the number of the logical block number (LBN) that comprises according to the size of distributing the district and each logic plane is tried to achieve logic plane PlaneNum and corresponding logical block number (LBN) that this piece is positioned at again, carries out addressing according to logical block number (LBN) then;
D. the described logical block number (LBN) of above-mentioned steps c is by the corresponding one by one pseudo-physical block number of mapping table;
It is skew page number Page in phy chip Chip, physical block number Phy and the piece that e.MTD obtains the needed address of visit NAND internal memory according to pseudo-physical block number Fake, and it may further comprise the steps:
(1) the skew page number Page in computational physics chip Chip and the piece: Chip=(PlaneNum+FstPlane)/PlanePerChip; Page=SectorNum%SecPerBlk; Wherein, PlanePerChip represents the physical plane number that each phy chip is divided; SecPerBlk represents the sector sum in the physical block;
(2) if logic plane PlaneNum is 0, then pseudo-physical block number Fake is updated to: Fake=Fake+StartBlkOfFstPlane enters next step again; Otherwise, directly enter next step;
(3) under following situation, obtain physical block number Phy respectively:
Under the situation of single physical plane: Phy=Fake;
Divide in the address, front and back under the situation of physical plane:
PlaneNum＝(PlaneNum+FstPlane)％PlanePerChip；
Phy＝Fake+PlaneNum*BlockPerPlane；
Divide in the odd even address under the situation of physical plane:
PlaneNum＝(PlaneNum+FstPlane)％PlanePerChip；
Phy＝Fake*PlanePerChip+PlaneNum；
The address is divided under the situation of physical plane before and after existing odd even has again:
PlaneNum＝(PlaneNum+FstPlane)％PlanePerChip；
Phy＝Fake*2+(PlaneNum/2)*BlockPerPlane*2+(PlaneNum％2)；
Wherein, FstPlane represents the physical plane that first physical block was positioned at number of MTD management;
BlockPerPlane represents the total block data that a physical plane comprises.
2. handle the discontinuous a kind of method in address in the MTD of the nand flash memory according to claim 1 design, it is characterized in that, the described mapping table of steps d is target array under being with logical block number (LBN), and the content of array is the pseudo-physical block number of logical block number (LBN) correspondence.
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| US20110161553A1 (en) * | 2009-12-30 | 2011-06-30 | Nvidia Corporation | Memory device wear-leveling techniques |
| US9594675B2 (en) | 2009-12-31 | 2017-03-14 | Nvidia Corporation | Virtualization of chip enables |
| CN103377135B (en) * | 2012-04-25 | 2016-04-13 | 上海东软载波微电子有限公司 | Addressing method, Apparatus and system |
| CN103853496B (en) * | 2012-11-28 | 2017-02-22 | 华为技术有限公司 | Method and device for hooking various devices in same memory technology device partition |
| CN109343887A (en) * | 2018-09-20 | 2019-02-15 | 深圳市零点智联科技有限公司 | A method of optimization STM32 chip DFU upgrading |
| CN113409846A (en) * | 2021-06-30 | 2021-09-17 | 芯天下技术股份有限公司 | Discontinuous address processing method and device, electronic equipment and storage medium |
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