CN103853496B - Method and device for hooking various devices in same memory technology device partition - Google Patents
Method and device for hooking various devices in same memory technology device partition Download PDFInfo
- Publication number
- CN103853496B CN103853496B CN201210495019.9A CN201210495019A CN103853496B CN 103853496 B CN103853496 B CN 103853496B CN 201210495019 A CN201210495019 A CN 201210495019A CN 103853496 B CN103853496 B CN 103853496B
- Authority
- CN
- China
- Prior art keywords
- mtd
- subregion
- chip
- sub
- description information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 83
- 238000005192 partition Methods 0.000 title abstract description 11
- 238000005516 engineering process Methods 0.000 title abstract description 6
- 238000010276 construction Methods 0.000 claims description 30
- 230000006978 adaptation Effects 0.000 claims description 10
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 7
- 108010024160 informosome Proteins 0.000 description 5
- 101150076088 MTD1 gene Proteins 0.000 description 4
- 239000002245 particle Substances 0.000 description 3
- 230000004899 motility Effects 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 238000004590 computer program Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Abstract
The embodiment of the invention provides a method and a device for hooking various devices in a same memory technology device partition. The method and device for hooking various devices in the same memory technology device partition are used for reducing the complexity of upper software processing. The method comprises expanding the same MTD (memory technology device) partition into a plurality of sub MTD partitions; adapting a corresponding chip description information body to every sub MTD partition; associating every chip description information body to a private information body provided by a manufacture of an MTD memory device to be hooked. The method can hook various types of chips in different sub MTD partitions of the same parent MTD partition and only embody a single parent MTD partition for upper software, thereby meeting the requirement of the application scenario in which complexity of the upper software is reduced and MTD original memory devices with the various types of chips are hooked in the same MTD partition, and meanwhile, enhancing the flexibility of chip type selection of products and reducing the cost in the chip type selection.
Description
Technical field
The present invention relates to field of data storage, more particularly, to realize same memory techniques equipment subregion and mount plurality of devices
Method and apparatus.
Background technology
Memory techniques equipment（Memow Technology Device, MTD）It is the Linux for accessing memory device
Subsystem.The main purpose of MTD is in order that the driving of new memory device is simpler, for this it between hardware and upper strata
Provide an abstract interface.It is struct mtd_info that each MTD original storage device has a mtd_info structure
Mtd, every kind of chip also has the structure for describing each Flash chip Proprietary Information, for example, the structure of description NAND chip
Body is struct nand_chipchip, and describes the structure of MTD original storage device and the knot of description chip Proprietary Information
Structure body corresponds, and for example, struct mtd_info mtd and struct nand_chip chip corresponds.
Structure due to there is above-mentioned MTD original storage device is corresponded with the structure of description chip Proprietary Information
Relation, i.e. the original storage device of a MTD subregion must be same attribute, therefore, under same MTD subregion all
Mounting same kind chip, the original storage device of different attribute（Corresponding to dissimilar chip）Same MTD can not be articulated in
Under subregion.For example, it is assumed that MTD1 subregion has mounted NAND Flash, then can only mount NAND Flash under MTD1 subregion,
Other kinds of chip, such as NOR Flash or NVRAM Flash can not be mounted, mount NOR Flash or
NVRAMFlash, can only mount under another MTD subregion.
MTD original storage device according to existing above-mentioned same kind chip can only be articulated under same MTD subregion or
Person can only be articulated to this framework under different MTD subregions respectively due to the MTD original storage device of dissimilar chip, when for
Reduce the complexity of upper layer software (applications)（For example, reduce the management to MTD subregion）, need to mount difference under same MTD subregion
During the MTD original storage device of type chip, the framework of prior art just cannot realize this demand.
Content of the invention
The embodiment of the present invention provides the method and apparatus realizing that same memory techniques equipment subregion mounts plurality of devices, to increase
Plus the application scenarios of same MTD subregion.
The embodiment of the present invention provides a kind of method realizing same memory techniques equipment subregion mounting many attributes equipment, described
Method includes：Same memory techniques equipment MTD subregion is expanded to many sub- MTD subregions；For every in the plurality of sub- MTD subregion
One sub- MTD subregion is adapted to a corresponding chip description information body；By each chip description information body described respectively with needs
The privately owned description information body association that the MTD memory device manufacturer of mounting is provided.
Alternatively, described chip description information body is the structure of description chip attribute, institute of described MTD memory device manufacturer
The code private data structure that the privately owned description information body providing is provided by MTD memory device manufacturer.
Alternatively, described it is adapted to a corresponding chip for the sub- MTD subregion of each of the plurality of sub- MTD subregion and describes
Informosome includes：The construction structure with each of the plurality of sub- MTD subregion corresponding chip attribute of sub- MTD subregion respectively
Body；Corresponding for same memory techniques equipment MTD subregion structure is pointed to the structure of multiple chip attributes of described construction.
Alternatively, described it is adapted to a corresponding chip for the sub- MTD subregion of each of the plurality of sub- MTD subregion and describes
Informosome includes：The construction structure with each of the plurality of sub- MTD subregion corresponding chip attribute of sub- MTD subregion respectively
Body；Corresponding for same memory techniques equipment MTD subregion structure is pointed to the structure of multiple chip attributes of described construction；Institute
State each chip description information body described vendor code privately owned description information body with the MTD original device needing mounting respectively
Association includes：Each of the structure of multiple chip attributes by described construction structure be respectively directed to described need mount
The code private data structure that provided of MTD memory device manufacturer.
The embodiment of the present invention provides a kind of device realizing same memory techniques equipment subregion mounting many attributes equipment, described
Device includes：Subregion expansion module, for expanding to many sub- MTD subregions by same memory techniques equipment MTD subregion；Adaptation mould
Block, for being adapted to a corresponding chip description information body for the sub- MTD subregion of each of the plurality of sub- MTD subregion；Association
Module, for privately owned with what the MTD memory device manufacturer needing mounting was provided respectively by each chip description information body described
Description information body associates.
Alternatively, described chip description information body is the structure of description chip attribute, institute of described MTD memory device manufacturer
The code private data structure that the privately owned description information body providing is provided by MTD memory device manufacturer.
Alternatively, described adaptation module includes：Structure structural unit, is divided with the plurality of sub- MTD respectively for construction
The structure of the corresponding chip attribute of each of area sub- MTD subregion；First link setup unit, for by same memory techniques equipment
The corresponding structure of MTD subregion points to the structure of multiple chip attributes of described construction.
Alternatively, described relating module includes：Second link setup unit, for by the knot of multiple chip attributes of described construction
Each of structure body structure is respectively directed to the code private data that the described MTD memory device manufacturer needing mounting is provided
Structure.
Knowable to the embodiments of the present invention, because same MTD subregion is expanded into many sub- MTD subregions, so, same
One MTD subregion can accommodate the MTD memory device of different attribute, and each sub- MTD subregion is adapted to a corresponding chip and retouches
State informosome, and the privately owned description information body being provided with the MTD memory device manufacturer needing mounting respectively is associated.Therefore, originally
The method that inventive embodiments provide can make different types of chip be articulated in the difference sub- MTD subregion of same father's MTD subregion
Under, but upper layer software (applications) is still only presented as with father's MTD subregion, disclosure satisfy that in order to reduce the complexity of upper layer software (applications) and
Mount the demand of MTD original storage this application scenarios of device of dissimilar chip under same MTD subregion, be also product simultaneously
Carry out chip type selecting and increased motility, the cost of chip type selecting can be reduced.
Brief description
In order to be illustrated more clearly that the technical scheme of the embodiment of the present invention, in prior art or embodiment being described below
The accompanying drawing of required use be briefly described it should be apparent that, drawings in the following description be only the present invention some are real
Apply example, for those skilled in the art, other accompanying drawings can also be obtained as these accompanying drawings.
Fig. 1 is the method stream realizing same memory techniques equipment subregion mounting many attributes equipment provided in an embodiment of the present invention
Journey schematic diagram；
Fig. 2 is provided in an embodiment of the present invention same memory techniques equipment MTD subregion is expanded to many sub- MTD to divide
Area's schematic diagram；
Fig. 3 is the points relationship schematic diagram of each structure provided in an embodiment of the present invention；
Fig. 4 is the device knot realizing same memory techniques equipment subregion mounting many attributes equipment provided in an embodiment of the present invention
Structure schematic diagram；
Fig. 5 is the dress realizing same memory techniques equipment subregion mounting many attributes equipment that another embodiment of the present invention provides
Put structural representation；
Fig. 6（a）It is that the same memory techniques equipment subregion of realizing that another embodiment of the present invention provides mounts many attributes equipment
Apparatus structure schematic diagram；
Fig. 6（b）It is that the same memory techniques equipment subregion of realizing that another embodiment of the present invention provides mounts many attributes equipment
Apparatus structure schematic diagram.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, the every other embodiment that those skilled in the art are obtained, broadly fall into the scope of protection of the invention.
Refer to accompanying drawing 1, be provided in an embodiment of the present invention to realize same memory techniques equipment subregion and mount many attributes setting
Standby method flow schematic diagram, main inclusion step S101, step S102 and step S103：
S101, same memory techniques equipment MTD subregion is expanded to many sub- MTD subregions.
In embodiments of the present invention, it is no longer with a MTD subregion for minimum operation unit, but by a MTD subregion
It is split as some sub- MTD subregions, so, for smallest particles, many sub- MTD subregions can be operated with sub- MTD subregion.
Same memory techniques equipment MTD subregion is expanded to after many sub- MTD subregions, extends many sub- MTD subregions of gained and expanded
The MTD subregion of exhibition is membership.As shown in Fig. 2 it is father that n sub- MTD subregion of extension gained is under the jurisdiction of same MTD subregion
MTD subregion.
Although it should be noted that same memory techniques equipment MTD subregion expands to many sub- MTD subregions, interior verification
The interface layer on upper strata remains layer belonging to father's MTD subregion, and upper strata is presented as with a corresponding structure, for example, struct
mtd_info mtd；Upper strata remains to the operation of MTD subregion first calls the interface that this layer belonging to father's MTD subregion provides to come in fact
Existing.
S102, is that the sub- MTD subregion of each of the plurality of sub- MTD subregion is adapted to a corresponding chip description information
Body.
As it was previously stated, after same memory techniques equipment MTD subregion expands to many sub- MTD subregions, can be with sub- MTD subregion
For smallest particles, many sub- MTD subregions are operated.Because the attribute major embodiment of each MTD original device is in its chip
In the data description of attribute abstraction, and so that every sub- MTD subregion mounting is a kind of（Individual）MTD original device, thus realize
Same memory techniques equipment MTD subregion mounts the MTD original device of many attribute, by same memory techniques equipment MTD subregion
After expanding to many sub- MTD subregions, need to be adapted to one accordingly for the sub- MTD subregion of each of the plurality of sub- MTD subregion
Chip description information body.
As one embodiment of the invention, chip description information body can be the structure of description chip attribute.For example, right
In NAND Flash, chip description information body can describe its attribute with struct this structure of nand_chip chip, such as
Fruit have multiple, can with struct nand_chip chip [0], struct nand_chipchip [1] ..., struct
Nand_chip chip [n] etc. is distinguished by；The structure of description chip attribute provides one for direct read/write chip data
Interface layer, and interface layer just corresponds to an attribute.
In embodiments of the present invention, it is that each of many sub- MTD subregions MTD subregion one corresponding chip of adaptation is retouched
State informosome to include：The construction structure with each of the plurality of sub- MTD subregion corresponding chip attribute of sub- MTD subregion respectively
Body, then, corresponding for same memory techniques equipment MTD subregion structure is pointed to the structure of multiple chip attributes of described construction
Body.
In other words, same memory techniques equipment MTD subregion is extended to how many sub- MTD subregions, and just correspondingly construction is many
The structure of few chip attribute.The structure of each chip attribute at least includes one and can point at next laminar structure
Pointer to member, for example, for the structure structnand_chip chip of description NAND attribute, it should comprise member and refer to
Pin * priv；* priv is used for pointing to next laminar structure, for example, the vendor code privately owned description information body of MTD.
Due to the corresponding structure script of father's MTD subregion just have point to next laminar structure pointer to member, therefore, when point
Do not construct with after the structure of each of the plurality of sub- MTD subregion corresponding chip attribute of sub- MTD subregion, it is possible to use
The pointer to member of father's MTD subregion corresponding construction body points to the structure of multiple chip attributes of described construction；Then, father MTD divides
Area's corresponding construction body points to the structure of the corresponding chip attribute of each individual sub- MTD subregion being under the jurisdiction of it.
S103, each chip description information body described is provided with the MTD memory device manufacturer needing mounting respectively
Privately owned description information body association.
As one embodiment of the invention, the privately owned description information body that MTD memory device manufacturer is provided can be that MTD deposits
The code private data structure that memory device manufacturer is provided, it comprises the information of concrete memory device, such as size of devices,
Little read/write unit, erasure unit and read/write function etc., and two members：Mtd_info and chip, to realize and storage core
The IO associative operation of piece.For example, for the MTD memory device of NAND, the code private data structure that its manufacturer is provided can
So that its attribute is described with this structure of structfsl_elbc_mtd nandpriv；If there are multiple, can be with
structfsl_elbc_mtd nandpriv[0]、struct fsl_elbc_mtd nandpriv[1]、……、
Structfsl_elbc_mtd nandpriv [n] etc. is distinguished by.When constructing respectively each of with many sub- MTD subregions
The structure of the corresponding chip attribute of sub- MTD subregion, and corresponding for same memory techniques equipment MTD subregion structure is pointed to institute
After stating the structure of multiple chip attributes of construction, can be by each of structure of multiple chip attributes of described construction
Structure is respectively directed to the code private data structure that the described MTD memory device manufacturer needing mounting is provided.Specifically,
Can be by the pointer to member in each of the structure of multiple chip attributes of described construction structure body be respectively directed to
The described code private data structure that provided of MTD memory device manufacturer needing mounting is realizing.
When user's execution division operation, program entity is by father MTD according to " father MTD->Sub- MTD->MTD memory device "
Mode carries out extension and the structure mounting of MTD subregion, and so, father MTD can comprise the MTD memory device of many middle attributes, and
User is needed the address accessing according to each sub- MTD partition size, is scaled corresponding address in certain sub- MTD subregion corresponding, and
According to sub- MTD attribute（For example, the read/write function of concrete mounting）Conduct interviews.
Below so that same memory techniques equipment MTD subregion expands to 2 sub- MTD subregions as a example, the embodiment of the present invention is described
The above-mentioned method realizing same memory techniques equipment MTD subregion mounting many attributes equipment providing.
Assume the memory device needing under same memory techniques equipment MTD subregion to mount NAND chip and NOR chip, then press
According to said method, can be that to be under the jurisdiction of the 0th work song MTD subregion of father's MTD subregion be MTD0 and the 1st work song MTD subregion is MTD1
It is adapted to corresponding chip description information body respectively, i.e. the structure struct nand_chip of first construction description chip attribute
Chip [0] and struct nor_chip chip [1]；Structnand_chip chip [0] and struct nor_chip
Chip [1] all has the pointer to member * priv pointing to next laminar structure.Then, by corresponding for father's MTD subregion structure
The pointer to member * priv that struct mtd_info mtd is had points to struct nand_chip chip [0] and struct
nor_chip chip[1]；Described structnand_chip chip [0] and struct nor_chip chip [1] are referred to respectively
The code private data structure being provided to the described MTD memory device manufacturer needing mounting, i.e. by struct nand_
The pointer to member * priv of chip chip [0] points to the code private data needing the MTD memory device manufacturer of mounting to be provided
Structure struct fsl_elbc_mtd nandpriv [0], by the pointer to member * of struct nor_chip chip [1]
Priv points to the code private data structure struct fsl_elbc_ needing the MTD memory device manufacturer of mounting to be provided
mtdnorpriv[1].Its complete structure is as follows：
nandpriv[0]->mtd=mtd；
norpriv[1]->mtd=mtd；
nandpriv[0]->chip=chip[0]；
norpriv[1]->chip=chip[1]；
chip[0]->priv=nandpriv[0]；
chip[1]->priv=norpriv[1]；
mtd->priv=chip[0]；
Or
mtd->priv=chip[1]；
The points relationship of each structure is as shown in Figure 3.
It should be noted that the structure pointer member of group MTD0 or sub- MTD1 subregion（struct mtd_info*mtd）
When pointing to father's MTD subregion corresponding structure struct mtd_info mtd, between MTD subregion, be equivalent to one circulation of composition
Chained list, can be according to original MTD equipment corresponding structure struct fsl_elbc_mtd so that program is when processing
Nandpriv [0] or struct fsl_elbc_mtd nordpriv [1] finding the address of father MTD because wherein have having
This member of mtd_info.
When upper level applications pass through MTD interface accessing, according to actual access address, switching at runtime mounts mtd->priv
Point to chip [0] or mtd->Priv point to chip [1], thus the memory device realizing multiple different attributes be articulated in same
Under individual MTD subregion.
Realize the method that same memory techniques equipment subregion mounts many attributes equipment from what the embodiments of the present invention provided
Understand, because same MTD subregion is expanded into many sub- MTD subregions, so, same MTD subregion can accommodate different attribute
MTD equipment, and each sub- MTD subregion is adapted to a corresponding chip description information body, and respectively with need the MTD that mounts
The privately owned description information body association that memory device manufacturer is provided.Therefore, method provided in an embodiment of the present invention can make difference
The chip of type is articulated under the difference sub- MTD subregion of same father's MTD subregion, but is still only presented as one to upper layer software (applications)
Father's MTD subregion, disclosure satisfy that to reduce the complexity of upper layer software (applications) and mounts dissimilar chip under same MTD subregion
The demand of MTD original storage this application scenarios of device, carries out chip type selecting for product simultaneously and increased motility, can reduce
The cost of chip type selecting.
Refer to accompanying drawing 4, be provided in an embodiment of the present invention to realize same memory techniques equipment subregion and mount many attributes setting
Standby apparatus structure schematic diagram.For convenience of description, illustrate only the part related to the embodiment of the present invention.Accompanying drawing 4 example
The same memory techniques equipment subregion realized mount the device of many attributes equipment and include subregion expansion module 401, adaptation module 402
With relating module 403, wherein：
Subregion expansion module 401, for expanding to many sub- MTD subregions by same memory techniques equipment MTD subregion.
In the device of this accompanying drawing 4 example, it is no longer with a MTD subregion for minimum operation unit, but by a MTD
Subregion is split as some sub- MTD subregions, so, many sub- MTD subregions can be grasped with sub- MTD subregion for smallest particles
Make.Subregion expansion module 401 expands to same memory techniques equipment MTD subregion after many sub- MTD subregions, extends the many of gained
Individual sub- MTD subregion and the MTD subregion being expanded are memberships.As shown in Fig. 2 n sub- MTD subregion of extension gained is under the jurisdiction of
Same MTD subregion is father's MTD subregion.
Although it should be noted that same memory techniques equipment MTD subregion is expanded to many height by subregion expansion module 401
MTD subregion, but the interface layer on interior verification upper strata remains layer belonging to father's MTD subregion, and upper strata is presented as with a corresponding structure
Body, for example, struct mtd_info mtd；Upper strata remains to the operation of MTD subregion first calls this layer belonging to father's MTD subregion
The interface providing is realizing.
Adaptation module 402, for being adapted to a corresponding core for the sub- MTD subregion of each of the plurality of sub- MTD subregion
Piece description information body.
Relating module 403, for the MTD memory device factory mounting each chip description information body described respectively with needs
The privately owned description information body association that business is provided.
It should be noted that implementation above same memory techniques equipment subregion mounts the embodiment party of the device of many attributes equipment
In formula, the division of each functional module is merely illustrative of, can as needed in practical application, and the configuration of for example corresponding hardware will
Ask or the convenient of realization of software considers, and above-mentioned functions distribution is completed by different functional modules, will described realize
The internal structure that same memory techniques equipment subregion mounts the device of many attributes equipment is divided into different functional modules, to complete
All or part of function described above.And, in practical application, the corresponding functional module in the present embodiment can be by
Corresponding hardware is realized completing it is also possible to execute corresponding software by corresponding hardware, for example, aforesaid subregion expansion module,
Can be that there is the aforementioned hardware that same memory techniques equipment MTD subregion expands to many sub- MTD subregions of execution, such as subregion
Expander or be able to carry out corresponding computer program thus completing general processor or other hardware of aforementioned function
Equipment；For another example aforesaid adaptation module, can be to have execution aforementioned to divide for each of the plurality of sub- MTD subregion MTD
Area is adapted to the hardware of a corresponding chip description information body function, such as adapter or be able to carry out accordingly calculating
Machine program is thus complete general processor or other hardware devices of aforementioned function（Each embodiment that this specification provides is all
Foregoing description principle can be applied）.
In the device of this accompanying drawing 4 example, chip description information body can be the structure of description chip attribute.For example,
For NAND Flash, chip description information body can describe its attribute with struct this structure of nand_chip chip,
If there are multiple, can with struct nand_chip chip [0], struct nand_chipchip [1] ..., struct
Nand_chip chip [n] etc. is distinguished by；The structure of description chip attribute provides one for direct read/write chip data
Interface layer, and interface layer just corresponds to an attribute.The adaptation module 402 of accompanying drawing 4 example can include structure structural unit 501
With the first link setup unit 502, what another embodiment of the present invention provided as shown in Figure 5 realizes same memory techniques equipment subregion extension
Connect the device of many attributes equipment, wherein：
Structure structural unit 501, for construction respectively with each of the plurality of sub- MTD subregion MTD subregion phase
The structure of the chip attribute answered；
First link setup unit 502, for pointing to described construction by corresponding for same memory techniques equipment MTD subregion structure
Multiple chip attributes structure.
In the device of this accompanying drawing 4 example, chip description information body can be deposited for the structure of description chip attribute, MTD
The code private data structure that the privately owned description information body that memory device manufacturer is provided can be provided by MTD memory device manufacturer
Body, for the MTD memory device of NAND, the code private data structure that its manufacturer is provided can be with struct fsl_
This structure of elbc_mtd nandpriv describes its attribute.
The relating module 403 of accompanying drawing 4 example can include the second link setup unit 601, such as accompanying drawing 6（a）The shown present invention is another
What one embodiment provided realizes the device that same memory techniques equipment subregion mounts many attributes equipment.Second link setup unit 601, uses
Deposit in each of the structure of multiple chip attributes of described construction structure is respectively directed to the described MTD needing mounting
The code private data structure that memory device manufacturer is provided.
The adaptation module 402 of accompanying drawing 4 example can include structure structural unit 501 and the first link setup unit 502, association
Module 403 can include the second link setup unit 601, such as accompanying drawing 6（b）Realizing that shown another embodiment of the present invention provides is same interior
Deposit the device that technical equipment subregion mounts many attributes equipment, wherein：
Structure structural unit 501, for construction respectively with each of the plurality of sub- MTD subregion MTD subregion phase
The structure of the chip attribute answered；
First link setup unit 502, for pointing to described construction by corresponding for same memory techniques equipment MTD subregion structure
Multiple chip attributes structure；
Second link setup unit 601, for by each of the structure of multiple chip attributes of described construction structure
It is respectively directed to the code private data structure that the described MTD memory device manufacturer needing mounting is provided.
It should be noted that the content such as information exchange between each module/unit of said apparatus, implementation procedure, due to
The inventive method embodiment is based on same design, and the technique effect that it brings is identical with the inventive method embodiment, particular content
Can be found in the narration in the inventive method embodiment, here is omitted.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can
Completed with the hardware instructing correlation by program, one or more or whole of such as following various methods：
Same memory techniques equipment MTD subregion is expanded to many sub- MTD subregions；
It is adapted to a corresponding chip description information body for the sub- MTD subregion of each of the plurality of sub- MTD subregion；
Each chip description information body described privately owned is retouched with what the MTD memory device manufacturer needing mounting provided respectively
State informosome association.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can
Completed with the hardware instructing correlation by program, this program can be stored in a computer-readable recording medium, storage
Medium can include：Read only memory（ROM, Read Only Memory）, random access memory（RAM, Random
Access Memory）, Flash equipment, disk or CD etc..
Above to provided in an embodiment of the present invention realize same memory techniques equipment subregion mount plurality of devices method and
Device is described in detail, and specific case used herein is set forth to the principle of the present invention and embodiment, with
The explanation of upper embodiment is only intended to help and understands the method for the present invention and its core concept；General simultaneously for this area
Technical staff, according to the thought of the present invention, all will change in specific embodiments and applications, in sum,
This specification content should not be construed as limitation of the present invention.
Claims (8)
1. a kind of realize same memory techniques equipment subregion and mount the method for many attributes equipment it is characterised in that methods described bag
Include：
Same memory techniques equipment MTD subregion is expanded to many sub- MTD subregions；
It is adapted to a corresponding chip description information body for the sub- MTD subregion of each of the plurality of sub- MTD subregion；
The privately owned description letter that each chip description information body described is provided with the MTD memory device manufacturer needing mounting respectively
Breath body association.
2. the method for claim 1 is it is characterised in that described chip description information body is the structure of description chip attribute
Body, the code that the privately owned description information body that described MTD memory device manufacturer is provided is provided by MTD memory device manufacturer is privately owned
Data structure.
3. method as claimed in claim 2 is it is characterised in that described divide for each of the plurality of sub- MTD subregion MTD
Area is adapted to a corresponding chip description information body and includes：
The construction structure with each of the plurality of sub- MTD subregion corresponding chip attribute of sub- MTD subregion respectively；
Corresponding for same memory techniques equipment MTD subregion structure is pointed to the structure of multiple chip attributes of described construction.
4. method as claimed in claim 3 it is characterised in that described by each chip description information body described respectively with needs
The vendor code privately owned description information body association of the MTD original device of mounting includes：
Each of the structure of multiple chip attributes by described construction structure is respectively directed to the described MTD needing mounting
The code private data structure that memory device manufacturer is provided.
5. a kind of realize same memory techniques equipment subregion and mount the device of many attributes equipment it is characterised in that described device bag
Include：
Subregion expansion module, for expanding to many sub- MTD subregions by same memory techniques equipment MTD subregion；
Adaptation module, for being adapted to a corresponding chip description letter for the sub- MTD subregion of each of the plurality of sub- MTD subregion
Breath body；
Relating module, for being carried each chip description information body described respectively with the MTD memory device manufacturer needing mounting
For code privately owned description information body association.
6. device as claimed in claim 5 is it is characterised in that described chip description information body is the structure of description chip attribute
Body, the code that the privately owned description information body that described MTD memory device manufacturer is provided is provided by MTD memory device manufacturer is privately owned
Data structure.
7. device as claimed in claim 6 is it is characterised in that described adaptation module includes：
Structure structural unit, for construction respectively with each of the plurality of sub- MTD subregion corresponding chip of sub- MTD subregion
The structure of attribute；
First link setup unit, for pointing to the multiple of described construction by corresponding for same memory techniques equipment MTD subregion structure
The structure of chip attribute.
8. device as claimed in claim 7 is it is characterised in that described relating module includes：
Second link setup unit, for being respectively directed to each of the structure of multiple chip attributes of described construction structure
The code private data structure that the described MTD memory device manufacturer needing mounting is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210495019.9A CN103853496B (en) | 2012-11-28 | 2012-11-28 | Method and device for hooking various devices in same memory technology device partition |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210495019.9A CN103853496B (en) | 2012-11-28 | 2012-11-28 | Method and device for hooking various devices in same memory technology device partition |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103853496A CN103853496A (en) | 2014-06-11 |
| CN103853496B true CN103853496B (en) | 2017-02-22 |
Family
ID=50861213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210495019.9A Active CN103853496B (en) | 2012-11-28 | 2012-11-28 | Method and device for hooking various devices in same memory technology device partition |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103853496B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104573421B (en) * | 2014-12-30 | 2017-12-22 | 北京兆易创新科技股份有限公司 | A kind of MCU chip information protecting method and device based on some subregions |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101169726A (en) * | 2007-11-28 | 2008-04-30 | 浪潮电子信息产业股份有限公司 | Embedded type Linux system on-line upgrading method based on MTD partition |
| KR20080081470A (en) * | 2007-03-05 | 2008-09-10 | 삼성전자주식회사 | File system management method and apparatus for embedded linux based set-top box |
| CN101344854A (en) * | 2008-08-22 | 2009-01-14 | 四川长虹电器股份有限公司 | Method for upgrading embedded type Linux equipment through SD card |
| CN101458656A (en) * | 2007-12-12 | 2009-06-17 | 安凯（广州）软件技术有限公司 | Method for multimedia application processor compatible with various NandFlash |
| CN101470663A (en) * | 2007-12-29 | 2009-07-01 | 安凯（广州）软件技术有限公司 | Method for processing address discontinuity in MTD design of NAND flash memory |
| CN102298555A (en) * | 2011-08-22 | 2011-12-28 | 宜兴市华星特种陶瓷科技有限公司 | Modular flash management system based on Not AND (NAND) technology |
-
2012
- 2012-11-28 CN CN201210495019.9A patent/CN103853496B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080081470A (en) * | 2007-03-05 | 2008-09-10 | 삼성전자주식회사 | File system management method and apparatus for embedded linux based set-top box |
| CN101169726A (en) * | 2007-11-28 | 2008-04-30 | 浪潮电子信息产业股份有限公司 | Embedded type Linux system on-line upgrading method based on MTD partition |
| CN101458656A (en) * | 2007-12-12 | 2009-06-17 | 安凯（广州）软件技术有限公司 | Method for multimedia application processor compatible with various NandFlash |
| CN101470663A (en) * | 2007-12-29 | 2009-07-01 | 安凯（广州）软件技术有限公司 | Method for processing address discontinuity in MTD design of NAND flash memory |
| CN101344854A (en) * | 2008-08-22 | 2009-01-14 | 四川长虹电器股份有限公司 | Method for upgrading embedded type Linux equipment through SD card |
| CN102298555A (en) * | 2011-08-22 | 2011-12-28 | 宜兴市华星特种陶瓷科技有限公司 | Modular flash management system based on Not AND (NAND) technology |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103853496A (en) | 2014-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| AitSahlia et al. | Is concurrent engineering always a sensible proposition? | |
| WO2019037203A1 (en) | Application program performance testing method, device, computer equipment, and storage medium | |
| CN105893234B (en) | Method and calculating equipment for software test | |
| CN110110174A (en) | Generation, monitoring and the methods of exhibiting of the data visualization page, browser and server | |
| CN107678946B (en) | Model-based airborne embedded software test environment construction method | |
| CN104965757A (en) | Virtual machine live migration method, virtual machine migration management apparatus, and virtual machine live migration system | |
| CN114327861B (en) | Method, device, system and storage medium for executing EDA task | |
| WO2016209324A1 (en) | Controlling application deployment based on lifecycle stage | |
| CN104461649B (en) | chip compatible method and device | |
| CN110389903B (en) | Test environment deployment method and device, electronic equipment and readable storage medium | |
| CN107818104B (en) | Database deployment method, database deployment device, control equipment and system | |
| CN111988160B (en) | Method and device for deploying virtualized network function | |
| CN104753706B (en) | A kind of distributed type assemblies configuring management method and device | |
| CN103744647A (en) | Java workflow development system and method based on workflow GPD | |
| CN103856548A (en) | Dynamic resource scheduling method and dynamic resource scheduler | |
| CN108418752B (en) | A kind of creation method and device of aggregation group | |
| CN108874520A (en) | Calculation method and device | |
| CN105634635B (en) | A kind of methods, devices and systems of shared RTC | |
| CN104331333B (en) | Computer implemented method and computing system | |
| CN105187250A (en) | Method and system for deploying nodes based on component template | |
| CN103853496B (en) | Method and device for hooking various devices in same memory technology device partition | |
| CN101141315A (en) | Network resource scheduling simulation system | |
| US20070038836A1 (en) | Simulating partition resource allocation | |
| CN114153732A (en) | Fault scene testing method and device, electronic equipment and storage medium | |
| Sahli et al. | A BRS-based approach to model and verify cloud systems elasticity |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20231221 Address after: Room 1-9, 24th Floor, Unit 2, Building 1, No. 28, North Section of Tianfu Avenue, High tech Zone, Chengdu City, Sichuan Province, 610095 Patentee after: Sichuan Huakun Zhenyu Intelligent Technology Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |
|
| TR01 | Transfer of patent right |