CN101465343A - Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof - Google Patents
Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof Download PDFInfo
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- CN101465343A CN101465343A CN 200710160820 CN200710160820A CN101465343A CN 101465343 A CN101465343 A CN 101465343A CN 200710160820 CN200710160820 CN 200710160820 CN 200710160820 A CN200710160820 A CN 200710160820A CN 101465343 A CN101465343 A CN 101465343A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
The invention provides a vertically and electrically self-connected three-dimensional stack chip structure and a manufacturing method thereof; wherein, respective electrical conductive wire layers are formed among the three-dimensional stack chips and then extended to the sidewalls of the chips; the respective electrical conductive wire layers which are buried among the layers and exposed out of the sidewalls of the chips are used to carry out electroless metal self-deposition to grow up isotropically, so as to form a vertical and electrical conductive wire along the sidewalls of the stack chips; the vertical and electrical conductive wire is then connected with each electrical conductive layer to complete the vertical and electrical self-connection of the three-dimensional stack chips.
Description
Technical field
The present invention is about a kind of three-dimensional stack chip structure and manufacture method thereof; Particularly relevant for self-three-dimensional stack chip structure and the manufacture method thereof that connects of a kind of tool vertical electrical.
Background technology
For compact, the power saving and the dynamical demand trend of catering to following electronic product, the structure of conventional semiconductors two dimension (2D) chip dress has not met following product demand with line connection at present.Therefore, the connected mode that the chip lead layout type of two dimension is changed into three-dimensional (3D) can effectively solve the technical bottleneck that conventional two-dimensional chip lead layout type is met with.The storehouse mode of three-dimensional chip can effectively increase the advantages such as component density, reduction chip size size and energy loss of unit are.
United States Patent (USP) the 5th, disclose a kind of three-dimensional stack chip manufacture method 279, No. 991, after first cut crystal is separated each chip, a plurality of chip stacks are got up, utilize the metal vacuum sputtering method to be connected again with the chip sidewall lead that photoetching process forms stack chip.United States Patent (USP) the 5th, 517, No. 057, the 5th, 502, No. 667, the 5th, 561, No. 622, the 5th, 563, No. 086, the 5th, 614, No. 277, the 5th, 648, No. 684, the 5th, 763, No. 943, the 5th, 907, No. 178 and the 5th, 930, the first cut crystal of the three-dimensional stack chip manufacture method that discloses for No. 098 is separated each chip, will desire the chip stack of storehouse again, utilizes metal vacuum sputter mode to be connected with the chip sidewall lead that photoetching process forms stack chip afterwards again.Aforementioned three-dimensional stack chip manufacture method is applied to the storehouse of same size size chip.The chip of different size size then is put in by the superiors of stack chip, connects and utilize the routing mode to form metal.United States Patent (USP) the 6th, 177 after a kind of three-dimensional stack chip manufacture method of No. 296 announcements goes out each chip with the wafer cutting and separating earlier, will be desired the chip stack of storehouse again, and the chip side-wall metallic of utilizing conducting resinl to form stack chip again connects.United States Patent (USP) the 6th, 188, after the three-dimensional stack chip manufacture method that discloses for No. 129 goes out each chip with the wafer cutting and separating earlier, to desire the chip stack of storehouse again, utilize metal vacuum sputter mode to be connected afterwards again, and directly form tin ball projection on the sidewall of stack chip with the chip side-wall metallic that photoetching process forms stack chip.United States Patent (USP) the 7th, 102, a kind of three-dimensional stack chip manufacture method of No. 238 announcements forms the sidewall of plain conductor in front wafer surface, the back side and chip edge in the wafer scale mode.The storehouse mode of chip utilizes the tin ball projection of chip chamber to do to electrically connect conducting.United States Patent (USP) the 7th, 208, the first cut crystal of the three-dimensional stack chip manufacture method of No. 343 announcements will be desired the chip stack of storehouse again to separate each chip, and the side-wall metallic of utilizing conducting resinl to form stack chip afterwards again connects.
Aforementioned known various three-dimensional stack chip manufacture method all need use quite expensive equipment and complex process consuming time, makes these three-dimensional stack chip manufacture methods spend quite high cost.In view of the above, demand providing a kind of three-dimensional stack chip structure and manufacture method thereof that reduces manufacturing cost urgently.
Summary of the invention
The invention provides three-dimensional stack chip structure and manufacture method thereof that a kind of tool vertical electrical oneself connects, the vertical electrical oneself who adopts the low-cost electroless plating techniques (electroless plating technique) of non-photoetching process to finish between three-dimensional stack chip connects.
The three-dimensional stack chip structure that a kind of tool vertical electrical oneself provided by the invention connects comprises: most chips of storehouse from bottom to up, and wherein at least two described chips have most corresponding its at least one sides of chip of metal gaskets respectively; Majority layer first insulating barrier are formed at the first surface top of each this chip respectively and expose described metal gasket, and this first insulating barrier are passed in each this metal gasket top formation one electrical contact; Most layer electric lead layers, be formed at this first insulating barrier top of each this chip, this electric lead layer comprises this sides of chip that most bar electric leads extend to the corresponding described metal gasket of this chip, and each this metal gasket electrically contacts by it and is electrically connected at a corresponding aforementioned electric lead; Most layer second insulating barrier, this first insulating barrier top that is formed at each this chip coats this chip and makes the described electric lead of its this sides of chip expose out; And most bar vertical electrical leads, be formed at this sides of chip of described stack chip and electrically connect the described electric lead that is exposed to this sides of chip, to set up the vertical electrical oneself conducting of this three-dimensional stack chip.
On the other hand, the three-dimensional stack chip structure making process step that a kind of tool vertical electrical oneself provided by the invention connects comprises: a wafer is provided, be formed with most chips on this wafer, have a Cutting Road between the adjacent described chip, each this chip has most metal gaskets; Form a chase on this wafer in each Cutting Road; Form one first insulating barrier on this wafer and in wherein forming most openings, so that described metal gasket exposes to the open air out; Form an electric lead layer on this first insulating barrier, this electric lead layer comprises most bar electric leads and extends across described chase, and makes described metal gasket electrically connect corresponding this electric lead respectively; Form one second insulating barrier in this electric lead layer top; One temporary base is fitted on this second insulating barrier; This bottom of wafer is thinned to corresponding position, described chase position; Remove this temporary base, to obtain a wafer that comprises aforementioned electrical conductor layer; Most the wafer contrapositions that comprise aforementioned electrical conductor layer are engaged storehouse together; Form a groove in each Cutting Road of the described wafer butt joint of storehouse, expose the some of each this electric lead of bar with side direction; Carry out electroless plating, form most bar vertical electrical leads with a sidewall and electrically connect this side-walls by exposed described electric lead in each groove; And carry out the wafer cutting, to form most three-dimensional stack chips.
In addition, the invention provides the three-dimensional stack chip structure that another kind of tool vertical electrical oneself connects, it comprises: at least two chips of mutual storehouse, and corresponding its at least one sides of chip of each this chip has most metal gaskets; One electric lead layer is formed at the upper surface of each this chip, and this electric lead layer comprises most bar electric leads, and wherein each this metal gasket electrically connects an aforementioned electric lead; One first insulating barrier is formed at lower floor chip upper surface top and exposes the some of described electric lead; One second insulating barrier is formed at the some that upper strata chip upper surface top this upper strata chip of coating and side direction expose its described electric lead; And most bar vertical electrical leads, be formed at least one this sides of chip of this upper strata chip and electrically connect exposed this electric lead aforementioned electric lead corresponding of one bar side direction respectively with this lower floor's chip.
The manufacturing method of chip that the present invention also provides a kind of electric property oneself to connect, it comprises: a chip is provided, and this chip has most metal gaskets and is formed on the surface thereof; And carry out electroless plating, to form a metal level on each this metal gasket outer surface, the metal level between wherein adjacent described metal gasket is electrically contact each other.
The three-dimensional stack chip manufacture method that the present invention also provides another kind of electric property oneself to connect, it comprises: one first chip is provided, and this first chip has most metal gaskets in the surface thereof below; Form one first insulating barrier this surface, and make described metal gasket expose to the open air out in this first chip; One second chip is provided, and this second chip has most metal gaskets in the surface thereof below; Form one second insulating barrier this upper surface top, and make described metal gasket expose to the open air out in this second chip; Form a wall on this first insulating barrier of this first chip; This second chip docked the metal gasket mode with metal gasket be stacked over this first chip top; And carry out electroless plating, to form a Metal Contact between each described metal gasket to correspondence.
The vertical electrical oneself that the present invention adopts simple electroless plating to finish the three-dimensional stack chip of the present invention connects, and (Through Silicon Via, TSV) technology is set up the vertical electrical conducting need not use expensive silicon perforation.So the invention provides a kind of three stack chip structure and manufacture methods thereof of tool low-cost advantage.
Description of drawings
Figure 1A to Figure 1B is connected to form the schematic diagram of technology for electrical oneself between the metal gasket that shows a chip;
Fig. 2 A to Fig. 2 J is the structural section schematic diagram according to three-dimensional each step correspondence of stack chip structure making process of the tool vertical electrical oneself connection of one embodiment of the invention;
Fig. 3 A is for looking schematic diagram on the three-dimensional stack chip structure of Fig. 2 J;
Fig. 3 B is the schematic side view of Fig. 3 A along A-A ' line;
Fig. 3 C is the schematic cross-section of Fig. 3 A along B-B ' line;
Fig. 4 A to Fig. 4 D is for showing the various electric connection schematic diagrames of the three-dimensional stack chip structure of the present invention;
Fig. 5 A to Fig. 5 C is the structural section schematic diagram that one of the three-dimensional stack chip structure making process that connects of the tool vertical electrical oneself of Fig. 2 changes each step correspondence of example;
Fig. 6 is the three-dimensional stack chip structural section schematic diagram that tool vertical electrical oneself according to another embodiment of the present invention connects; And
Fig. 7 is according to the electrically self-stack chip structural section schematic diagram that connects between the tool metal gasket of another embodiment again of the present invention.
Drawing reference numeral:
2a, 2b, the three-dimensional stack chip of 2c, 2d----
10----chip 102----metal gasket
The 104----metal level
20,20a, 20b, 20c----wafer
The 21----temporary base
60,62,70,72----chip 64----adhesion layer
200a, 200b----chip 201----chase
202----metal gasket 203----first insulating barrier
204----opening 205----electric lead layer
205a----electric lead 206----second insulating barrier
207----groove 208----opening
209----vertical electrical lead 210----Metal Contact
211----conductive projection 212----insulating properties protective layer
602,622----metal gasket
603a, 603b----first electric lead
604----first insulating barrier
623a, 623b----second electric lead
624----second insulating barrier
625a, 625b----vertical electrical lead
626----Metal Contact 627----conductive projection
702,722----metal gasket 704,724----insulating barrier
725----wall 726----Metal Contact
Embodiment
Figure 1A and Figure 1B are the schematic diagram that 102 electrical oneselfs of each metal gasket are connected to form technology on the chip 10, it adopts electroless plating (electroless plating process) that metal 104 is deposited on each metal gasket 102, metal 104 grades that make deposition are to growing up, and then, connect with the electrical oneself who forms 102 of each metal gaskets at 102 formation of each metal gasket metal bridge joint.The present invention further is applied in the framework of three-dimensional stack chip with this notion, sets up vertical electrical conducting between three-dimensional stack chip with simple electroless plating.
Three-dimensional stack chip structure and manufacture method thereof that tool vertical electrical oneself of the present invention connects by following examples conjunction with figs., will be described in detail as follows:
Fig. 2 A to Fig. 2 J is the structural section schematic diagram according to three-dimensional each step correspondence of stack chip structure making process of the tool vertical electrical oneself connection of one embodiment of the invention.Please refer to Fig. 2 A, one wafer 20 at first is provided, silicon wafer for example, be formed with most chip 200a, 200b on this wafer 20, has a Cutting Road (not shown) between adjacent described chip 200a, the 200b, and each this chip 200a and/or 200b have most metal gaskets 202, for example aluminium pads.Please refer to Fig. 2 B, utilize cutting tool or laser or etching mode each Cutting Road on this wafer 20 to form a chase 201.Then, form one first insulating barrier 203 in these wafer 20 tops and insert described chase 201.Afterwards, form most openings 204 in this first insulating barrier 203, to expose described metal gasket 202.Please refer to Fig. 2 C, form an electric lead layer 205 on this first insulating barrier 203.This electric lead layer 205 comprises most bar electric leads and extends across described chase 201, and makes described metal gasket 202 electrically connect corresponding this electric lead 205a respectively.This electric lead layer 205 can be an aluminum metal layer or copper metal layer and can include adhesion layer Titanium (Ti) or tungsten titanium (TiW) or chromium metal materials such as (Cr).Please refer to Fig. 2 D, then form one second insulating barrier 206 in these electric lead layer 205 tops, this second insulating barrier 206 can be that a tool chip sticks together the insulating barrier of function.Please refer to Fig. 2 E, a temporary base (handlingsubstrate) 21 is temporarily fitted on this second insulating barrier 206, and these wafer 20 grinding back surfaces are thinned to described chase 201 corresponding positions.The wafer thickness of thinning of the present invention is preferable less than 20 microns (μ m).Afterwards, again this temporary base 21 is removed from these wafer 20 tops, have the chip thinning of this electric lead layer 205 with formation.Please refer to Fig. 2 F, repeat abovementioned steps, form a plurality of chip thinning 20a, 20b respectively with this electric lead layer 205.With described chip thinning 20a, 20b with this electric lead layer 205 and aforementioned chip thinning 20 and with this electric lead layer 205 not the wafer 20c contraposition with this electric lead layer 205 of thinning engage storehouse together, wherein said second insulating barrier 206 can have chip and stick together function or for example described wafer and utilize the adhesion layer (not shown) that is engaged with each other between any two.Please refer to Fig. 2 G, form a groove 207 in each Cutting Road that described wafer 20,20a, 20b, the 20c of storehouse dock, expose the some of this electric lead of each bar 205a with side direction, in this second insulating barrier 206 of this superiors' wafer 20, form most openings 208 simultaneously, so that the part surface of its this electric lead layer 205 exposes to the open air out.Please refer to Fig. 2 H, then carry out electroless plating (elctroless plating process), to deposit a metal level in the exposed part of the side direction of described electric lead 205a, grade by described metal level contacts with each other adjacent described metal level to growth, connects corresponding described electric lead 205 and form a vertical electrical lead 209.Form a Metal Contact 210 simultaneously and in this second insulating barrier 206 of the superiors' wafer 20, also electrically contact corresponding this metal gasket 202.Can form the aforementioned vertical electrical lead 209 of most bars at each groove 207 sidewall of described storehouse wafer 20,20a, 20b, 20c by aforementioned electroless plating.Described vertical electrical lead 209 and Metal Contact 210 can comprise copper, nickel, tin, gold or its combination.Please refer to Fig. 2 I, then form conductive projection 211 for example tin ball projection in described Metal Contact 210 tops of this superiors' wafer 20, to provide and the extraneous path that electrically conducts.Please refer to Fig. 2 J, carry out the wafer cutting, have three-dimensional stack chip 2a, the 2b that the vertical electrical oneself connects to form most.
Fig. 3 A be aforementioned have three- dimensional stack chip 2a, 2b that vertical electrical oneself connects on look schematic diagram, Fig. 3 B is along the side schematic view of A-A ' line among Fig. 3, and Fig. 3 C is the schematic cross-section of Fig. 3 A along B-B ' line, wherein Fig. 3 C is the three-dimensional stack chip 2b cross section structure of corresponding diagram 2J, and wherein element numbers is omitted from accompanying drawing.
The three-dimensional stack chip structure that the tool vertical electrical oneself that the inventive method forms connects can be just like the vertical electrical connected mode of Fig. 4 A to Fig. 4 D, wherein Fig. 4 A is that the vertical electrical that has between second chip to the four-core sheet (IC2-IC3-IC4) connects, Fig. 4 B has second chip to be connected with vertical electrical between the four-core sheet (IC2-IC4), Fig. 4 C has the 3rd chip (IC3) and extraneous electric connection, and Fig. 4 D has second chip (IC2) and extraneous electric connection.In addition, if the orlop chip is desired to electrically connect with extraneous, then can design the electric lead layer that is not connected across its adjacent Cutting Road with its aluminium pad in other layer chip.
Moreover the present invention also can form a protective layer and cover and protect described vertical electrical lead in each chip sidewall of described three- dimensional stack chip 2a, 2b, shown in Fig. 5 A to Fig. 5 C.Fig. 5 A after the corresponding processing step of Fig. 2 H is finished, then forms described Metal Contact 210 tops of an insulating properties protective layer 212 in this upper strata chip 20 again, and covers described vertical electrical lead 209 simultaneously, and make described Metal Contact 210 expose to the open air out.Please refer to Fig. 5 B, then form a conductive projection 211 these Metal Contact 210 tops, to set up and the extraneous path that electrically connects in this upper strata chip 20.Please refer to Fig. 5 C, then carry out the wafer cutting, to form most three- dimensional stack chip 2c, 2d.
Fig. 6 is for three-dimensional according to another embodiment of the present invention stack chip structural section schematic diagram, and in this embodiment, this three-dimensional stack chip comprises the chip 60,62 of two different chip size sizes, and both engage storehouse together by an adhesion layer 64.This chip 60 has most metal gaskets 602, for example aluminium pads.One first electric lead layer is formed at this chip 60 upper surfaces, and this first electric lead layer comprises most bar first electric lead 603a, 603b, so that described metal gasket 602 is electrically connected to the first electric lead 603a, the 603b of a correspondence.One first insulating barrier 604 is formed at this first electric lead layer top and the part surface exposure of the described first electric lead 603a, 603b is come out.This chip 62 has most metal gaskets 622, for example aluminium pads.One second electric lead layer is formed at this chip 62 tops, this second electric lead layer comprises most bar second electric lead 623a, 623b, extend to the relative sides of chip of this chip 62 respectively, and make the described second electric lead 623a, 623b side direction expose out.This metal gasket 622 of this chip 62 is electrically connected to the second electric lead 623b of a correspondence.One second insulating barrier 624 is formed at this second electric lead layer top, and makes the part surface of this second electric lead 623a expose to the open air out.In this embodiment, carry out electroless plating, to be deposited a metal level respectively by exposed part and the described second electric lead 623a, the exposed part of 623b side direction at the described first electric lead 603a and 603b.Described metal levels etc. are to growing up until contacting with each other, and form a vertical electrical lead 625a between this first electric lead 603a and this second electric lead 623a of correspondence, and form a vertical electrical lead 625b between this first electric lead 603b and this second electric lead 623b of correspondence.Deposition forms a Metal Contact 626 also electrically contacts a correspondence in this second insulating barrier 624 the second electric lead 623a simultaneously.Then, form most conductive projections 627 for example tin ball projection electrically connect so that this second electric lead 623a can set up with the external world in these second insulating barrier, 624 tops.In this embodiment, described first electric lead 603a and 603b are identical with the described electric lead 205a material of the described second electric lead 623a, 623b and Fig. 2, and described vertical electrical lead 625a, 625b are identical with described vertical electrical lead 209 materials of Fig. 2.Preferable by the thickness of this chip 62 of storehouse less than 20 microns (μ m).
The notion that the present invention utilizes electroless plating to form electrical oneself's connection lead also can be applicable to two chip chamber metal gaskets electrical oneself relative to each other and connects.Fig. 7 is the present invention's structural section schematic diagram of another embodiment again.In this embodiment, chip stack structure of the present invention comprise two fronts to the front each other contraposition engage storehouse chip 70,72 together, wherein this chip 70 has most metal gaskets 702, aluminium pad for example, and an insulating barrier 704 is formed at this chip 70 tops, and makes the part surface of described metal gasket 702 expose to the open air out.This chip 72 has most metal gaskets 722, aluminium pad for example, and another insulating barrier 724 is formed on this chip 72, and make the part surface of described metal gasket 722 expose to the open air out.In this embodiment, described chip 70,72 fronts to the front each other contraposition engage storehouse together, and make described metal gasket 702,722 mutual contrapositions.One wall 725 between described chip 70,72 to form the gap between the two.In this embodiment, carry out electroless plating and form a Metal Contact 726 between each described metal gasket 702,722 correspondence with deposition.
The inventive method also can be applicable to chip to wafer or the wafer wafer scale structure dress technology to wafer except can be applicable to the storehouse of chip to chip.
The above is specific embodiments of the invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the protection range.
Claims (26)
1. the three-dimensional stack chip structure that connects of tool vertical electrical oneself is characterized in that this three-dimensional stack chip structure comprises:
A most chip, described chip is three-dimensional stack architecture from bottom to up, and at least two described chips have most corresponding its at least one sides of chip of metal gasket respectively;
One first insulating barrier is formed at the first surface top of each described chip and exposes described metal gasket, and each this metal gasket top forms an electrical contact and passes described first insulating barrier;
One electric lead layer, be formed at first insulating barrier top of each described chip, this electric lead layer comprises the sides of chip that most bar electric leads extend to the corresponding described metal gasket of described chip, and each metal gasket electrically contacts by it and is electrically connected at a corresponding aforementioned electric lead;
One second insulating barrier, first insulating barrier top that is formed at each described chip coats this chip and makes the described electric lead of its sides of chip expose out; And
Most bar vertical electrical leads are formed at described sides of chip and electrically connect the described electric lead that is exposed to described sides of chip.
2. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects, it is characterized in that this three-dimensional stack chip structure also comprises most conductive projections and is positioned at the first surface top of the superiors' chip and is electrically coupled to corresponding described electric lead.
3. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects is characterized in that described second insulating barrier has chip and sticks together function.
4. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects is characterized in that described chip has an adhesion layer between any two.
5. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects is characterized in that the described electric lead of described electric lead layer comprises aluminium or copper.
6. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects is characterized in that described electric lead contains the metal adhesion layer that titanium, tungsten titanium or chromium are formed.
7. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects is characterized in that described vertical electrical lead forms with electroless deposition method.
8. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 7 connects is characterized in that described vertical electrical lead comprises copper, nickel, tin, gold or its combination.
9. the three-dimensional stack chip structure that tool vertical electrical as claimed in claim 1 oneself connects is characterized in that, by each described chip thickness of storehouse less than 20 microns.
10. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 1 connects is characterized in that this three-dimensional stack chip structure also comprises a protective layer and coats described vertical electrical lead.
11. the three-dimensional stack chip structure that tool vertical electrical oneself connects is characterized in that this three-dimensional stack chip structure comprises:
At least two chips of mutual storehouse, corresponding its at least one sides of chip of each described chip has most metal gaskets;
One electric lead layer is formed at the upper surface of each described chip, and this electric lead layer comprises most bar electric leads, and wherein each described metal gasket electrically connects an aforementioned electric lead;
One first insulating barrier is formed at lower floor chip upper surface top and exposes the some of described electric lead;
One second insulating barrier is formed at the some that upper strata chip upper surface top coating described upper strata chip and side direction expose its described electric lead; And
Most bar vertical electrical leads are formed at least one sides of chip of described upper strata chip and electrically connect one bar side direction exposed an electric lead and a corresponding aforementioned electric lead of described lower floor chip respectively.
12. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 11 connects is characterized in that described chip has same size size or different size size.
13. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 11 connects, it is characterized in that, this three-dimensional stack chip structure also comprises most conductive projections and is positioned at described second insulating barrier top, at least one an aforementioned electric lead of wherein said upper strata chip and a described conductive projection electric property coupling.
14. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 11 connects is characterized in that described vertical electrical lead forms with electroless deposition method.
15. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 14 connects is characterized in that described vertical electrical lead comprises copper, nickel, tin, gold or its combination.
16. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 11 connects is characterized in that the described electric lead of described upper strata chip and lower floor's chip comprises aluminium or copper.
17. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 11 connects is characterized in that described electric lead contains the metal adhesion layer that titanium, tungsten titanium or chromium are formed.
18. the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 11 connects is characterized in that this three-dimensional stack chip structure also comprises an insulating properties adhesion layer between described upper strata chip and lower floor's chip.
19. the three-dimensional stack chip structure that tool vertical electrical as claimed in claim 11 oneself connects is characterized in that, by the described chip thickness of storehouse less than 20 microns.
20. the manufacture method of the three-dimensional stack chip structure of tool vertical electrical oneself connection is characterized in that this method comprises:
One wafer is provided, is formed with most chips on this wafer, have a Cutting Road between the adjacent described chip, each described chip has most metal gaskets;
Form a chase on described wafer in each Cutting Road;
Form one first insulating barrier on described wafer and in wherein forming most openings, so that described metal gasket exposes to the open air out;
Form an electric lead layer on described first insulating barrier, this electric lead layer comprises most bar electric leads, so that described metal gasket electrically connects a corresponding electric lead respectively, described electric lead extends across described chase;
Form one second insulating barrier in described electric lead layer top;
One temporary base is fitted on described second insulating barrier;
Described bottom of wafer is thinned to corresponding position, described chase position;
Remove described temporary base, to obtain a wafer that comprises aforementioned electrical conductor layer;
Most the wafer contrapositions that comprise aforementioned electrical conductor layer are engaged storehouse together;
Form a groove in each Cutting Road of the described wafer butt joint of storehouse, expose the some of the described electric lead of each bar with side direction;
Carry out electroless plating, form most bar vertical electrical leads, to electrically connect described side-walls by exposed described electric lead with a sidewall in each groove; And
Carry out the wafer cutting, to form most three-dimensional stack chips.
21. the manufacture method of the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 20 connects, it is characterized in that, forming aforementioned groove before each Cutting Road of the described wafer of storehouse, also comprise described wafer contraposition with aforementioned storehouse engage be stacked over one not thinning comprise on the wafer of aforementioned electrical conductor layer.
22. the manufacture method of the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 20 connects, it is characterized in that, before carrying out the wafer cutting, also comprise and form the described second insulating barrier top of most conductive projections, use each described three-dimensional stack chip and extraneous electrically conducting that follow-up formation is provided in the superiors' wafer.
23. the manufacture method of the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 20 connects is characterized in that described second insulating barrier has chip and sticks together function.
24. the manufacture method of the three-dimensional stack chip structure that tool vertical electrical oneself as claimed in claim 20 connects is characterized in that described vertical electrical lead comprises copper, nickel, tin, gold or its combination.
25. the manufacturing method of chip that the electric property oneself connects is characterized in that this manufacture method comprises:
One chip is provided, and this chip has most metal gaskets and is formed on the surface thereof; And
Carry out electroless plating, to form a metal level on each described metal gasket outer surface, the described metal level between wherein adjacent described metal gasket is electrically contact each other.
26. the three-dimensional stack chip manufacture method that the electric property oneself connects is characterized in that this manufacture method comprises:
One first chip is provided, and this first chip has most metal gaskets in the surface thereof below;
Form one first insulating barrier in the surface of described first chip, and make described metal gasket expose to the open air out;
One second chip is provided, and this second chip has most metal gaskets in the surface thereof below;
Form the upper surface top of one second insulating barrier, and make described metal gasket expose to the open air out in described second chip;
Form a wall on first insulating barrier of described first chip;
Described second chip docked the metal gasket mode with metal gasket be stacked over described first chip top; And
Carry out electroless plating, to form a Metal Contact between each described metal gasket to correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710160820 CN101465343A (en) | 2007-12-18 | 2007-12-18 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710160820 CN101465343A (en) | 2007-12-18 | 2007-12-18 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101465343A true CN101465343A (en) | 2009-06-24 |
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| CN 200710160820 Pending CN101465343A (en) | 2007-12-18 | 2007-12-18 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
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| CN103003938A (en) * | 2010-03-25 | 2013-03-27 | 国际商业机器公司 | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip |
| CN105023901A (en) * | 2015-08-13 | 2015-11-04 | 上海航天测控通信研究所 | Aluminum-substrate-based three-dimensional lamination chip packaging structure and preparation method thereof |
| CN106653731A (en) * | 2015-10-27 | 2017-05-10 | 晟碟信息科技（上海）有限公司 | Sidewall bridge interconnector in semiconductor device |
| CN110010494A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of system in package interconnection architecture production method of the side wall with pad |
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| CN110993518A (en) * | 2019-12-19 | 2020-04-10 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
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- 2007-12-18 CN CN 200710160820 patent/CN101465343A/en active Pending
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| CN103003938A (en) * | 2010-03-25 | 2013-03-27 | 国际商业机器公司 | Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip |
| CN103003938B (en) * | 2010-03-25 | 2016-01-13 | 国际商业机器公司 | Formed comprise have with engage before and after another chip thin between put the method for the Multi-chip laminating structure of chip |
| CN105023901A (en) * | 2015-08-13 | 2015-11-04 | 上海航天测控通信研究所 | Aluminum-substrate-based three-dimensional lamination chip packaging structure and preparation method thereof |
| CN105023901B (en) * | 2015-08-13 | 2017-10-24 | 上海航天电子通讯设备研究所 | A kind of encapsulating structure of 3-D stacks chip based on aluminium base and preparation method thereof |
| CN106653731A (en) * | 2015-10-27 | 2017-05-10 | 晟碟信息科技（上海）有限公司 | Sidewall bridge interconnector in semiconductor device |
| CN110010495A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of high density side wall interconnected method |
| CN110010494A (en) * | 2018-12-26 | 2019-07-12 | 杭州臻镭微波技术有限公司 | A kind of system in package interconnection architecture production method of the side wall with pad |
| CN110010494B (en) * | 2018-12-26 | 2021-04-06 | 浙江集迈科微电子有限公司 | Method for manufacturing system-in-package interconnection structure with side wall provided with bonding pad |
| CN110010495B (en) * | 2018-12-26 | 2021-05-28 | 浙江集迈科微电子有限公司 | High-density side wall interconnection method |
| CN111081687A (en) * | 2019-12-16 | 2020-04-28 | 东莞记忆存储科技有限公司 | Stacked chip packaging structure and packaging method thereof |
| CN111081687B (en) * | 2019-12-16 | 2022-02-01 | 东莞记忆存储科技有限公司 | Stacked chip packaging structure and packaging method thereof |
| CN110993518A (en) * | 2019-12-19 | 2020-04-10 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
| CN111863641A (en) * | 2020-07-28 | 2020-10-30 | 南通通富微电子有限公司 | Chip packaging method |
| WO2023010457A1 (en) * | 2021-08-05 | 2023-02-09 | 广东省科学院半导体研究所 | Chip stack packaging structure and chip stack packaging method |
| US11869872B2 (en) | 2021-08-05 | 2024-01-09 | Institute of semiconductors, Guangdong Academy of Sciences | Chip stack packaging structure and chip stack packaging method |
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