CN101459110A - Shallow groove isolation region and forming method thereof - Google Patents
Shallow groove isolation region and forming method thereof Download PDFInfo
- Publication number
- CN101459110A CN101459110A CNA2007100944963A CN200710094496A CN101459110A CN 101459110 A CN101459110 A CN 101459110A CN A2007100944963 A CNA2007100944963 A CN A2007100944963A CN 200710094496 A CN200710094496 A CN 200710094496A CN 101459110 A CN101459110 A CN 101459110A
- Authority
- CN
- China
- Prior art keywords
- sidewall oxide
- shallow trench
- isolation area
- channel isolation
- shallow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Element Separation (AREA)
Abstract
A method for forming a shallow trench isolation region comprises the steps of forming a shallow trench on a semiconductor substrate, forming a lateral wall oxide layer covered on the shallow trench, performing nitriding operation to the lateral wall oxide layer to form the isolation region, wherein the isolation layer covers the lateral wall oxide layer after nitriding operation and fills the shallow trench, thereby forming the shallow trench isolation region. The damage of the lateral wall of the shallow trench can be reduced during the process of forming the shallow trench isolation region. The shallow trench isolation region comprises the shallow trench, the lateral wall oxide layer and the isolation layer, wherein the shallow trench is formed in the semiconductor substrate, the lateral wall oxide layer covers the shallow trench, the isolation layer covers the lateral wall oxide layer and fills the shallow trench, and nitrogen is distributed in the lateral wall oxide layer. The lateral wall of the shallow trench is not easy to be damaged during the process of forming the shallow trench isolation region.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of shallow channel isolation area and forming method thereof.
Background technology
Along with the increase of integrated circuit integrated level, must constantly dwindle in order to the size in active region isolation district in the isolation of semiconductor devices.Be used to isolate the regional oxidizing process (LOCOS) of active area in the traditional handicraft because the oxidation at the active area edge causes the field oxide edge to have the shape of beak (Bird ' sbeak), and make that in semiconductor device effective isolation length is restricted between the active area.Because can avoid the shortcoming of above-mentioned zone oxidizing process, shallow trench isolation is from (Shallow Trenchlsolation, STI) technology is widely used in the isolation between the active area in the semiconductor device in recent years.
Current, the step that forms shallow channel isolation area comprises: at first, as shown in Figure 1a, form shallow trench 12 on the semiconductor-based end 10; Subsequently, shown in Fig. 1 b, form the sidewall oxide 20 that covers described shallow trench 12; At last, shown in Fig. 1 c, form the separator 30 that covers described sidewall oxide 20 and fill described shallow trench 12, to form shallow channel isolation area.
Yet,,, use high-density plasma chemical vapor deposition (HDPCVD) technology usually and form described separator with synchronous deposition-etching power for guaranteeing the filling effect of STI along with dwindling of device critical dimension.Owing to use deposition-etching-depositing operation when forming described separator, and, described separator and described sidewall oxide are oxide, the etching operation that relates to when causing forming described separator easily causes described shallow trench sidewall damage, then, influence the isolation effect of described shallow channel isolation area, and then, device performance influenced.
A kind of method that reduces shallow trench isolating side wall oxide layer stress and erosion that provides in the Chinese patent of disclosed notification number on March 19 in 2003 for CN1242466C, this method comprises the following steps: to provide substrate at least, and described substrate has first dielectric layer and covers second dielectric layer of described first dielectric layer; In described substrate, form groove; Form sidewall oxide, described sidewall oxide covers the sidewall and the bottom of described groove; Fill up described groove with dielectric material; And carry out on-site steam generation processing procedure to reoxidize described sidewall oxide, described on-site steam generation processing procedure comprises at least introduces oxygen and hydroxyl.
When forming shallow channel isolation area, the application said method seems and can reduce described shallow trench sidewall damage by the damage that reduces described sidewall oxide, but, said method is actual to be to utilize on-site steam generation processing procedure to repair the described shallow trench sidewall of wound in damaged condition, to form new sidewall oxide; What relate to is damage repair process afterwards, that is, use said method and can not fundamentally reduce described shallow trench sidewall damage.
Summary of the invention
The invention provides a kind of shallow channel isolation area formation method, can in the process that forms described shallow channel isolation area, reduce described shallow trench sidewall damage; The invention provides a kind of shallow channel isolation area, in it shallow trench sidewall subject to damage not in the process that forms described shallow channel isolation area.
A kind of shallow channel isolation area formation method provided by the invention comprises:
On the semiconductor-based end, form shallow trench;
Form the sidewall oxide that covers described shallow trench;
Described sidewall oxide is carried out the nitrogenize operation;
Form separator, described separator covers the sidewall oxide of the described nitrogenize operation of experience and fills described shallow trench, to form shallow channel isolation area.
Alternatively, described sidewall oxide comprises silicon dioxide; Alternatively, use thermal oxidation technology or ISSG technology and form described sidewall oxide; Alternatively, when using ISSG technology and forming described sidewall oxide, the reacting gas that relates to comprises H
2And O
2, described H
2And O
2Flow-rate ratio be 1:2; Alternatively, use DPN, NH
3RTP or stove formula RTN technology are carried out described nitrogenize operation; Alternatively, when using DPN technology and carrying out described nitrogenize operation, the reacting gas that relates to comprises N
2, described N
2Range of flow be 50～500sccm; Alternatively, when using DPN technology and carrying out described nitrogenize operation, also comprise buffer gas, described buffer gas comprises He, and the range of flow of described He is 100～500sccm; Alternatively, when using DPN technology and carrying out described nitrogenize operation, the reaction pressure scope is 10～50mT; Alternatively, after using DPN technology and carrying out described nitrogenize operation, have gradient nitrogen in the described sidewall oxide and distribute, the concentration of nitrogen by the interface of described sidewall oxide and described separator extremely the interface of described sidewall oxide and described shallow trench reduce gradually.
A kind of shallow channel isolation area provided by the invention comprises the separator that is formed at the intrabasement shallow trench of semiconductor, covers the sidewall oxide of described shallow trench and covers described sidewall oxide and fill described shallow trench; Having nitrogen in the described sidewall oxide distributes.
Alternatively, have gradient nitrogen in the described sidewall oxide and distribute, the concentration of nitrogen by the interface of described sidewall oxide and described separator extremely the interface of described sidewall oxide and described shallow trench reduce gradually.
Compared with prior art, technique scheme has the following advantages:
The shallow channel isolation area formation method that technique scheme provides, by after forming described sidewall oxide, again described sidewall oxide is carried out the nitrogenize operation, has the sidewall oxide that nitrogen distributes in it to form, promptly, by the described sidewall oxide of nitrogenize,, can reduce the possibility of described shallow trench damaged in the process that forms described separator to strengthen the density of described sidewall oxide;
The optional mode of the shallow channel isolation area formation method that technique scheme provides forms described sidewall oxide by adopting on-site steam generation processing procedure, can strengthen the performance of the sidewall oxide of formation;
The optional mode of the shallow channel isolation area formation method that technique scheme provides, by the hydrogen that relates in the control on-site steam generation processing procedure and the ratio of oxygen is 1:2, can form described sidewall oxide in conjunction with wet-type oxidation technology and dry type oxidation technology, can strengthen the efficient of the sidewall oxide of formation, be beneficial on described shallow trench surface and form described sidewall oxide fully, reduce the possibility of described shallow trench damaged in the process that forms described separator;
The optional mode of the shallow channel isolation area formation method that technique scheme provides, use DPN technology and carry out described nitrogenize operation, distribute so that have gradient nitrogen in the described sidewall oxide, and the concentration of nitrogen is reduced gradually by the interface of described sidewall oxide and the described separator interface to described sidewall oxide and described shallow trench, can make when using this method formation shallow channel isolation area, after reducing described shallow trench damage, also can reduce the damage of described sidewall oxide;
The shallow channel isolation area that technique scheme provides, has the sidewall oxide that nitrogen distributes by in described shallow channel isolation area, forming, to strengthen the density of described sidewall oxide, can reduce the possibility of the shallow trench damaged that comprises in the described shallow channel isolation area;
The optional mode of the shallow channel isolation area that technique scheme provides, has the sidewall oxide that gradient nitrogen distributes by in described shallow channel isolation area, forming, and the concentration of nitrogen is reduced gradually by the interface of described sidewall oxide and the described separator interface to described sidewall oxide and described shallow trench, can make the described sidewall oxide that comprises in the described shallow channel isolation area have less damage.
Description of drawings
Fig. 1 a～1c is for forming each step schematic diagram of shallow channel isolation area in the explanation prior art;
Fig. 2 a～2d is each step schematic diagram of the formation shallow channel isolation area of the explanation embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
The concrete steps of using method formation shallow channel isolation area provided by the invention comprise:
Step 1: shown in Fig. 2 a, on the semiconductor-based end 100, form shallow trench 102.
The described semiconductor-based end 100, have passivation layer or the separator that forms in turn and the Semiconductor substrate (substrate) of passivation layer for defining device active region and surface.Described Semiconductor substrate comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).
The described semiconductor-based end 100, can utilize traditional twin well process to obtain, and promptly forms via operations such as oxidation growth, ion injection and annealing to have the Semiconductor substrate of corresponding NMOS and PMOS transistor active area.Described passivation layer can utilize low-pressure chemical vapor phase deposition (LPCVD) equipment, under high temperature (about 750 degrees centigrade) condition, generates silicon nitride (Si via ammonia and dichlorosilane reaction
3N
4) obtain.Described passivation material includes but not limited to a kind of or its combination in silicon nitride, silicon oxynitride (SiON), carborundum (SiC), silicon oxide carbide (SiCO) or the carbonitride of silicium (SiCN); Described oxide layer can utilize thermal oxidation technology to obtain, and described thermal oxidation technology can use high-temperature oxydation equipment or oxidation furnace carries out.The process that forms described passivation layer comprises steps such as deposition, grinding and detection; The process that forms described oxide layer can comprise thermal oxidation and detect step, specifically can use any traditional technology, does not repeat them here.
The step that forms described shallow trench 102 comprises: form patterned resist layer on the semiconductor-based end 100, surface, the described semiconductor-based ends 100 has passivation layer; With described patterned resist layer is mask, the described passivation layer of etching; With the described passivation layer after the etching is hard mask, the described semiconductor-based end 100 of etched portions.
Perhaps, the step that forms described shallow trench 102 comprises: form patterned resist layer on the semiconductor-based end 100, surface, the described semiconductor-based ends 100 has separator and the passivation layer that forms in turn; With described patterned resist layer is mask, the described passivation layer of etching; With the described passivation layer after the etching is hard mask, the order described separator of etching and the described semiconductor-based end 100 of part.
Step 2: shown in Fig. 2 b, form the sidewall oxide 120 that covers described shallow trench 102.
In described shallow trench 102, promptly form shallow channel isolation area behind the layer deposited isolating; In described shallow trench 102, need be pre-formed the sidewall oxide 120 that covers described shallow trench before the layer deposited isolating; The operation that forms described sidewall oxide 120 can utilize thermal oxidation technology or insitu moisture generate (insitu steam generation, ISSG) technology is carried out; The operation that forms described sidewall oxide 120 can be repaired the lattice damage of the semiconductor-based ends 100 that causes when forming described shallow trench 102; Also can reduce the damage that the plasma that relates in the process of subsequent deposition separator causes described shallow trench 102.
Usually, described sidewall oxide 120 comprises silicon dioxide; With 90nm technology is example, and the thickness of described sidewall oxide 120 is generally 10～100 dusts, as 30 dusts, 50 dusts.When adopting ISSG technology to form described sidewall oxide 120, the reacting gas that relates to comprises H
2And O
2, described H
2And O
2Flow-rate ratio be 1:2; By adopting flow-rate ratio is the H of 1:2
2And O
2ISSG technology carry out to form the operation of described sidewall oxide 120, can form described sidewall oxide in conjunction with wet-type oxidation technology and dry type oxidation technology, can strengthen the efficient of the sidewall oxide of formation, be beneficial on described shallow trench surface and form described sidewall oxide fully, reduce the possibility of described shallow trench damaged in the process that forms described separator.
Particularly, described H
2And O
2Range of flow be 10～50sccm, as 20sccm, 30sccm; The reaction temperature that relates to is 950～1100 degrees centigrade, as 1000 degrees centigrade, 1050 degrees centigrade; The reaction pressure that relates to is 10～20T, as 15T; The ISSG duration of the reaction was 10～50 seconds, as 20 seconds, 30 seconds.By adopting on-site steam generation processing procedure to form described sidewall oxide, can strengthen the performance of the sidewall oxide of formation.
Step 3: shown in Fig. 2 c, described sidewall oxide is carried out the nitrogenize operation, to form the sidewall oxide 122 of the described nitrogenize operation of experience.
The present inventor thinks after analyzing, and forms the sidewall oxide that has the nitrogen distribution in it, can strengthen the density of described sidewall oxide, can further reduce the possibility of described shallow trench damaged in the process that forms described separator.
Think after the present inventor's undergoing analysis and the practice, described sidewall oxide is carried out the nitrogenize operation, has the sidewall oxide that nitrogen distributes in it to form, promptly, by the described sidewall oxide of nitrogenize, to strengthen the density of described sidewall oxide, become the direction that reduces described shallow trench damage.
In the practice, can adopt DPN (decoupled plasma nitridation, uncoupling pecvd nitride), NH
3RTP (rapid thermal treatment) or stove formula RTN (Rapid Thermal Nitrided) technology are carried out described nitrogenize operation.
Use DPN technology and carry out described nitrogenize operation, can make and have the distribution of gradient nitrogen in the described sidewall oxide 122, and the concentration of nitrogen is reduced gradually by interface to the interface of described sidewall oxide 122 with described shallow trench of described sidewall oxide 122 with described separator, can make when using this method formation shallow channel isolation area, after reducing described shallow trench damage, also can reduce the damage of described sidewall oxide 122.
When using DPN technology and carrying out described nitrogenize operation, the reacting gas that relates to comprises N
2, described N
2Range of flow be 50～500sccm, as 100sccm, 200sccm or 300sccm; When using DPN technology and carrying out described nitrogenize operation, also comprise buffer gas, described buffer gas comprises He, and the range of flow of described He is 100～500sccm, as 200sccm, 300sccm or 400sccm; When using DPN technology and carrying out described nitrogenize operation, the reaction pressure scope is 10～50mT, as 20mT, 30mT; The reaction pressure scope is 25～70 degrees centigrade, as 50 degrees centigrade, 60 degrees centigrade; The reaction pressure that relates to is 10～50mT, as 20mT; The DPN operation duration was 15～60 seconds, as 30 seconds.
Also comprise PNA (post nitridation anneal, post-nitridation anneal) operation in the described DPN operation; When carrying out the PNA operation, the reaction temperature that relates to is 950～1100 degrees centigrade, as 1050 degrees centigrade; The reaction pressure that relates to is 0.5～50T, as 20T; The PNA operation duration was 15～60 seconds, as 30 seconds.
Step 4: shown in Fig. 2 d, form separator 140, described separator 140 covers the sidewall oxide 122 of the described nitrogenize operation of experience and fills described shallow trench 102, to form shallow channel isolation area.
The operation of filling described shallow trench 102 realizes by layer deposited isolating in described shallow trench 102 140; In the actual production, adopt deposition-etching-depositing operation to form described separator usually, described deposition-etching-depositing operation can utilize high-density plasma chemical vapor deposition (HDP) technology to carry out.
Described deposition-etching-depositing operation is: at first, and the described separator of deposition part; Then, the established separator of etched portions; And then sequential aggradation is isolated layering, to form separator.
It should be noted that described deposition-etching-depositing operation is not limited to utilize high-density plasma chemical vapor deposition (HDP) technology to carry out; Deposition that relates in described deposition-etching-depositing operation and etching operation all can be used arbitrary conventional deposition and the etching technics in the existing manufacture of semiconductor, as chemical vapor deposition method and plasma etch process.
Use the shallow channel isolation area formation method that the technical program provides, by after forming described sidewall oxide, again described sidewall oxide is carried out the nitrogenize operation, has the sidewall oxide that nitrogen distributes in it to form, promptly, by the described sidewall oxide of nitrogenize,, can reduce the possibility of described shallow trench damaged in the process that forms described separator to strengthen the density of described sidewall oxide
Especially, form described sidewall oxide by the mode that adopts ISSG technology to combine with DPN technology, can form gradient nitrogen in the described sidewall oxide of excellent performance distributes, and the concentration of nitrogen is reduced gradually by the interface of described sidewall oxide and the described separator interface to described sidewall oxide and described shallow trench, can make when using this method formation shallow channel isolation area, after reducing described shallow trench damage, also can reduce the damage of described sidewall oxide.
Based on identical design, shown in Fig. 2 d, the present invention also provides a kind of shallow channel isolation area, comprises the shallow trench 102 that is formed at at the semiconductor-based end 100, covers the sidewall oxide 120 of described shallow trench 102 and cover described sidewall oxide 120 and fill the separator 140 of described shallow trench 102; Having nitrogen in the described sidewall oxide 120 distributes.
Has the sidewall oxide that nitrogen distributes by in described shallow channel isolation area, forming, to strengthen the density of described sidewall oxide, can reduce the possibility of the shallow trench damaged that comprises in the described shallow channel isolation area.
Have gradient nitrogen in the described sidewall oxide 120 and distribute, the concentration of nitrogen is reduced gradually by interface to the interface of described sidewall oxide 120 with described shallow trench 102 of described sidewall oxide 120 with described separator 140.
Has the sidewall oxide that gradient nitrogen distributes by in described shallow channel isolation area, forming, and the concentration of nitrogen is reduced gradually by the interface of described sidewall oxide and the described separator interface to described sidewall oxide and described shallow trench, can make the described sidewall oxide that comprises in the described shallow channel isolation area have less damage.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (11)
1. a shallow channel isolation area formation method is characterized in that, comprising:
On the semiconductor-based end, form shallow trench;
Form the sidewall oxide that covers described shallow trench;
Described sidewall oxide is carried out the nitrogenize operation;
Form separator, described separator covers the sidewall oxide of the described nitrogenize operation of experience and fills described shallow trench, to form shallow channel isolation area.
2. shallow channel isolation area formation method according to claim 1 is characterized in that: described sidewall oxide comprises silicon dioxide.
3. shallow channel isolation area formation method according to claim 1 and 2 is characterized in that: described sidewall oxide forms the process using thermal oxidation technology or insitu moisture generates technology.
4. shallow channel isolation area formation method according to claim 3 is characterized in that: when site of deployment steam generated technology and forms described sidewall oxide, the reacting gas that relates to comprised H
2And O
2, described H
2And O
2Flow-rate ratio be 1:2.
5. shallow channel isolation area formation method according to claim 1 is characterized in that: use uncoupling plasma nitridation process, NH
3Quick thermal treatment process or stove formula Rapid Thermal Nitrided technology are carried out described nitrogenize operation.
6. shallow channel isolation area formation method according to claim 5 is characterized in that: when using the uncoupling plasma nitridation process and carrying out described nitrogenize operation, the reacting gas that relates to comprises N
2, described N
2Range of flow be 50～500sccm.
7. shallow channel isolation area formation method according to claim 6, it is characterized in that: when using the uncoupling plasma nitridation process and carrying out described nitrogenize operation, also comprise buffer gas, described buffer gas comprises He, and the range of flow of described He is 100～500sccm.
8. shallow channel isolation area formation method according to claim 5 is characterized in that: when using the uncoupling plasma nitridation process and carrying out described nitrogenize operation, the reaction pressure scope is 10～50mT.
9. shallow channel isolation area formation method according to claim 5, it is characterized in that: after carrying out described nitrogenize operation, have gradient nitrogen in the described sidewall oxide and distribute, the concentration of nitrogen by the interface of described sidewall oxide and described separator extremely the interface of described sidewall oxide and described shallow trench reduce gradually.
10. a shallow channel isolation area comprises the separator that is formed at the intrabasement shallow trench of semiconductor, covers the sidewall oxide of described shallow trench and covers described sidewall oxide and fill described shallow trench; It is characterized in that: have nitrogen in the described sidewall oxide and distribute.
11. shallow channel isolation area according to claim 10, it is characterized in that: have gradient nitrogen in the described sidewall oxide and distribute, the concentration of nitrogen by the interface of described sidewall oxide and described separator extremely the interface of described sidewall oxide and described shallow trench reduce gradually.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100944963A CN101459110A (en) | 2007-12-13 | 2007-12-13 | Shallow groove isolation region and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100944963A CN101459110A (en) | 2007-12-13 | 2007-12-13 | Shallow groove isolation region and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101459110A true CN101459110A (en) | 2009-06-17 |
Family
ID=40769873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100944963A Pending CN101459110A (en) | 2007-12-13 | 2007-12-13 | Shallow groove isolation region and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101459110A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706090A (en) * | 2017-09-22 | 2018-02-16 | 德淮半导体有限公司 | Fleet plough groove isolation structure, semiconductor structure and preparation method thereof |
| CN108336014A (en) * | 2018-04-12 | 2018-07-27 | 德淮半导体有限公司 | The method that groove isolation construction is formed in semiconductor material layer |
-
2007
- 2007-12-13 CN CNA2007100944963A patent/CN101459110A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107706090A (en) * | 2017-09-22 | 2018-02-16 | 德淮半导体有限公司 | Fleet plough groove isolation structure, semiconductor structure and preparation method thereof |
| CN108336014A (en) * | 2018-04-12 | 2018-07-27 | 德淮半导体有限公司 | The method that groove isolation construction is formed in semiconductor material layer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101459066B (en) | Gate, shallow slot isolation region forming method and flattening method for silicon base etching surface | |
| JP4984558B2 (en) | Manufacturing method of semiconductor device | |
| CN106471615B (en) | ONO stacks forming method | |
| CN101606236B (en) | Integration of non-volatile charge trap memory devices and logic cmos devices | |
| ATE387928T1 (en) | CATHETER TIP | |
| CN103871968B (en) | The manufacture method of MOS transistor | |
| CN102024761A (en) | Method for forming semiconductor integrated circuit device | |
| CN104350603A (en) | Integration of non-volatile charge trap memory devices and logic CMOS devices | |
| US7825004B2 (en) | Method of producing semiconductor device | |
| CN101459111A (en) | Shallow groove isolation region forming method and dielectric layer forming method | |
| CN101789377B (en) | Method for increasing stress led into channel and semiconductor device | |
| CN101364538B (en) | Gate layer forming method | |
| CN101459110A (en) | Shallow groove isolation region and forming method thereof | |
| JP2007048941A (en) | Semiconductor device manufacturing method | |
| JP5119604B2 (en) | Manufacturing method of semiconductor device | |
| CN103531476B (en) | Semiconductor device manufacturing method | |
| CN101197282A (en) | Semiconductor device and its making method | |
| CN103531454B (en) | Semiconductor device manufacturing method | |
| CN101359615B (en) | Semiconductor isolation structure and manufacturing method of semiconductor device | |
| CN108281356A (en) | Photoresist minimizing technology | |
| CN101577223B (en) | Grid, semiconductor apparatus and methods for forming grid, doped area and nitrogen-containing side wall substrate | |
| CN101459113B (en) | Shallow groove isolation region forming method | |
| CN105826267B (en) | Semiconductor element and manufacturing method thereof | |
| CN106298779A (en) | A kind of semiconductor device and manufacture method, electronic installation | |
| JP2006210463A (en) | Semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090617 |