CN101452836A - Method for reducing substrate current in semiconductor device - Google Patents
Method for reducing substrate current in semiconductor device Download PDFInfo
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- CN101452836A CN101452836A CNA2007100943778A CN200710094377A CN101452836A CN 101452836 A CN101452836 A CN 101452836A CN A2007100943778 A CNA2007100943778 A CN A2007100943778A CN 200710094377 A CN200710094377 A CN 200710094377A CN 101452836 A CN101452836 A CN 101452836A
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- semiconductor device
- epitaxial loayer
- silicon
- substrate current
- substrate
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Abstract
The invention discloses a method for reducing substrate current in a semiconductor device. The method comprises: growing two layers of epitaxial layers on a silicon substrate, wherein the first epitaxial layer is made of wide bandgap semiconductor material, the second epitaxial layer is made of monocrystal silicon, and the selected wide bandgap semiconductor material and crystal lattices of silicon have better matching property; and then forming a PN node of the device on the first epitaxial layer, so as to reduce leakage current of the PN node in the semiconductor device, further reduce substrate current, and improve reliability of the semiconductor device.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, relate in particular to a kind of method that reduces substrate current in the semiconductor device.
Background technology
Along with reducing of device size, short-channel effect is obvious all the more, and substrate current increases.Big substrate current will cause the integrity problem of a series of devices: puncture as device Snapback, effect (Latch up effect) and the reduction of device lifetime etc. are locked in fastening of cmos circuit.
Because substrate current mainly comes from the leakage current of PN junction, and the leakage current of PN junction is main relevant with the energy gap of semi-conducting material.As shown in Figure 1, in the prior art, various semiconductor device generally all are formed directly on the silicon substrate, but because the energy gap of silicon is 1.119ev, belong to low-gap semiconductor, so the PN junction leakage current of silicon is bigger, thereby makes that the substrate current of semiconductor device is also bigger.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that reduces substrate current in the semiconductor device, can reduce substrate current, thereby improves the reliability of semiconductor device.
For solving the problems of the technologies described above, the invention provides a kind of method that reduces substrate current in the semiconductor device, comprising:
At first, growth first epitaxial loayer on silicon substrate, and described first epitaxial loayer is selected semiconductor material with wide forbidden band for use;
Then, growth second epitaxial loayer on described first epitaxial loayer, and described second epitaxial loayer is a monocrystalline silicon.
The present invention is owing to adopted technique scheme, has following beneficial effect, promptly by the two-layer epitaxial loayer of growth on silicon substrate, wherein first epitaxial loayer is a semiconductor material with wide forbidden band, second epitaxial loayer is a monocrystalline silicon, and selected semiconductor material with wide forbidden band and silicon have preferably and mate between lattice, be formed on described first epitaxial loayer by PN junction then device, thereby played the effect that reduces the leakage current of PN junction in the semiconductor device, and then reduced substrate current, improved the reliability of semiconductor device.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the sectional structure chart by the semiconductor device of prior art manufacturing;
Fig. 2 is the flow chart of an embodiment of the method for the invention;
The sectional structure chart of Fig. 3 a-3b in the method for the invention process, forming;
Fig. 4 is the sectional structure chart according to the semiconductor device of the method for the invention manufacturing.
Embodiment
As shown in Figure 2, in one embodiment, the present invention includes following steps:
Because semiconductor material with wide forbidden band has the little characteristic of PN junction electric leakage, therefore in the present invention, at first, growth first epitaxial loayer on silicon substrate.Described first epitaxial loayer should be selected semiconductor material with wide forbidden band (as being ZnS, SiC, InP etc.) for use, and should guarantee that selected semiconductor material with wide forbidden band and silicon have preferably mates between lattice, should guarantee that promptly the lattice mismatch between selected semiconductor material with wide forbidden band and silicon is as far as possible little, with the lattice defect of above-mentioned two kinds of storerooms of reducing to cause, and then play the effect that improves device performance because of lattice mismatch.At this moment the cross-section structure of device is shown in Fig. 3 a.Like this, in the successive process that semiconductor device is made, just the PN junction of this device can be formed in this first epitaxial loayer, reduce the PN junction leakage current, and then play the effect that reduces substrate current thereby play.
Then, second epitaxial loayer of on described first epitaxial loayer, growing again, preferably, described second epitaxial loayer is a monocrystalline silicon, structure at this moment is shown in Fig. 3 b.
The thickness of described first epitaxial loayer and second epitaxial loayer depends on the physical size of the semiconductor device that will realize and the silicon loss (Silicon loss) in the described device fabrication process.
Subsequently, just can based on above-mentioned the growth structure of first epitaxial loayer and second epitaxial loayer be arranged, continue successive process according to the particular type of the semiconductor device that will realize at silicon substrate.For example, the semiconductor device of structure is made on the basis according to the formed said structure of the method for the invention as shown in Figure 3, by this figure as can be seen the PN junction in this device be formed on first epitaxial loayer that described material is a semiconductor material with wide forbidden band, thereby played the effect that reduces substrate current.
Claims (3)
1, a kind of method that reduces substrate current in the semiconductor device is characterized in that, comprising:
At first, growth first epitaxial loayer on silicon substrate, and described first epitaxial loayer is selected semiconductor material with wide forbidden band for use;
Then, growth second epitaxial loayer on described first epitaxial loayer, and described second epitaxial loayer is a monocrystalline silicon.
2, according to the method for substrate current in the described minimizing semiconductor device of claim 1, it is characterized in that, described semiconductor material with wide forbidden band should and silicon between lattice mismatch as far as possible little.
3, according to the method for substrate current in claim 1 or the 2 described minimizing semiconductor device, it is characterized in that the thickness of described first epitaxial loayer and second epitaxial loayer depends on the physical size of the semiconductor device that will realize and the silicon loss in the described device fabrication process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100943778A CN101452836A (en) | 2007-12-06 | 2007-12-06 | Method for reducing substrate current in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100943778A CN101452836A (en) | 2007-12-06 | 2007-12-06 | Method for reducing substrate current in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101452836A true CN101452836A (en) | 2009-06-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100943778A Pending CN101452836A (en) | 2007-12-06 | 2007-12-06 | Method for reducing substrate current in semiconductor device |
Country Status (1)
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| CN (1) | CN101452836A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214562A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103367252A (en) * | 2013-07-08 | 2013-10-23 | 河北普兴电子科技股份有限公司 | Manufacturing method for two-layer silicon epitaxial wafer used for bipolar transistor |
-
2007
- 2007-12-06 CN CNA2007100943778A patent/CN101452836A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214562A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| WO2011124002A1 (en) * | 2010-04-09 | 2011-10-13 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| GB2484420A (en) * | 2010-04-09 | 2012-04-11 | Inst Of Microelectronics Cas | Semiconductor structure and manufacturing method thereof |
| CN103367252A (en) * | 2013-07-08 | 2013-10-23 | 河北普兴电子科技股份有限公司 | Manufacturing method for two-layer silicon epitaxial wafer used for bipolar transistor |
| CN103367252B (en) * | 2013-07-08 | 2015-02-04 | 河北普兴电子科技股份有限公司 | Manufacturing method for two-layer silicon epitaxial wafer used for bipolar transistor |
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Open date: 20090610 |