CN101452210B - Photolithography method for forming different pattern density - Google Patents

Photolithography method for forming different pattern density Download PDF

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Publication number
CN101452210B
CN101452210B CN2007100943161A CN200710094316A CN101452210B CN 101452210 B CN101452210 B CN 101452210B CN 2007100943161 A CN2007100943161 A CN 2007100943161A CN 200710094316 A CN200710094316 A CN 200710094316A CN 101452210 B CN101452210 B CN 101452210B
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lithography mask
pattern density
mask version
different
photoetching
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CN101452210A (en
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陈华伦
陈雄斌
陈瑜
熊涛
罗啸
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

The invention discloses a photolithographic method which is capable of forming different pattern densities and is used for an etching macro load effect test. The photolithographic method uses at least two photolithographic masking plates with different pattern densities, wherein at least one photolithographic masking plate is provided with test patterns. The photolithographic masking plates with different pattern densities are used for carrying out the photolithography at the preset positions in different units in array on a silicon slice, thereby making the array form a photolithographic pattern with even images, and finally the integral photolithographic pattern density is obtained. At least two photolithographic masking plates with different pattern densities are used for carrying out the combined photolithography on basic units, thereby forming the integral photolithographic pattern with different pattern densities, effectively reducing the number of the photolithographic masking plates in the process of the study on the etching macro load, and reducing the study cost.

Description

Form the photoetching method of different pattern density
Technical field
The present invention relates to a kind of optical semiconductor lithography, particularly a kind of photoetching technique that is used for the grand load effect test of etching.
Background technology
Plasma etch rate is called load effect (loadingeffect) to the relation between the etching area.This effect can be explained theoretically, and can be used as the foundation that the etch mode of set time and endpoint detecting is selected in our consideration for use.Especially the penetrance characteristic of lithography mask version has determined the size of exposure area, therefore directly causes the load effect of whole grand load (macroloading) and local micro-loading (microloading).
In order to finely tune the etching process parameter, to reach the optimised process performance, the estimation of chip exposure area is a key subject; That is to say that the estimation of the correlation properties of lithography mask version penetrance is necessary.The etching step of polysilicon layer promptly is a representative example, and for the penetrance (being decided by the assembly pattern) of different lithography mask versions, same process parameter is set, and but may cause the mistake of polysilicon layer to lose or owes erosion.Because load effect square is directly proportional to the silicon chip radius, therefore when preparation is transferred to bigger die size, also need consider the etching load effect.In fact, suppose under identical pattern density and minimum dimension technology that then required film etching amount will have linear increase with the amplification of silicon area.Physics in the etch reactor or chemical process conditions also will have different greatly simultaneously.These all are first-order effects, that is etching has grand load effect.For the research of grand load effect process window in the etching technics, the data of etching speed in the time of need obtaining difference with the lithography mask version of different pattern density.In the prior art, for obtaining the litho pattern of different pattern density, often need to make the polylith lithography mask version, preparation cost is higher.Simultaneously, discontinuous because of the pattern density of lithography mask version, have only the value (see figure 1) of several point of discontinuity, be unfavorable for carrying out of research work.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of photoetching method that forms different pattern density, and it can reduce the cost of used lithography mask version.
For solving the problems of the technologies described above, the photoetching method of formation different pattern density of the present invention, be used for the grand load effect test of etching, this photoetching method uses two lithography mask versions with different pattern density at least, wherein has resolution chart at least one lithography mask version, utilize the mask blank of above-mentioned different pattern density by the preposition photoetching in the different units of certain the one-tenth array on silicon chip, make this array form the uniform litho pattern of image, finally obtain whole litho pattern density.
Method of the present invention, lithography mask version by several tool different pattern densities makes up photoetching on elementary cell, formation has the different whole litho pattern of pattern density, and effective quantity that has reduced lithography mask version in the grand loading process of research etching reduces research cost.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 be in the prior art etching rate and litho pattern density concern synoptic diagram;
Fig. 2 a to Fig. 2 c is a concrete synoptic diagram of implementing of the present invention;
Fig. 3 a to Fig. 3 c is another concrete synoptic diagram of implementing of the present invention;
Fig. 4 be in the photoetching method of the present invention etching rate and litho pattern density concern synoptic diagram.
Embodiment
The photoetching method of formation different pattern density of the present invention, it mainly utilizes the lithography mask version of at least two above tool different pattern densities, in the different units of a basic array, adopt the various combination of lithography mask version and different units position, realize the purpose of the variation of whole pattern density.
Implement method of the present invention, prepare to have the different lithography mask version more than two of different pattern density at first at least, wherein at least one lithography mask version resolution chart is arranged.And along with the minimizing of lithography mask version number, pattern density difference will strengthen between the lithography mask version.When doing photoetching, pattern density is as required edited the planar alignment figure of each piece mask blank in advance, between the mask blank with different pattern density, and lithography mask version with skip between do different collocation.Afterwards according to the planar alignment figure that edits in advance, and do multiexposure, multiple exposure (exposure frequency is identical with the quantity of the actual lithography mask version that uses) and appropriately make up the employed lithography mask version of different view fields on the silicon chip, make this array form the uniform litho pattern of image, finally form different whole pattern densities.Can realize the exposure of each unit during concrete operations by photolithography stepper, the unit that the need of same lithography mask version can be exposed is finished by the stepper selected cell.
For example, adopt two lithography mask versions, the pattern density of lithography mask version A is 5%, and the pattern density of lithography mask version B is 50%.First kind is combined as lithography mask version A and lithography mask version B alternately photoetching (seeing Fig. 2 a and Fig. 2 b) in array, forms the litho pattern shown in Fig. 2 c, obtains whole litho pattern density and is: (5%+50%)/and 2=27.5%.Be combined as in second and use lithography mask version A photoetching shown in Fig. 3 a, with lithography mask version B photoetching, obtain litho pattern whole shown in Fig. 3 c shown in Fig. 3 b, this integral body litho pattern density is: 5%*0.25+50%*0.75=38.75%.Can also be with lithography mask version A photoetching 1/4 unit wherein, and with lithography mask version B photoetching 3/4 unit wherein, form whole litho pattern density and be: 50%*0.25+5%*0.75=16.25%.In the manner described above, multiple being combined to form can be arranged, obtain a plurality of different litho pattern density, finally can form etch rate data as Fig. 4.

Claims (3)

1. photoetching method that forms different pattern density, be used for the grand load effect test of etching, it is characterized in that: this photoetching method uses two lithography mask versions with different pattern density at least, wherein has resolution chart at least one lithography mask version, the mask blank that utilizes above-mentioned different pattern density in the different units of certain array on silicon chip is by the preposition photoetching, make this array form the uniform litho pattern of image, finally obtain whole litho pattern density.
2. according to the described photoetching method of claim 1, it is characterized in that: the lithography mask version that uses two different pattern densities, wherein has resolution chart at least one lithography mask version, in the different units of certain array on silicon chip, with the alternately photoetching mutually of described two lithography mask versions, obtain whole pattern density and be above-mentioned two lithography mask version pattern densities and half litho pattern density.
3. according to the described photoetching method of claim 1, it is characterized in that: the lithography mask version that uses two different pattern densities, wherein has resolution chart at least one lithography mask version, in the array element of a 2X2 on silicon chip, therein on three unit with described wherein lithography mask version photoetching, and on remaining unit with another piece lithography mask version photoetching, obtain whole litho pattern density.
CN2007100943161A 2007-11-28 2007-11-28 Photolithography method for forming different pattern density Active CN101452210B (en)

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CN101452210B true CN101452210B (en) 2010-09-08

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103293847A (en) * 2013-05-29 2013-09-11 北京京东方光电科技有限公司 Mask plate and preparation method of mask plate
CN105810564A (en) * 2014-12-30 2016-07-27 展讯通信(上海)有限公司 Combined mask for preparing MOS tube
CN109541884B (en) * 2018-12-29 2022-06-14 上海华力微电子有限公司 Test photomask of spliced product and combination method thereof
CN116500871B (en) * 2023-06-26 2023-09-26 合肥晶合集成电路股份有限公司 Photoetching method and system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599665B1 (en) * 2000-10-10 2003-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a semiconductor wafer imaging mask having uniform pattern features
CN1542913A (en) * 2003-04-28 2004-11-03 旺宏电子股份有限公司 Crystallite picture making process
CN101025569A (en) * 2006-02-23 2007-08-29 海力士半导体有限公司 Method for forming fine pattern of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6599665B1 (en) * 2000-10-10 2003-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a semiconductor wafer imaging mask having uniform pattern features
CN1542913A (en) * 2003-04-28 2004-11-03 旺宏电子股份有限公司 Crystallite picture making process
CN101025569A (en) * 2006-02-23 2007-08-29 海力士半导体有限公司 Method for forming fine pattern of semiconductor device

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