CN101447804A - Method for calibrating phase of zero intermediate frequency communicator and device thereof - Google Patents
Method for calibrating phase of zero intermediate frequency communicator and device thereof Download PDFInfo
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- CN101447804A CN101447804A CNA2007101937929A CN200710193792A CN101447804A CN 101447804 A CN101447804 A CN 101447804A CN A2007101937929 A CNA2007101937929 A CN A2007101937929A CN 200710193792 A CN200710193792 A CN 200710193792A CN 101447804 A CN101447804 A CN 101447804A
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Abstract
The invention discloses a method for calibrating phase of a zero intermediate frequency communicator and a device thereof. The method comprises the following steps: before an IQ digital signal enters a digital-analog conversion (DAC) unit, the IQ digital signal is subject to delay adjustment by a digital processing system, thereby completing phase adjustment of the IQ signal. By adopting the invention, before the IQ digital signal enters the DAC in a transmitting channel and when the IQ digital signal is digital, the delay adjustment is carried out on the IQ digital signal, so that the difference of phases between an analog I signal and an analog Q signal arriving at an IQ modulator is 90 degrees, thereby achieving the aim of optimizing EVM, effectively inhibiting sidebands, achieving the aim of improving radio frequency signal EVM, ORINGIN OFFSET and other radio frequency indexes and achieving convenience.
Description
Technical field
The present invention relates to wireless communication field, relate in particular to a kind of method and device of zero intermediate frequency sender phase alignment.
Background technology
Zero intermediate frequency (directly up-conversion) is exactly that baseband signal directly is modulated to a kind of modulation system on the radio-frequency carrier.This modulation system, do not need intermediate frequency amplification, filtering and frequency conversion part, and relaxed performance requirement to the radio frequency part filter, even need not add SAW (Surface Acoustic Wave) filter, thereby volume (practice shows that the PCB of zero intermediate frequency sender (printed circuit board (PCB)) layout has only the sixth of common sender), weight, power consumption and the cost of sender have greatly been reduced.But also there are a lot of shortcomings in this technology, as to the unusual sensitivity etc. of the phase place of orthogonal demodulation signal and orthogonal local oscillation signal and amplitude imbalance and direct current offset distortion, and therefore can cause serious sideband and local-oscillator leakage, cause EVM indexs such as (error vector magnitude) to worsen.Zero intermediate frequency is a new technology, and current shortcoming for zero intermediate frequency sideband and local-oscillator leakage in this technology of solution all is to realize by direct current biasing, gain, the phase place of adjusting the IQ signal generally.Carry out direct current biasing and gain for the IQ signal and adjust and generally to realize, the IQ signal is carried out the phase place adjustment, current not well solution than being easier to.
In sum, the technical scheme of a kind of zero intermediate frequency sender of current needs phase alignment.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method and device of zero intermediate frequency sender phase alignment, adopt digital processing unit to the adjustment of delaying time of digital IQ signal, reach the purpose of adjusting phase place, can effectively restrain sideband, improve the EVM index of radiofrequency signal.
In order to address the above problem, the invention provides a kind of method of zero intermediate frequency sender phase alignment,
Comprise, before the IQ digital signal enters the digital-to-analogue conversion unit, to the adjustment of delaying time of IQ digital signal, finish adjustment the IQ signal phase by digital processing system.
Further, said method also can comprise, described digital processing system comprises to be write control unit, dual port random access memory cell, read control unit.
Further, said method also can comprise, describedly write the IQ digital signal being write in the described dual port random access memory cell of control unit circulation, after reading a phase place adjustment parameter address of control unit after writing the current address of control unit, read the IQ digital signal that writes described dual port random access memory cell, and will become the IQ digital signal output of quadrature, finish the adjustment of IQ signal phase.
The present invention also provides a kind of device of zero intermediate frequency sender phase alignment,
Comprise digital processing system, be used for finishing adjustment the IQ signal phase to entering the adjustment of delaying time of IQ digital signal before the digital-to-analogue conversion unit.
Further, said apparatus also can comprise, described digital processing system comprises to be write control unit, dual port random access memory cell, read control unit.
Further, said apparatus also can comprise, the described control unit of writing, and what be used to circulate writes described dual port random access memory cell with described IQ digital signal;
The described control unit of reading, be used for after described phase place after writing the current address of control unit is adjusted a parameter address, read the IQ digital signal that writes described dual port random access memory cell, and will become the IQ digital signal output of quadrature, finish the adjustment of IQ signal phase.
Compared with prior art, use the present invention, numerical portion before transmission channel DAC, to the adjustment of delaying time of digital IQ signal, make Simulation with I and the Q signal that arrives the IQ modulator, phase phasic difference 90 degree, reach the purpose of optimizing EVM, effectively restrain sideband, reach the purpose that improves radiofrequency signal EVM and ORINGIN OFFSET radio-frequency (RF) index such as (origin offset), and realize conveniently.
Description of drawings
Fig. 1 is the structure chart of zero intermediate frequency sender;
Fig. 2 is the structure chart of the device of intermediate frequency sender phase alignment in the specific embodiment of the invention;
Fig. 3 is the structural representation of digital processing system in the specific embodiment of the invention;
Fig. 4 is the theory diagram that digital processing system is realized the IQ phase alignment in the instantiation of the present invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
As shown in Figure 1, the zero intermediate frequency sender is made of following several parts: 101 baseband modulator, 102 base band calibrators, 103 digital-to-analogue converter DAC, 104 local oscillator oscillators, 105IQ modulator.Wherein 101 baseband modulator are carried out baseband modulation to digital signal, produce I and Q digital signal, 102 base band calibrators to the I and the Q signal of numeral setover, the calibration of gain, phase place, 103 digital-to-analogue converter DAC transform carrying out digital-to-analogue through the IQ digital signal of calibration, produce the I and the Q signal of simulation, the clock that the 105IQ modulator adopts 104 local oscillator oscillators to provide is modulated the analog I signal of 103 digital-to-analogue converter DAC output, the output radiofrequency signal.
Main design of the present invention is to propose on the principle of analyzing the generation of zero intermediate frequency sender local-oscillator leakage and sideband, its key is the powerful advantages of performance digital processing system to sequential logic and signal processing, before the digital-to-analogue converter, by digital processing system to digital signal lag adjustment, reach adjustment to the analog I signal phase that enters the IQ modulator, make the analog I signal phase that enters the IQ modulator differ 90 degree, improve the purpose of sender radio-frequency (RF) index.
A kind of method of zero intermediate frequency sender phase alignment comprises in the specific embodiment of the invention,
Before the IQ digital signal enters the digital-to-analogue conversion unit, to the adjustment of delaying time of IQ digital signal, finish adjustment to the IQ signal phase by digital processing system.
Before the IQ digital signal enters the digital-to-analogue conversion unit, to the adjustment of delaying time of IQ digital signal, finish adjustment to the analog I signal phase that enters the IQ modulator by digital processing system.
Wherein digital processing system realizes that IQ phase alignment device mainly comprises following a few part: write control unit, dual port RAM (random access memory) unit, read control unit; Numeral I signal or digital Q signal become the IQ digital signal of quadrature through after writing control unit, dual port RAM unit, reading control unit.
Write the IQ digital signal being write in the described dual port RAM unit of control unit circulation, after reading DELAY the address of control unit after writing the current address of control unit, read the IQ digital signal that writes described dual port RAM unit, and will become the IQ digital signal output of quadrature, finish the adjustment of IQ signal phase.
As shown in Figure 2, a kind of device of zero intermediate frequency sender phase alignment comprises digital processing system in the specific embodiment of the invention, is used for finishing the adjustment to the IQ signal phase to entering the adjustment of delaying time of IQ digital signal before the digital-to-analogue conversion unit.
As shown in Figure 3, described digital processing system comprises and writes control unit, dual port RAM unit, reads control unit.
The described control unit of writing, what be used to circulate writes described twoport unit with described IQ digital signal;
The described control unit of reading is used for reading the IQ digital signal that writes described dual port RAM unit behind described DELAY address after writing the current address of control unit, and will becomes the IQ digital signal output of quadrature, finishes the adjustment of IQ signal phase.
The invention will be further described below in conjunction with instantiation.
Fig. 4 is the theory diagram that digital processing system is realized the IQ phase alignment, digital I signal or digital Q signal through 201 writing controllers, 202 dual port RAM memories, 203 Read Controllers after, become the IQ digital signal of quadrature.
To write from the digital IQ signal of 101 baseband modulator in the 202 dual port RAM memories of 201 writing controllers circulation, 203 Read Controllers behind DELAY address are reading out digital IQ signal behind the current address of 201 writing controllers, send into 103DAC digital-to-analogue converter, reach the purpose of adjusting phase place.
Because individual difference, it is different that the phase place of each veneer is adjusted parameter (DELAY).
In the practical application, during debugging single board, from small to large, the parameters such as change DELAY of order can make the parameters such as DELAY of the every index optimum of veneer output signal deposit among the ROM on the veneer then.During the sender real work, the DELAY parameter that digital processing system will deposit among the ROM is taken out, and is configured in the base band calibrator and goes, and reaches the purpose that improves radio-frequency (RF) index.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (6)
1, a kind of method of zero intermediate frequency sender phase alignment is characterized in that,
Comprise, before the IQ digital signal enters the digital-to-analogue conversion unit, to the adjustment of delaying time of IQ digital signal, finish adjustment the IQ signal phase by digital processing system.
2, the method for claim 1 is characterized in that,
Described digital processing system comprises to be write control unit, dual port random access memory cell, reads control unit.
3, method as claimed in claim 2 is characterized in that,
Describedly write the IQ digital signal being write in the described dual port random access memory cell of control unit circulation, after reading a phase place adjustment parameter address of control unit after writing the current address of control unit, read the IQ digital signal that writes described dual port random access memory cell, and will become the IQ digital signal output of quadrature, finish the adjustment of IQ signal phase.
4, a kind of device of zero intermediate frequency sender phase alignment is characterized in that,
Comprise digital processing system, be used for finishing adjustment the IQ signal phase to entering the adjustment of delaying time of IQ digital signal before the digital-to-analogue conversion unit.
5, device as claimed in claim 4 is characterized in that,
Described digital processing system comprises to be write control unit, dual port random access memory cell, reads control unit.
6, device as claimed in claim 5 is characterized in that,
The described control unit of writing, what be used to circulate writes described dual port random access memory cell with described IQ digital signal;
The described control unit of reading, be used for after described phase place after writing the current address of control unit is adjusted a parameter address, read the IQ digital signal that writes described dual port random access memory cell, and will become the IQ digital signal output of quadrature, finish the adjustment of IQ signal phase.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101937929A CN101447804B (en) | 2007-11-27 | 2007-11-27 | Method for calibrating phase of zero intermediate frequency communicator and device thereof |
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| CN2007101937929A CN101447804B (en) | 2007-11-27 | 2007-11-27 | Method for calibrating phase of zero intermediate frequency communicator and device thereof |
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| CN101447804A true CN101447804A (en) | 2009-06-03 |
| CN101447804B CN101447804B (en) | 2012-11-28 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105959067A (en) * | 2016-04-22 | 2016-09-21 | 北京联盛德微电子有限责任公司 | Calibration method and device for transmitter chip |
| CN112865844A (en) * | 2019-11-27 | 2021-05-28 | 大唐移动通信设备有限公司 | Channel calibration method and device thereof |
| CN114337699A (en) * | 2021-12-14 | 2022-04-12 | 中国电子科技集团公司第三十八研究所 | Self-adaptive carrier cancellation device and method of zero-intermediate-frequency transmitter |
| CN115296969A (en) * | 2022-07-28 | 2022-11-04 | 湖南迈克森伟电子科技有限公司 | Method and system for adjusting phase of transmission code element |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2793619B1 (en) * | 1999-05-10 | 2001-08-10 | Cit Alcatel | DEVICE AND METHOD FOR PRODUCING A FILTER SIGNAL HAVING A GIVEN FREQUENCY AND A HERTZIAN TRANSMITTER TRANSMITTING AT A FREQUENCY ESTABLISHED BY A FREQUENCY ADJUSTABLE OSCILLATOR |
| US7254379B2 (en) * | 2004-07-09 | 2007-08-07 | Silicon Storage Technology, Inc. | RF receiver mismatch calibration system and method |
| CN100589462C (en) * | 2005-12-20 | 2010-02-10 | 中兴通讯股份有限公司 | Multiple path multiple carrier digital pre-distortion sender of wideband CDMA base station system |
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2007
- 2007-11-27 CN CN2007101937929A patent/CN101447804B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105959067A (en) * | 2016-04-22 | 2016-09-21 | 北京联盛德微电子有限责任公司 | Calibration method and device for transmitter chip |
| CN112865844A (en) * | 2019-11-27 | 2021-05-28 | 大唐移动通信设备有限公司 | Channel calibration method and device thereof |
| CN114337699A (en) * | 2021-12-14 | 2022-04-12 | 中国电子科技集团公司第三十八研究所 | Self-adaptive carrier cancellation device and method of zero-intermediate-frequency transmitter |
| CN114337699B (en) * | 2021-12-14 | 2023-05-09 | 中国电子科技集团公司第三十八研究所 | Self-adaptive carrier cancellation device and method for zero intermediate frequency transmitter |
| CN115296969A (en) * | 2022-07-28 | 2022-11-04 | 湖南迈克森伟电子科技有限公司 | Method and system for adjusting phase of transmission code element |
| CN115296969B (en) * | 2022-07-28 | 2023-06-16 | 湖南迈克森伟电子科技有限公司 | Method and system for adjusting phase of transmitting code element |
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| CN101447804B (en) | 2012-11-28 |
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