CN115296969B

CN115296969B - Method and system for adjusting phase of transmitting code element

Info

Publication number: CN115296969B
Application number: CN202210900468.0A
Authority: CN
Inventors: 吕游; 赵海军; 龚高茂
Original assignee: Hunan Maxwell Electronic Technology Co Ltd
Current assignee: Hunan Maxwell Electronic Technology Co Ltd
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2023-06-16
Anticipated expiration: 2042-07-28
Also published as: CN115296969A

Abstract

The embodiment of the application discloses a method and a system for adjusting the phase of a transmitting symbol, which are used for adjusting the phase of the transmitting IQ symbol and realizing the alignment of the phase of the IQ symbol. The system comprises an FPGA and a phase acquisition module, wherein the FPGA comprises a phase-locked loop, a logic unit, a first serial transceiver, a second serial transceiver and a phase control module; after generating a digital baseband code element signal according to a target clock signal output by a phase-locked loop, the logic unit serially transmits an I path and a Q path of analog baseband code element signals under the action of the digital baseband code element signal and the target clock signal by the first serial transceiver and the second serial transceiver; the phase acquisition module acquires phase information between analog baseband code element signals of the I path and the Q path; when the phase of the IQ code element is deviated, the phase control module adjusts the phase of a target clock signal in the transceiver according to the phase information so as to adjust the phase between the I-path and Q-path analog baseband code element signals transmitted by the transceiver.

Description

Method and system for adjusting phase of transmitting code element

Technical Field

The application belongs to the technical field of communication, and particularly relates to a method and a system for adjusting the phase of a transmitting code element.

Background

Currently, conventional QPSK modulation systems typically include a field programmable gate array (Field Programmable Gate Array, FPGA) and a digital-to-analog converter (Digital to analog converter, DAC). The FPGA is used for generating a digital baseband code element signal, modulating the digital baseband code element signal and obtaining a modulated digital signal; the DAC is used for performing digital-to-analog conversion on the modulated digital signals output by the FPGA and outputting QPSK modulation analog signals.

In the existing QPSK modulation system, after digital end modulation, digital-to-analog conversion is carried out through a DAC. In the signal modulation process of the digital end, the same clock is used, the phases of the transmitted I path code element and the transmitted Q path code element are aligned, and the problem of phase misalignment is avoided.

Disclosure of Invention

Aiming at a QPSK modulation system comprising an FPGA and an IQ modulator, when a serial transceiver in the FPGA is used as a transmitting source of an analog baseband code element signal, the transmitted IQ code element has the problem of phase misalignment.

In a first aspect, an embodiment of the present application provides a transmit symbol phase adjustment system, including an FPGA, a phase acquisition module, and an IQ modulator, where the FPGA includes a phase locked loop, a logic unit, a first serial transceiver, a second serial transceiver, and a phase control module;

The phase-locked loop is respectively connected with the logic unit, the first serial transceiver and the second serial transceiver, and the logic unit is respectively connected with the first serial transceiver and the second serial transceiver; the first serial transceiver is respectively connected with the phase acquisition module and the IQ modulator, and the second serial transceiver is respectively connected with the phase acquisition module and the IQ modulator; the phase acquisition module is connected with the phase control module, and the phase control module is respectively connected with the first serial transceiver and the second serial transceiver;

the phase-locked loop is used for generating a target clock signal according to an external clock signal; the logic unit is used for generating a digital baseband code element signal according to the target clock signal;

the first serial transceiver is used for serially transmitting I paths of analog baseband symbol signals under the action of the digital baseband symbol signals and the target clock signals; the second serial transceiver is used for serially transmitting Q paths of analog baseband symbol signals under the action of the digital baseband symbol signals and the target clock signal;

the phase acquisition module is used for acquiring phase information between an input I-path analog baseband code element signal and an input Q-path analog baseband code element signal, wherein the phase information comprises information for representing whether the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation or not and deviation range information;

The phase control module is used for adjusting the phase of a target clock signal in the first serial transceiver and the second serial transceiver according to the phase information if the phase deviation between the I-path analog baseband code element signal and the Q-path analog baseband code element signal is determined according to the phase information, so as to adjust the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal;

the IQ modulator is used for carrying out IQ modulation on the input I-path analog baseband symbol signal and the Q-path analog baseband symbol signal after the phases of the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are aligned, so as to obtain QPSK modulated signals.

As can be seen from the above, in the embodiment of the present application, the IQ symbols transmitted by the serial transceiver are divided into two paths, one path of IQ symbol signals is input to the IQ modulator for IQ modulation, and the other path of IQ symbol signals is input to the phase acquisition module for acquiring phase information between the two paths of IQ symbol signals, and feedback control is performed according to the phase information, that is, whether the phase of the IQ symbol has a deviation and a deviation range is determined according to the phase information, and when the phase of the IQ symbol is deviated, the phase control module adjusts the phase of the transmitted IQ symbol according to the phase information, so as to implement phase alignment of the IQ symbol.

In a possible implementation manner of the first aspect, the phase acquisition module includes an exclusive or phase detector and a phase acquisition unit;

one input end of the exclusive-or phase discriminator is connected with the first serial transceiver, and the other input end of the exclusive-or phase discriminator is connected with the second serial transceiver; the output end of the exclusive or phase discriminator is connected with the input end of the phase acquisition unit, and the output end of the phase acquisition unit is connected with the phase control module;

the exclusive-or phase discriminator is used for carrying out exclusive-or operation on the input I-path analog baseband code element signals and the Q-path analog baseband code element signals to obtain exclusive-or signals;

the phase acquisition unit is used for carrying out phase acquisition on the signals after the exclusive or to obtain phase information.

In one possible implementation of the first aspect, the IQ modulator is a high-speed IQ modulator.

In a possible implementation manner of the first aspect, the IQ modulator is specifically configured to IQ modulate the I-path analog baseband symbol signal and the Q-path analog baseband symbol based on the local oscillator LO, to obtain a QPSK modulated signal. The local oscillator LO is connected to the IQ modulator.

In one possible implementation manner of the first aspect, the first serial transceiver and the second serial transceiver are GTX transceivers.

In a possible implementation manner of the first aspect, the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are pseudo-random binary sequence PRBS symbol signals.

In a second aspect, an embodiment of the present application provides a method for adjusting a phase of a transmitting symbol, which is applied to a transmitting symbol phase adjustment system, where the transmitting symbol phase adjustment system includes an FPGA, a phase acquisition module, and an IQ modulator, and the FPGA includes a phase-locked loop, a logic unit, a first serial transceiver, a second serial transceiver, and a phase control module;

the method comprises the following steps:

the phase-locked loop generates a target clock signal according to the external clock signal; the logic unit generates a digital baseband code element signal according to the target clock signal;

The first serial transceiver serially transmits I paths of analog baseband symbol signals under the action of the digital baseband symbol signals and the target clock signal; the second serial transceiver serially transmits Q paths of analog baseband symbol signals under the action of the digital baseband symbol signals and the target clock signal;

the phase acquisition module acquires phase information between an input I-path analog baseband code element signal and an input Q-path analog baseband code element signal, wherein the phase information comprises information for representing whether the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation or not and deviation range information;

if the phase control module determines that the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation according to the phase information, the phase control module adjusts the phase of the target clock signals in the first serial transceiver and the second serial transceiver according to the phase information so as to adjust the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal;

after the phases of the I-path analog baseband code element signals and the Q-path analog baseband code element signals are aligned, the IQ modulator carries out IQ modulation on the input I-path analog baseband code element signals and Q-path analog baseband code element signals to obtain QPSK modulation signals.

In a possible implementation manner of the second aspect, the phase acquisition module includes an exclusive or phase detector and a phase acquisition unit;

the phase acquisition unit obtains phase information according to the input I path analog baseband code element signal and Q path analog baseband code element signal, and the phase acquisition unit comprises:

the exclusive-or phase discriminator performs exclusive-or operation on the input I-path analog baseband code element signals and Q-path analog baseband code element signals to obtain exclusive-or signals;

the phase acquisition unit performs phase acquisition on the signals after the exclusive or to obtain phase information.

In a possible implementation manner of the second aspect, the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are pseudo-random binary sequence PRBS symbol signals.

In one possible implementation manner of the second aspect, the first serial transceiver and the second serial transceiver are GTX transceivers.

It will be appreciated that the benefits of the second aspect may be found in the related description of the first aspect, and are not described in detail herein.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic block diagram of a QPSK modulation system;

fig. 2 is a schematic block diagram of a QPSK modulation system according to an embodiment of the present application;

fig. 3 is another schematic block diagram of a QPSK modulation system provided in an embodiment of the present application;

FIG. 4 is a schematic block diagram of a transmit symbol phase adjustment system according to an embodiment of the present application;

FIG. 5 is another schematic block diagram of a transmit symbol phase adjustment system provided in an embodiment of the present application;

FIG. 6 is another schematic block diagram of a transmit symbol phase adjustment system provided in an embodiment of the present application;

fig. 7 is a schematic phase deviation diagram of a GTX dual-channel transmission symbol according to an embodiment of the present application;

fig. 8 is a schematic phase alignment diagram of a GTX dual-channel transmission symbol according to an embodiment of the present application;

Fig. 9 is a schematic block diagram of a method for adjusting the phase of a transmission symbol according to an embodiment of the present application

Fig. 10 is a schematic structural diagram of an FPGA according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The inventors have found during long-term research that existing QPSK modulation systems typically require digital to analog conversion using a DAC. In a high-speed or ultra-high-speed communication scenario, a high-speed DAC is generally used to meet the requirement of the communication code rate as much as possible. That is, to implement digital-to-analog conversion, a DAC is typically used.

And, it was also found that: compared with a low-speed communication scene, the conventional QPSK modulation system has higher communication code rate in a high-speed or ultra-high-speed communication scene. In the case of an increase in the communication code rate, the sampling rate of the DAC also needs to be increased by a multiple. Because the high-speed DAC consumes more power, increasing the sampling rate of the DAC increases the hardware power consumption of the system, which in turn results in an increase in the hardware power consumption of the modulation system. In addition, the adjustment of the communication code rate of the traditional QPSK modulation system is related to hardware, so that the improvement of the DAC sampling rate also causes the complexity of hardware design, the difficulty of hardware type selection and the greater difficulty of realization.

Illustratively, referring to a schematic block diagram of the QPSK modulation system shown in FIG. 1, the system includes an FPGA11 and a high-speed DAC12. The FPGA11 and the high-speed DAC12 communicate via a Low-voltage differential signaling (Low-Voltage Differential Signaling, LVDS) bus.

The FPGA11 is configured to generate a digital baseband symbol signal, i.e., generate a digital baseband symbol signal within the FPGA; after generating a digital baseband code element signal, multiplying the digital baseband code element signal with a direct digital frequency synthesis (Direct Digital Synthesis, DDS) signal generated in the FPGA to obtain a modulated digital signal; after the modulated digital signal is subjected to the shaping filtering process, the digital symbol signal is transmitted to the high-speed DAC12 through the parallel LVDS bus.

The high-speed DAC12 is configured to receive the digital symbol signal, and perform operations such as interpolation and filtering on the digital symbol signal, so as to convert the parallel digital symbol signal into a serial QPSK modulation analog signal, thereby completing the QPSK modulation.

In the QPSK modulation system shown in fig. 1, digital modulation is performed inside the FPGA, i.e., signal modulation is performed at the digital end. Further, since the FPGA outputs a digital signal, a high-speed DAC is required to perform digital-to-analog conversion to convert the digital signal into an analog signal.

In a high-speed or ultra-high-speed communication scenario, the sampling rate of the high-speed DAC12 is high, which in turn makes the hardware power consumption of the whole modulation system high. And when the communication code rate is higher, the model of hardware such as the high-speed DAC12 is selected, and the difficulty of system hardware design and the like is higher. In addition, in the high-speed or ultra-high-speed communication scenario, the difficulty of digital modulation in the FPGA11 is also great due to the higher communication code rate.

Aiming at the problems that the existing QPSK modulation system has high hardware power consumption and large implementation difficulty in a high-speed or ultra-high-speed communication scene, the embodiment of the application provides the QPSK modulation system which comprises an FPGA and an IQ modulator, and a high-speed serial transceiver in the FPGA is used as a transmitting source of analog code element signals, so that the modulation system does not need to comprise a DAC (digital-to-analog converter) and does not need to use the DAC to perform digital-to-analog conversion. In this way, under the high-speed or ultra-high-speed communication scene, although the communication code rate is higher, the high-speed DAC is not required to perform digital-to-analog conversion, so that the hardware power consumption of the system is lower; in addition, the adjustment of the communication code rate is completely carried out by the software-controlled high-speed serial transceiver for code rate switching, and is irrelevant to hardware, so that the method is simpler in hardware design and hardware model selection and easy to realize.

Illustratively, referring to a schematic block diagram of a QPSK modulation system provided in the embodiment of the present application shown in fig. 2, the system includes an FPGA21 and an IQ modulator 22, the FPGA21 includes a high-speed serial transceiver as a transmission source of analog baseband symbols, I analog baseband symbol signals are sent to the IQ modulator 22 through a first channel, and Q analog baseband symbol signals are sent to the IQ modulator 22 through a second channel.

Wherein the FPGA21 comprises logic resources for generating digital baseband symbol signals.

In some embodiments, the logic resource may generate the digital baseband symbol signal via a clock signal and a phase locked loop. Wherein the clock signal may be an external clock signal. In a high-speed or ultra-high-speed communication scenario, the frequency of the internal clock signal may not meet the requirement of the communication code rate, and then an externally input clock signal with a specific frequency may be used.

The phase locked loop is used to control the frequency and phase of an oscillation signal inside the loop using an external clock signal. In the embodiment of the application, the external clock signal is input to a phase-locked loop, and the phase-locked loop outputs a target clock signal with corresponding frequency and phase, and the target clock signal is used for generating a digital baseband symbol signal.

After the phase-locked loop outputs the frequency-doubled target clock signal according to the external input clock signal, the logic resource of the FPGA generates a digital baseband code element signal with corresponding frequency and phase according to the target clock signal.

The FPGA21 also includes a high-speed serial transceiver. A high-speed serial transceiver refers to a transceiver whose transmission bandwidth can meet the requirements of a high-speed or ultra-high-speed communication scenario. For example, a high-speed serial transceiver refers to a serial transceiver having a transmission rate above a preset threshold. The high speed serial transceiver is illustratively a GTX transceiver. Of course, the QPSK modulation system provided in the embodiments of the present application may also be applied to a low-speed communication scenario, where the high-speed serial transceiver may be adaptively replaced with a low-rate transceiver.

It should be noted that, where the IQ modulator bandwidth allows, the QPSK modulation system provided in the embodiments of the present application may also use a lower rate or higher rate serial transceiver, such as a series of higher speed serial transceivers, e.g., GTP, GTH, and GTY.

The high-speed serial transceiver is configured to transmit an analog baseband symbol signal based on an input digital baseband symbol signal and a target clock signal. At this time, the high-speed serial transceiver serves as a transmission source of the analog baseband symbol signal. In QPSK modulation, an I (in-phase) path and a Q (quadrature) path analog signals are required to be carrier modulated, so that the high-speed serial transceiver transmits an I path analog baseband symbol signal and a Q path analog baseband symbol signal, and transmits the I path analog baseband symbol signal and the Q path analog baseband symbol signal to the IQ modulator through two transmission channels, respectively.

In some embodiments, after the phase-locked loop generates the target clock signal, the logic resource in the FPGA generates the digital baseband symbol signal according to the target clock signal, and inputs both the target clock signal and the digital baseband symbol signal to the first high-speed serial transceiver and the second high-speed serial transceiver. The first high-speed serial transceiver serially transmits an I-path analog baseband code element signal under the action of the digital baseband code element signal and the target clock signal, and the second high-speed serial transceiver serially transmits a Q-path baseband code element signal under the action of the digital baseband code element signal and the target clock signal.

Illustratively, the high-speed serial transceiver may be a GTX (GT Transceiver) transceiver. The GTX transceiver can transmit serial data of 10Gbps, so that the communication code rate requirement in a high-speed or ultra-high-speed communication scene can be met. In an embodiment of the present application, the QPSK modulation system may include two GTX transceivers, which are a first GTX transceiver and a second GTX transceiver, respectively. The first GTX transceiver is used as a first channel, and the second GTX transceiver is used as a second channel. Based on the digital baseband symbol signal and the target clock signal, the first GTX transceiver is driven to generate an I-path analog baseband symbol signal, and the I-path analog baseband symbol signal is transmitted in series. Similarly, the second GTX transceiver is driven to generate Q analog baseband symbol signals based on the digital baseband symbol signals and the target clock signal, and the Q analog baseband symbol signals are transmitted in series.

It is worth noting that the digital baseband symbol signal is converted into the analog baseband symbol signal by the high-speed serial transceiver, and the characteristic that the high-speed serial transceiver can transmit high-speed serial data is utilized, so that high-speed digital-to-analog conversion is not needed by the high-speed DAC, the high-speed DAC can be removed by the modulation system, and the modulation system can be still applicable in high-speed or ultra-high-speed communication scenes.

The IQ modulator 22 is configured to receive the I-path and Q-path analog baseband symbol signals, and IQ modulate the I-path and Q-path signals to obtain QPSK modulated signals. That is, the embodiment of the present application performs signal modulation at the analog end.

In particular, the system further includes a Local Oscillator (LO) 23. The LO23 is connected to the IQ modulator 22 for generating a local oscillation signal, and the IQ modulator 22 performs IQ modulation according to the local oscillation signal.

In a specific application, the IQ modulator 22 may be a high-speed IQ modulator, where the high-speed IQ modulator has a modulation chip with an ultra-high speed, so as to meet the communication code rate requirement of a high-speed or ultra-high-speed communication scenario. A high-speed IQ modulator refers to a modulator with a modulation rate greater than a certain threshold. Of course, as described above, the QPSK modulation system provided in the embodiments of the present application may also be applied to a low-speed communication scenario, where the IQ modulator 22 may not be a high-speed IQ modulator.

Illustratively, referring to another schematic block diagram of the QPSK modulation system provided by the embodiment of the present application shown in fig. 3, the first high-speed serial transceiver and the second high-speed serial transceiver are illustratively GTX transceivers. The system includes an FPGA31, a high-speed IQ modulator 32, and an LO33.FPGA31 includes phase-locked loop 311, logic unit 312, first GTX transceiver 313, and second GTX transceiver 314. The phase-locked loop 311 is connected to the logic unit 312, the first GTX transceiver 313 and the second GTX transceiver 314, respectively; logic unit 312 is coupled to first GTX transceiver 313 and second GTX transceiver 314, respectively.

The phase-locked loop 311 is configured to output a target clock signal according to an external clock signal. Logic 312 is configured to generate a digital baseband symbol signal based on the target clock signal.

The first GTX transceiver 313 is configured to serially transmit an I-path analog baseband symbol signal under the action of a target clock signal and a digital baseband symbol signal; the second GTX transceiver 314 is configured to serially transmit the Q analog baseband symbol signals under the influence of the target clock signal and the digital baseband symbol signals.

In fig. 3, the serial transmission of gtx_i to high speed IQ modulator 32 and the serial transmission of gtx_q to the high speed IQ modulator is shown. Where gtx_i and gtx_q represent analog baseband symbol signals of transmission I and Q paths.

From the above, the modulation system of the embodiment of the application comprises the FPGA and the IQ modulator, and the system architecture is simple and easy to implement in hardware. In addition, the high-speed serial transceiver is utilized to serially send out analog baseband code element signals, and the characteristics of high-speed data transmission are utilized, so that the system removes a high-speed DAC, does not need to carry out high-speed digital-to-analog conversion by the high-speed DAC, reduces the power consumption of the system, and is easy to realize in hardware design and selection.

Further, when performing QPSK modulation using a modulation system including an FPGA and an IQ modulator, the inventors have also found that, at each power-up of a serial transceiver within the FPGA, the transmitted IQ analog baseband symbol signals cannot guarantee phase alignment, and that the symbols transmitted by the two channels have a phase deviation of one half to several symbols. However, in case of QPSK modulation, it is necessary to ensure the phase alignment of the transmitted IQ symbols.

In order to solve the problem that when a serial transceiver in an FPGA is electrified every time, the transmitted IQ analog baseband code element signals cannot guarantee phase alignment, the embodiment of the application also provides a transmitted code element phase alignment system, the system divides the IQ code element transmitted by the serial transceiver into two paths, one path of IQ code element signals are input to an IQ modulator for IQ modulation, the other path of IQ code element signals are input to a phase acquisition module for acquiring phase information between the two paths of IQ code element signals, feedback control is carried out according to the phase information, namely, whether the phase of the IQ code element has deviation and deviation range is judged according to the phase information, and when the phase of the IQ code element is deviated, the phase control module adjusts the transmitted IQ code element phase according to the phase information so as to realize the phase alignment of the IQ code element.

Illustratively, referring to fig. 4, an embodiment of the present application provides a schematic block diagram of a transmit symbol phase adjustment system, which includes an FPGA41, a phase acquisition module 42, and an IQ modulator 43, the FPGA41 including a phase locked loop 411, a first serial transceiver 412, a second serial transceiver 414, and a phase control module 413 logic unit 415.

Wherein the phase-locked loop 411 is respectively connected with the logic unit 415, the first serial transceiver 412 and the second serial transceiver 414; logic unit 415 is coupled to first serial transceiver 412 and second serial transceiver 414, respectively; the first serial transceiver 412 is connected to the phase acquisition module 42 and the IQ modulator 43, respectively, and the second serial transceiver 414 is connected to the phase acquisition module 42 and the IQ modulator 43, respectively; the phase acquisition module 42 is connected to a phase control module 413, and the phase control module 413 is connected to a first serial transceiver 412 and a second serial transceiver 414, respectively.

The phase-locked loop 411 is used for generating a target clock signal according to an external clock signal; logic unit 415 is configured to generate a digital baseband symbol signal based on the target clock signal. The first serial transceiver 412 is configured to serially transmit the I-path analog baseband symbol signal under the action of the digital baseband symbol signal and the target clock signal; the second serial transceiver 414 is configured to serially transmit the Q-path analog baseband symbol signal under the influence of the digital baseband symbol signal and the target clock signal.

That is, the external reference clock signal is input to the phase-locked loop 411, and the phase-locked loop 411 outputs a multiplied target clock signal, and the target clock signal is input to the logic unit 415 in one path, is input to the first serial transceiver 412 in one path, and is input to the second serial transceiver 414 in one path. After the logic unit 415 acquires the target clock signal, the generated digital baseband symbol signals are output to the first serial transceiver 412 and the second serial transceiver 414.

In other words, the first serial transceiver 412 and the second serial transceiver 414 serially transmit the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal, respectively, under the driving of the target clock signal and the digital baseband symbol signal.

The first serial transceiver 412 and the second serial transceiver 414 may be high-speed serial transceivers or low-rate serial transceivers, which are not limited herein. For example, when applied to a high speed or ultra-high speed communication scenario, the first serial transceiver 412 and the second serial transceiver 414 may be high speed serial transceivers to meet the communication code rate requirements of the high speed or ultra-high speed communication scenario, such as a GTX transceiver, and may also be a series of higher rate serial transceivers such as GTP, GTH, and GTY. At this time, the first serial transceiver 412 and the second serial transceiver 414 are respectively used as a first channel and a second channel for transmitting IQ analog baseband symbol signals; when applied to a low speed communication scenario, the first serial transceiver 412 and the second serial transceiver 414 may be low rate serial transceivers.

In particular applications, to facilitate phase monitoring, the symbols transmitted by the two lanes of the first serial transceiver 412 and the second serial transceiver 414 are the same. For example, before phase alignment, the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are both pseudo-random binary sequence (Pseudo Random Binary Sequence, PRBS) symbol signals, and the PRBS symbols can ensure that the transmitted symbols are irregular, which is more beneficial for phase monitoring. After the FPGA is powered up, the phases of the IQ symbols are typically misaligned. At this time, the first serial transceiver 412 and the second serial transceiver 414 may be enabled to transmit PRBS symbol signal data in two channels, so as to facilitate phase monitoring and thus facilitate IQ symbol phase adjustment.

After the IQ symbols are phase aligned, the first serial transceiver 412 and the second serial transceiver 414 may be enabled to transmit the traffic data to be transmitted, where the phases of the traffic data to be transmitted are aligned.

The phase acquisition module 42 is configured to obtain phase information according to the input I-path analog baseband symbol signal and Q-path analog baseband symbol signal, that is, acquire phase information between the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal. The phase information includes information for characterizing whether there is a deviation in phase between the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal, and deviation range information.

That is, the phase acquisition module 42 is configured to perform phase monitoring on the IQ symbol signals transmitted by the first serial transceiver 412 and the second serial transceiver 414 to determine whether there is a deviation in the phase of the IQ symbol, and when there is a deviation in the phase, the deviation range is specific.

The phase control module 413 is configured to, if it is determined that the phase between the I analog baseband symbol signal and the Q analog baseband symbol signal deviates according to the phase information, adjust the phases of the target clock signals in the first serial transceiver 412 and the second serial transceiver 414 according to the phase information, so as to adjust the phases between the I analog baseband symbol signal and the Q analog baseband symbol signal transmitted by the two transceivers.

In a specific application, the phase control module 413 may determine whether the phase of the symbol signals of the IQ two paths has a deviation according to the phase information, and if the phase of the symbol signals has a deviation, the phase control module enters a phase calibration procedure. In the phase calibration procedure, the phase control module 413 obtains a phase deviation range according to the phase information, and adjusts a clock signal in the transceiver according to the phase deviation range to adjust a phase between analog symbol signals of two paths of IQ transmitted by the transceiver.

Illustratively, when it is determined that the IQ symbols are not aligned, the phase control module 413 generates a control signal according to the phase deviation information in the phase information and outputs the control signal to the first serial transceiver 412 and the second serial transceiver 414. The first serial transceiver 412 and the second serial transceiver 414 adjust the phase of the target clock signal to the right or left according to the control signal, and output the phase-adjusted I-path analog baseband symbol signal and Q-path analog baseband symbol signal, respectively. Wherein the control signal is used to instruct the first serial transceiver 412 and the second serial transceiver 414 to adjust the phase of the target clock signal to the right or to the left, and the amount of phase adjustment.

After adjusting the IQ symbol phase, the first serial transceiver 412 and the second serial transceiver 414 output the phase-adjusted I-path analog baseband symbol signal and Q-path analog baseband symbol signal, respectively. At this time, the phase acquisition module is used for carrying out phase monitoring, and if the IQ code element phases are not aligned, the IQ code element phases transmitted by the serial transceiver are continuously adjusted according to the phase deviation range. I.e., phase adjustment, phase monitoring, phase adjustment, and so on, until phase alignment of IQ symbols is monitored. In a specific application, the phase control module 413 may control the phase between the I-path and Q-path symbols transmitted by the first serial transceiver 412 and the second serial transceiver 414 by controlling the phase of the target clock signal, so as to implement phase calibration for the IQ two-path symbols. After correcting the symbol phases of the two paths of IQ through the phase calibration flow, a target clock signal at the moment can be obtained, and the target clock signal can be used for subsequently controlling the two serial transceivers to emit service data with aligned phases.

If the phase of the symbol signals of the two paths of IQ has no phase deviation, the phase control module 413 may skip the phase calibration procedure and enter the service data transmission stage. At this time, based on the target clock signal obtained by the phase calibration process, digital baseband symbol signals of corresponding frequencies and corresponding phases are generated, and according to the generated digital baseband symbol signals and the target clock signal obtained by the phase calibration process, the two serial transceivers are driven to serially transmit the service data of the I-path and the Q-path with aligned phases, respectively, and the service data of the I-path and the Q-path with aligned phases is input to the IQ modulator.

It can be understood that, since the IQ symbols transmitted by the serial transceiver are split into two paths, one path is input to the phase acquisition module 42 for phase monitoring and phase adjustment, and the other path is input to the IQ modulator for IQ modulation to obtain a QPSK modulated signal. Therefore, through phase monitoring and phase adjustment, when the phases of the symbol signals of the two paths of IQ are aligned, the target clock signal during phase alignment can be used to control the two serial transceivers to transmit the service data with the aligned phases, and the two paths of service data with the aligned phases are subjected to IQ modulation, so that the transmitted QPSK modulation signal is obtained.

The IQ modulator 43 is configured to perform IQ modulation on the input I analog baseband symbol signal and Q analog baseband symbol signal after the phases of the I analog baseband symbol signal and Q analog baseband symbol signal are aligned, and obtain a QPSK modulated signal. At this time, the input I-path analog baseband symbol signal and Q-path analog baseband symbol signal may refer to the phase-aligned transmitted service data.

The IQ modulator 43 may be a high-speed IQ modulator or a low-speed IQ modulator. For example, when applied to high-speed or ultra-high-speed communication scenarios, then it is a high-speed IQ modulator.

In a specific application, the IQ modulator 43 may perform IQ modulation on the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal based on the local oscillator signal generated by the local oscillator LO, to obtain a QPSK modulated signal.

It will be appreciated that the two channels of the first serial transceiver 412 and the second serial transceiver 414 are controlled based on the target clock signal at the time of phase alignment to transmit the phase aligned I-way analog traffic data and Q-way analog traffic data, which are input to the IQ modulator 43.

When the phases of the I-and Q-paths of analog baseband symbol signals are not aligned, the IQ modulator 43 may not IQ modulate the input I-and Q-paths of analog baseband symbol signals, but may IQ modulate the input I-and Q-paths of analog service data after the phases are aligned.

Of course, the IQ modulator 43 may perform IQ modulation on the input IQ symbol at all times, regardless of whether the phases are aligned or not. At this time, when the phases are aligned, the service data of the IQ two paths is input. From the above, in the embodiment of the present application, the IQ symbol signal is input to the phase acquisition module, so as to acquire phase information between two paths of IQ symbol signals, and feedback control is performed according to the phase information, so as to adjust the phase of the transmitted IQ symbol, so as to implement IQ symbol phase alignment.

Based on the above embodiments, in some embodiments, referring to another schematic block diagram of the transmit symbol phase adjustment system provided in the embodiment of the present application shown in fig. 5, the phase acquisition module 42 includes an exclusive-or phase detector 421 and a phase acquisition unit 422.

An exclusive-or phase detector 421 has one input connected to the first serial transceiver 412 and the other input connected to the second transceiver 414; the output end of the exclusive or phase detector 421 is connected with the input end of the phase acquisition unit 422, and the output end of the phase acquisition unit 422 is connected with the phase control module 413;

the xor phase discriminator 421 is configured to perform an xor operation on the input I-path analog baseband symbol signal and the Q-path analog baseband symbol signal to obtain an xor-processed signal; the phase acquisition unit 422 is configured to perform phase acquisition on the signals after the exclusive or to obtain phase information.

It should be noted that, after the xor phase discriminator 421 performs the xor operation on the IQ symbol, a truth table of the xor may be obtained, where the truth table includes the xor result. When the exclusive-or result is 1, it indicates that there is a phase deviation between IQ symbols. Further, the range of IQ symbol phase deviation is obtained from the pulse width of occurrence 1 and the occurrence probability. When the exclusive-or result is 0, it indicates that there is no phase deviation between IQ symbols. The exclusive-or phase discriminator and the phase acquisition unit can convert the signals after the exclusive-or into phase information which can be identified by the FPGA, so that the FPGA can determine whether phase deviation exists in the IQ code element according to the phase information, and enter a phase calibration flow when the phase deviation exists.

Illustratively, referring to another schematic block diagram of the transmit symbol phase adjustment system provided by the embodiment of the present application shown in fig. 6, the first serial transceiver and the second serial transceiver are embodied as GTX transceivers. The system may include an FPGA61, an exclusive-or phase detector 62, a phase acquisition unit 63, a high-speed IQ modulator 64, and an LO65. Wherein FPGA61 includes a phase-locked loop 611, a first GTX transceiver 612, a second GTX transceiver 614, a logic unit 615, and a phase control module 613. Where gtx_1 and gtx_2 represent the first GTX transceiver and the second GTX transceiver, respectively, and gtx_i and gtx_q represent analog baseband symbol signals of transmission I and Q paths.

As shown in fig. 6, an external reference clock is input to the phase-locked loop 611, and the logic unit 615 generates a digital baseband symbol signal according to a target clock signal output from the phase-locked loop, and outputs the digital baseband symbol signal to the first GTX transceiver 612 and the second GTX transceiver 614.

First GTX transceiver 612 and second GTX transceiver 614 transmit gtx_i and gtx_q, respectively, under the combined action of the target clock signal and the digital baseband symbol signal. Gtx_i and gtx_q represent I and Q analog baseband symbol signals.

Gtx_i and gtx_q are input to the high speed IQ modulator 64 on one hand and to the xor phase detector 62 on the other hand. The exclusive-or phase discriminator 62 performs an exclusive-or operation on the input IQ symbol to obtain an exclusive-or signal, and outputs the exclusive-or signal to the phase acquisition unit 63. The phase acquisition unit 63 performs phase acquisition on the exclusive-or signal to obtain phase information, and outputs the phase information to the phase control module 613. When the phase control module 613 determines that the IQ symbol has a phase deviation according to the phase information, the phase control module controls the phase of the target clock signal, and further controls the phase of the IQ symbol signal sent by the GTX transceiver, so as to implement phase adjustment, and further implement phase alignment of the IQ symbol.

For example, referring to the schematic phase deviation of the GTX dual-channel transmission symbol shown in fig. 7 and the schematic phase alignment of the GTX dual-channel transmission symbol shown in fig. 8, fig. 7 shows that after the GTX transceiver is powered on, the phase of the transmitted IQ symbol has a deviation, and after the IQ symbol shown in fig. 7 is subjected to phase alignment by the transmission symbol adjustment scheme provided by the embodiment of the present application, the IQ symbol shown in fig. 8 can be obtained, and the phase of the IQ symbol signal of fig. 8 is completely aligned, so that the phase deviation is eliminated.

After describing the transmission symbol phase adjustment system provided in the embodiments of the present application, a method applied to the transmission symbol phase adjustment system is described below. For the description of the system, please refer to the above, and the description is omitted here.

Referring to fig. 9, which is a schematic block diagram illustrating a flow chart of a method for adjusting a phase of a transmission symbol according to an embodiment of the present application, the method may include the following steps:

step S901, a phase-locked loop generates a target clock signal according to an external clock signal; the logic unit generates a digital baseband symbol signal based on the target clock signal.

Step S902, the first serial transceiver serially transmits I paths of analog baseband code element signals under the action of the digital baseband code element signals and the target clock signals; the second serial transceiver serially transmits the Q analog baseband symbol signals under the influence of the digital baseband symbol signals and the target clock signal.

Step S903, a phase acquisition module acquires phase information between an input I-path analog baseband code element signal and a Q-path analog baseband code element signal, wherein the phase information comprises information for representing whether the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation or not and deviation range information;

Step S904, if the phase control module determines that the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation according to the phase information, the phase of the target clock signals in the first serial transceiver and the second serial transceiver is adjusted according to the phase information so as to adjust the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal;

step S905, after the phases of the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are aligned, the IQ modulator performs IQ modulation on the input I-path analog baseband symbol signal and Q-path analog baseband symbol signal, so as to obtain a QPSK modulated signal.

In one possible implementation, the phase acquisition module includes an exclusive or phase detector and a phase acquisition unit;

one input end of the exclusive-or phase discriminator is connected with the first serial transceiver, and the other input end of the exclusive-or phase discriminator is connected with the second serial transceiver; the output end of the exclusive-or phase discriminator is connected with the input end of the phase acquisition unit, and the output end of the phase acquisition unit is connected with the phase control module.

At this time, the xor phase discriminator can perform xor operation on the input I-path analog baseband symbol signal and the Q-path analog baseband symbol signal to obtain an xor-processed signal; and the phase acquisition unit performs phase acquisition on the exclusive-or signals to obtain phase information.

In one possible implementation, the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are both pseudo-random binary sequence PRBS symbol signals.

In one possible implementation, the first serial transceiver and the second serial transceiver are GTX transceivers.

It should be noted that, for the explanation of the method embodiment, reference may be made to the above system embodiment, which is not described herein.

It should be understood that the sequence number of each step in the foregoing embodiment does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Fig. 10 is a schematic structural diagram of an FPGA according to an embodiment of the present application. As shown in fig. 10, the FPGA10 of this embodiment includes: at least one logic processing unit 100 (only one is shown in fig. 10), a memory 101, and a transceiver 103, the memory 101 having stored therein a computer program 102 executable on the at least one logic processing unit 100, the logic processing unit 100 implementing the steps in any of the various method embodiments described above when executing the computer program 102. In some embodiments, the logic processing unit 100 may include the logic units and phase control modules mentioned above. The transceiver 103 is a serial transceiver, and may specifically include a first serial transceiver and a second serial transceiver. A phase locked loop may also be included.

The FPGA may include, but is not limited to, a logic processing unit 100, a memory 101. It will be appreciated by those skilled in the art that fig. 10 is merely an example of FPGA10 and is not intended to be limiting of FPGA10, and may include more or fewer components than shown, or may combine some components, or may include different components, such as input-output devices, network access devices, etc.

In this embodiment, the logic processing unit 100 may generate the digital baseband symbol signal based on the target clock signal generated by the phase-locked loop according to the external reference clock signal; driving the transceiver 103 to transmit an I-path analog baseband symbol signal and a Q-path analog baseband symbol signal according to the digital baseband symbol signal and the target clock signal; and acquiring phase information input by the phase acquisition module, determining whether phase deviation exists in the transmitted IQ code element according to the phase information, and adjusting the phase of the transmitted IQ code element according to the phase deviation range when the phase deviation exists so as to realize the phase alignment of the IQ code element.

The memory 101 may in some embodiments be an internal storage unit of the FPGA10, such as a hard disk or a memory of the FPGA 10. The memory 101 may also be an external storage device of the FPGA10 in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the FPGA 10. In an embodiment, the memory 101 may also include both internal memory units and external memory devices of the FPGA 10. The memory 101 is used for storing an operating system, application programs, boot loader (BootLoader), data, other programs, etc., such as program codes of the computer program. The memory 101 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

The embodiment of the application also provides an FPGA, which comprises: at least one logical processing unit, a memory and a computer program stored in the memory and executable on the at least one logical processing unit, the logical processing unit implementing the steps of any of the various method embodiments described above when the computer program is executed.

Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a logic processing unit, implements steps that may implement the various method embodiments described above.

Embodiments of the present application provide a computer program product that when run on an FPGA, causes the FPGA to perform steps that enable the implementation of the method embodiments described above.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, where the computer program may implement the steps of each of the method embodiments described above when executed by a logic processing unit. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing device/terminal apparatus, recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus, FPGA, and method may be implemented in other manners. For example, the above-described apparatus/FPGA embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims

1. The system is characterized by comprising an FPGA, a phase acquisition module and an IQ modulator, wherein the FPGA comprises a phase-locked loop, a logic unit, a first serial transceiver, a second serial transceiver and a phase control module;

the first serial transceiver is used for serially transmitting an I-path analog baseband symbol signal under the action of the digital baseband symbol signal and the target clock signal; the second serial transceiver is used for serially transmitting Q paths of analog baseband symbol signals under the action of the digital baseband symbol signals and the target clock signal;

the phase acquisition module is used for acquiring phase information between the input I-path analog baseband code element signal and the Q-path analog baseband code element signal, wherein the phase information comprises information for representing whether the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation or not and deviation range information;

The phase control module is configured to adjust phases of the target clock signals in the first serial transceiver and the second serial transceiver according to the phase information if it is determined that the phases between the I analog baseband symbol signal and the Q analog baseband symbol signal deviate according to the phase information, so as to adjust phases between the I analog baseband symbol signal and the Q analog baseband symbol signal;

the IQ modulator is used for carrying out IQ modulation on the input I-path analog baseband symbol signal and the Q-path analog baseband symbol signal after the phases of the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are aligned, so as to obtain QPSK modulation signals.

2. The system of claim 1, wherein the phase acquisition module comprises an exclusive or phase detector and a phase acquisition unit;

one input end of the exclusive-or phase detector is connected with the first serial transceiver, and the other input end of the exclusive-or phase detector is connected with the second serial transceiver; the output end of the exclusive-or phase discriminator is connected with the input end of the phase acquisition unit, and the output end of the phase acquisition unit is connected with the phase control module;

the phase acquisition unit is used for carrying out phase acquisition on the signals after the exclusive or to obtain the phase information.

3. The system of claim 1 wherein said IQ modulator is a high speed IQ modulator.

4. The system of claim 1, wherein the IQ modulator is configured to IQ modulate the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal based on a local oscillator LO, the local oscillator LO being coupled to the IQ modulator, to obtain a QPSK modulated signal.

5. The system of claim 1, wherein the first serial transceiver and the second serial transceiver are each GTX transceivers.

6. The system of any of claims 1 to 5, wherein the I-way analog baseband symbol signal and the I-way analog baseband symbol signal are both pseudo-random binary sequence PRBS symbol signals.

7. The method for adjusting the phase of the transmitting code element is characterized by being applied to a transmitting code element phase adjustment system, wherein the transmitting code element phase adjustment system comprises an FPGA (field programmable gate array), a phase acquisition module and an IQ (in-phase) modulator, and the FPGA comprises a phase-locked loop, a logic unit, a first serial transceiver, a second serial transceiver and a phase control module;

the method comprises the following steps:

after the phase-locked loop generates a target clock signal according to an external clock signal, the logic unit generates a digital baseband code element signal according to the target clock signal;

the first serial transceiver serially transmits an I-path analog baseband symbol signal under the action of the digital baseband symbol signal and the target clock signal, and the second serial transceiver serially transmits a Q-path analog baseband symbol signal under the action of the digital baseband symbol signal and the target clock signal;

the phase acquisition module acquires phase information between the input I-path analog baseband code element signal and the Q-path analog baseband code element signal, wherein the phase information comprises information for representing whether the phase between the I-path analog baseband code element signal and the Q-path analog baseband code element signal has deviation or not and deviation range information;

The phase control module adjusts the phase of the target clock signal in the first serial transceiver and the second serial transceiver according to the phase information if the phase between the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal is determined to have deviation according to the phase information, so as to adjust the phase between the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal;

and the IQ modulator performs IQ modulation on the input I-path analog baseband symbol signal and the Q-path analog baseband symbol signal after the phases of the I-path analog baseband symbol signal and the Q-path analog baseband symbol signal are aligned, so as to obtain a QPSK modulation signal.

8. The method of claim 7, wherein the phase acquisition module comprises an exclusive or phase detector and a phase acquisition unit;

The phase acquisition module obtains phase information according to the input I path analog baseband code element signal and the Q path analog baseband code element signal, and the phase acquisition module comprises:

the exclusive-or phase discriminator performs exclusive-or operation on the input I-path analog baseband code element signal and the Q-path analog baseband code element signal to obtain an exclusive-or signal;

and the phase acquisition unit acquires the phase of the exclusive-or signal to obtain the phase information.

9. The method of claim 7 or 8, wherein the I-way analog baseband symbol signal and the I-way analog baseband symbol signal are both pseudo-random binary sequence PRBS symbol signals.

10. The method of claim 7, wherein the first serial transceiver and the second serial transceiver are each GTX transceivers.