CN101447524A - Punch through effect enhanced type silicon photo transistor - Google Patents
Punch through effect enhanced type silicon photo transistor Download PDFInfo
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- CN101447524A CN101447524A CNA2008100516804A CN200810051680A CN101447524A CN 101447524 A CN101447524 A CN 101447524A CN A2008100516804 A CNA2008100516804 A CN A2008100516804A CN 200810051680 A CN200810051680 A CN 200810051680A CN 101447524 A CN101447524 A CN 101447524A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 66
- 239000010703 silicon Substances 0.000 title claims abstract description 66
- 230000000694 effects Effects 0.000 title claims abstract description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 101
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 50
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 20
- VJJVVKGSBWRFNP-UHFFFAOYSA-N [O].[Si](=O)=O Chemical compound [O].[Si](=O)=O VJJVVKGSBWRFNP-UHFFFAOYSA-N 0.000 claims description 31
- HJELPJZFDFLHEY-UHFFFAOYSA-N silicide(1-) Chemical compound [Si-] HJELPJZFDFLHEY-UHFFFAOYSA-N 0.000 claims 4
- 238000006243 chemical reaction Methods 0.000 abstract description 18
- 238000000034 method Methods 0.000 description 23
- 150000002500 ions Chemical class 0.000 description 14
- 230000008569 process Effects 0.000 description 13
- 230000005693 optoelectronics Effects 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 230000003287 optical effect Effects 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 229940090044 injection Drugs 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000012010 growth Effects 0.000 description 4
- 238000005286 illumination Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000005622 photoelectricity Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- CKQBSDUWDZEMJL-UHFFFAOYSA-N [W].[Br] Chemical compound [W].[Br] CKQBSDUWDZEMJL-UHFFFAOYSA-N 0.000 description 1
- 238000012271 agricultural production Methods 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
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- 238000000280 densification Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
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- 238000005259 measurement Methods 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- 239000000725 suspension Substances 0.000 description 1
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Abstract
The invention relates to a punch through effect enhanced type silicon photo transistor which comprises two types which are a NPN type and a PNP type; the silicon photo transistor sequentially comprises a silicon substrate layer, a P pit (or a N pit) layer positioned on the silicon substrate layer, two discrete N type (or P type) heavy doping active areas positioned inside the P pit (or a N pit) layer, a field silicon dioxide layer surrounded by the two N type (or P type) heavy doping active areas, two discrete bar-shaped gate oxide silicon dioxide layers which are arranged at the narrow side of the P pit (or a N pit) layer and on the upper surface of the field silicon dioxide layer, two discrete polysilicon layers that are coated on the gate oxide silicon dioxide layers and have the same shapes as that of the gate oxide silicon dioxide layers, and a bar-shaped metallic electrode layer that is positioned on the upper surface at the wide side of the P pit (or a N pit) layer and is respectively connected with the two discrete N type (or P type) heavy doping active areas from bottom to top. The device can effectively improve photoelectric conversion gain of devices, limit the dark current of devices, and reduce the noise of devices, so as to obtain higher signal-to-noise.
Description
Technical field
The invention belongs to the semiconductor photoelectric device field, be specifically related to a kind of punch through effect enhanced type silicon photo transistor.
Background technology
Semiconductor photo detector is widely used with its good performance, small size and cheap price, has infiltrated through social various aspects such as industrial and agricultural production, military science and technology, daily civilian, consumer electronics.Silicon photodetector is the big class of one in the semiconductor photo detector.At present, using more widely, silicon photodetector mainly comprises PIN photodiode, APD avalanche photodide and normal optical electric transistor etc.These photodetectors exist that size is big, higher to the manufactured materials performance requirement, operating voltage is higher, manufacturing process and CMOS technology are incompatible, and are difficult for and shortcoming such as peripheral circuit is integrated.
The main noise source of PIN photodiode is the thermal noise of outer meeting resistance and the shot noise of photoelectric current, but owing to there is not internal gain, its signal to noise ratio (snr) is not high, especially under the less situation of outer meeting resistance.Though the APD avalanche photodide has internal gain, introduced additional noise simultaneously, limited the detectivity of APD, and APD also needs very high operating voltage.The common photoelectric transistor has two kinds, and a kind of is the two ends phototransistor of base suspension, and another kind is the phototransistor of three ends.The two ends phototransistor is compound owing to existing in the space charge region at base-emitter PN junction place, and when incident optical power was very low, it was very low to gain; In addition, low incident optical power also causes the charging interval of emitter junction electric capacity very long, so gain bandwidth product and SNR become very little, has limited the application of this phototransistor aspect high speed like this.
Though three end phototransistors are being obtained some successes aspect raising gain and the response speed, but because the shot noise that base bias current is introduced is also amplified by transistor simultaneously, therefore, when base current during much larger than photogenerated current, it is very low that SNR can become, and this has seriously limited the detectivity of three end phototransistors under low light condition.
For response speed and the SNR that improves phototransistor simultaneously, 1993, people such as Y.Wang and E.S.Yang proposed a kind of break-through base phototransistor, not only can obtain high-gain, response fast, and can obtain low noise.Break-through base phototransistor has had the characteristics of low noise characteristics of PIN photodiode and APD photodiode high-gain simultaneously.Owing to do not have the base bias electric current, so its noise characteristic is better than the common photoelectric transistor.Therefore, phototransistor tool on weak light detection in break-through base has great advantage.But this break-through base phototransistor is made up of the AlGaAs/GaAs/GaAs structure, it is the same with other compound semiconductor device individual significant drawbacks---be difficult to mutually integrated with silicon integrated circuit, especially the CMOS integrated circuit technology of extensive use, the production cost height.
Calendar year 2001, people such as Hailin Luo realize silica-based break-through base phototransistor.When incident optical power was 1.9nW, the opto-electronic conversion gain was 15384, and the response device time is 1.6ns, and-three dB bandwidth is 300MHz, and SNR is approximately 40dB.Device is a lateral transistor structure, and the base exhausts fully during work, produces punchthrough effect, thereby obtains high opto-electronic conversion gain.Silicon break-through base phototransistor not only has performances such as high-gain and fast-response speed, is difficult to integrated shortcoming but also overcome compound break-through base phototransistor.But no matter be break-through compound substrate or silicon substrate base phototransistor, their dark current is all bigger, and can not be fully compatible with normal business CMOS technology.
Summary of the invention
The punch through effect enhanced type silicon photo transistor that the purpose of this invention is to provide a kind of high opto-electronic conversion gain, low-dark current and complete and normal business CMOS process compatible.
Punch through effect enhanced type silicon photo transistor structure of the present invention is divided into two types of NPN and PNP according to transistor types as shown in Figure 1.
NPN type punch through effect enhanced type silicon photo transistor, it is characterized in that: comprise layer-of-substrate silicon from the bottom to top successively, be positioned at the P trap layer on the layer-of-substrate silicon, be positioned at two discrete N type heavy doping active areas of P trap layer, be positioned at P trap layer, by two N type heavy doping active areas around the place silicon dioxide layer, be positioned at two discrete strip grate oxygen silicon dioxide layers of narrow side of P trap layer and place silicon dioxide layer upper surface, cover on the grid oxygen silicon dioxide layer, two the discrete polysilicon layers identical with grid oxygen silicon dioxide layer shape, the bullion electrode layer that is positioned at the wide side upper surface of P trap layer and links to each other respectively with two discrete N type heavy doping active areas.
Further, the U-shaped zone of two symmetries that above-mentioned NPN type punch through effect enhanced type silicon photo transistor, two discrete N type heavy doping active areas are divided into by grid oxygen silicon dioxide layer and polysilicon layer.
Above-mentioned NPN type punch through effect enhanced type silicon photo transistor, P trap layer, two discrete N type heavy doping active areas and the upper surface of place silicon dioxide layer are positioned at same plane.
Above-mentioned NPN type punch through effect enhanced type silicon photo transistor, the degree of depth of two discrete N type heavy doping active areas is less than the degree of depth of place silicon dioxide layer, and the degree of depth of place silicon dioxide layer is less than the degree of depth of P trap layer.
In above-mentioned NPN type device, layer-of-substrate silicon is as the basis that forms P trap layer, and P trap layer is as the base of device; The N type heavy doping active area (ion implanted region) of P trap layer inside is divided into two discrete active areas by place silicon dioxide layer and polysilicon layer, constitute the collector region and the emitter region of phototransistor respectively, be attached thereto the bullion electrode layer that connects, constitute collector region electrode and emitter region electrode respectively.
Such punch through effect enhanced type silicon photo transistor can be regarded as by the phototransistor of two kinds of different structure sizes is continuous and form, their base length difference:, constitute the base of long growing base area phototransistor of base length at P well area between emitter region and the collector region, below the silicon dioxide of place at the device zone line; At device two end regions, constitute the base of short short base phototransistor of base length at the P well area between emitter region and the collector region, below polysilicon layer and the grid oxygen silicon dioxide layer.
NPN type punch through effect enhanced type silicon photo transistor, its canonical parameter is: the length of P trap layer and wide 12～15 μ m and 5～7 μ m of being respectively, the degree of depth is 3～5 μ m.The place silicon dioxide layer is positioned at the central authorities of well region, and upper surface is equal with well region, long and wide 8～12 μ m and 2～4 μ m of being respectively, thick 0.4～0.8 μ m.Two parts grid oxygen silicon dioxide layer lays respectively at the narrow side of well region, aligns with the narrow limit of well region, and extends to the place silicon dioxide layer, long and wide 3～5 μ m and 1～2 μ m of being respectively, and thickness is 10～20nm.Two parts polysilicon layer is positioned on the grid oxygen silicon dioxide layer, and with the length of grid oxygen silicon dioxide layer and wide identical, thickness is 200～300nm.The heavy doping of N type is had chance with and distinguished is that the degree of depth is 0.15～0.25 μ m along two of the device major axis symmetry discrete semi-circular zones of U word, the interior long length of side 8～10 μ m, long 1～2 μ m of inner short-side, foreign minister's length of side 10～12 μ m, long 3～5 μ m of outer minor face.
The positive-negative-positive punch through effect enhanced type silicon photo transistor, it is characterized in that: comprise layer-of-substrate silicon from the bottom to top successively, be positioned at the N trap layer on the layer-of-substrate silicon, be positioned at two discrete P type heavy doping active areas of N trap layer, be positioned at N trap layer, by two P type heavy doping active areas around the place silicon dioxide layer, be positioned at two discrete strip grate oxygen silicon dioxide layers of narrow side of N trap layer and place silicon dioxide layer upper surface, cover on the grid oxygen silicon dioxide layer, two the discrete polysilicon layers identical with grid oxygen silicon dioxide layer shape, the bullion electrode layer that is positioned at the wide side upper surface of N trap layer and links to each other respectively with two discrete P type heavy doping active areas.
Further, the U-shaped zone of two symmetries that above-mentioned positive-negative-positive punch through effect enhanced type silicon photo transistor, two discrete P type heavy doping active areas are divided into by grid oxygen silicon dioxide layer and polysilicon layer.
Above-mentioned positive-negative-positive punch through effect enhanced type silicon photo transistor, N trap layer, two discrete P type heavy doping active areas and the upper surface of place silicon dioxide layer are positioned at same plane.
Above-mentioned positive-negative-positive punch through effect enhanced type silicon photo transistor, the degree of depth of two discrete P type heavy doping active areas is less than the degree of depth of place silicon dioxide layer, and the degree of depth of place silicon dioxide layer is less than the degree of depth of N trap layer.
In above-mentioned positive-negative-positive device, layer-of-substrate silicon is as the basis that forms the N trap, and N trap layer is as the base of device; The P type heavy doping active area (ion implanted region) of N trap inside is divided into two discrete active areas by place silicon dioxide layer and polysilicon layer, constitute the collector region and the emitter region of phototransistor respectively, be attached thereto the bullion electrode layer that connects, constitute collector region electrode and emitter region electrode respectively.
Such punch through effect enhanced type silicon photo transistor can be regarded as by the phototransistor of two kinds of different structure sizes is continuous and form, their base length difference:, constitute the base of long growing base area phototransistor of base length at N well area between emitter region and the collector region, below the silicon dioxide of place at the device zone line; At device two end regions, the N well area that is positioned at polysilicon layer and grid oxygen silicon dioxide layer below constitutes the base of short short base phototransistor of base length.
The positive-negative-positive punch through effect enhanced type silicon photo transistor, its canonical parameter is: long and wide 12～15 μ m and 5～7 μ m of being respectively of N well region, the degree of depth is 3～5 μ m.The place silicon dioxide layer is positioned at well region central authorities, and upper surface is equal with well region, long and wide 8～12 μ m and 2～4 μ m of being respectively, thick 0.4～0.8 μ m.Two parts grid oxygen silicon dioxide layer lays respectively at the narrow side of well region, aligns with the narrow limit of well region, and extends to the place silicon dioxide layer, long and wide 3～5 μ m and 1～2 μ m of being respectively, and thickness is 10～20nm.Two parts polysilicon layer is positioned on the grid oxygen silicon dioxide layer, and with the length of grid oxygen silicon dioxide layer and wide identical, thickness is 200～300nm.The heavy doping of P type is had chance with and distinguished is that the degree of depth is 0.15～0.25 μ m along two of the device major axis symmetry discrete semi-circular zones of U word, the interior long length of side 8～10 μ m, long 1～2 μ m of inner short-side, foreign minister's length of side 10～12 μ m, long 3～5 μ m of outer minor face.
Growing base area phototransistor in the punch through effect enhanced type silicon photo transistor, the place silicon dioxide (SiO of top, base
2) be printing opacity, so growing base area phototransistor base is as the light area.The top, base of short base phototransistor is a polysilicon, is lighttight.During phototransistor work, ambient light is injected by growing base area, the emitter region of device links to each other with ground with voltage source respectively with collector region, growing base area phototransistor and short base phototransistor are operated under the identical bias, if this bias voltage surpasses the punch through voltage of short base phototransistor, growing base area phototransistor operate as normal, the base of short base phototransistor exhausts fully, and promptly short base phototransistor reaches pass-through state.Because have only the base printing opacity of growing base area phototransistor, photo-generated carrier only partly produces at growing base area during illumination.The photoproduction minority carrier that produces is swept to collector electrode under the forward bias effect, the majority carrier of photoproduction simultaneously is accumulated in growing base area.Along with the photoproduction majority carrier constantly accumulates at growing base area, make the majority carrier concentration of growing base area part will be higher than short base part, therefore, the majority carrier concentration gradient can make a large amount of photoproduction majority carriers of growing base area be diffused into short base, thereby the potential barrier of short base is reduced, the electric current that makes emitter flow to collector electrode increases, thereby has amplified photogenerated current indirectly.
The common break-through base phototransistor of realizing with people such as Y.Wang and Hailin Luo compares, punch through effect enhanced type phototransistor of the present invention has utilized the base of growing base area phototransistor to accumulate the photoproduction majority carrier, reduce the potential barrier of the phototransistor base, short base that is in pass-through state, the photogenerated current that obtains amplifying has improved the photoelectricity conversion gain; Short simultaneously base is formed by the polysilicon autoregistration, and is simple in structure; Because the narrower in width of short base phototransistor, only account for the sub-fraction of total device structure, thus the effective dark current of limiting device, the reduction device noise obtains high signal to noise ratio.
Punch through effect enhanced type silicon photo transistor of the present invention has the following advantages:
1, adopted standard CMOS process.Both utilized the polysilicon self-aligned technology of standard CMOS process to define short base, the well region that has also utilized place silicon dioxide to cover simultaneously forms growing base area, has so just formed the compound transistor that contains two kinds of phototransistors;
2, improved the opto-electronic conversion gain.Punch through effect enhanced type silicon photo transistor contains growing base area phototransistor and break-through base, short base transistor, the base of growing base area phototransistor accumulates photo-generated carrier, be used for reducing the potential barrier of transistorized break-through base, short base, thereby can obtain bigger photogenerated current, can obtain very high opto-electronic conversion gain;
3, reduce dark current.The shortcoming of break-through base phototransistor is that dark current is bigger, and the narrower in width of break-through base, the inner short base of punch through effect enhanced type silicon photo transistor phototransistor, therefore and growing base area phototransistor width is very wide, limiting device dark current effectively;
4, technology is simple, is easy to integrated.The punch through effect enhanced type silicon photo transistor that the present invention proposes fully and normal business CMOS process compatible has not only reduced process complexity and cost, and can make things convenient for and carry out integrated with other CMOS peripheral circuits.
The curve (I-V curve) that punch through effect enhanced type silicon photo transistor of the present invention uses the Keithley4200-SCS semiconductor parametric tester to come the output current of measuring element to change with forward bias, the light source that the photoelectric characteristic test is used is the bromine tungsten filament lamp of model as LHT75, and the white light of light source output obtains the monochromatic light of 650nm wavelength by monochromator.The I-V test result as shown in Figure 3, under the 2.0V forward bias, the dark current of device has only 1 μ A as can be seen.The opto-electronic conversion gain as shown in Figure 4.The gain of definition opto-electronic conversion is the photo-generated carrier number of device generation and the ratio of incident photon number, promptly
(wherein, G represents opto-electronic conversion gain, I
PhotoAnd I
DarkRepresentative has light and the output current of device when unglazed respectively, and q is an electron charge, P
InBe incident optical power, h is a planck constant, and v is a lambda1-wavelength), when optical power density is 1 * 10
-6W/cm
2650nm monochromatic light when shining device surface, measurement result can get the opto-electronic conversion gain as calculated 10
6Magnitude.
The preparation method of punch through effect enhanced type silicon photo transistor of the present invention adopts normal business CMOS technology, and preparation process is as follows:
A: the selection of substrate---choose the silicon substrate that resistivity is 15～25 Ω cm, thickness is about 100～200 μ m;
B: the formation of well region---inject and carry out high temperature by energetic ion and advance, on silicon substrate, form P trap or N trap.For the NPN device, inject As, energy approximately is 100keV, dosage approximately is 5 * 10
12Cm
-2, 1000～1200 ℃ advance 30～60 minutes down then; For the PNP device, inject B, energy approximately is 120keV, dosage approximately is 2 * 10
12Cm
-2, 1000～1200 ℃ advance 20～50 minutes down then;
C: carry out selective oxidation---utilize the method silicon oxide surface of the wet-oxygen oxidation method of vapour atmosphere and high temperature on the silicon beyond desire forms the heavy doping active area, obtaining thickness is the place silicon dioxide layer of 400～600nm, and utilizes chemico-mechanical polishing to polish the surface of P trap or N trap and place silicon dioxide;
D: preparation polysilicon layer---middle position at oxygen layer two ends, the field of device surface, utilize the strip grid oxygen silicon dioxide layer of the hot oxygen oxidizing process growth of dried oxygen and high temperature, on grid oxygen silicon dioxide layer, utilize the grow polysilicon of same size, thickness 200～400nm of the method for chemical gaseous phase extension then than thickness 10～20nm;
E: the formation of heavy doping active area---utilize the polysilicon layer that forms among the place silicon dioxide layer that forms among the step C and the step D to do and cover, carry out energetic ion and inject.For NPN type device, inject N type impurity, as As; For the positive-negative-positive device, inject p type impurity, as B;
The metal A l electrode layer of F: metal electrode layer---method growth 0.5～1.0 μ m by thermal evaporation or sputter also is connected with N type or P type heavy doping active area, formation collector region electrode and emitter region electrode, and then finished preparation of devices.
Elaborate content of the present invention below in conjunction with accompanying drawing and specific implementation method, should be appreciated that the present invention is not limited to following preferred implementation, present embodiment is as just the illustrative embodiment of this patent.
Description of drawings
Fig. 1: the structural representation of punch through effect enhanced type silicon photo transistor of the present invention;
Fig. 2: (a) punch through effect enhanced type silicon photo transistor of the present invention is along the profile of AA ';
(b) punch through effect enhanced type silicon photo transistor of the present invention is along the profile of BB ';
Fig. 3: the I-V curve chart of punch through effect enhanced type silicon photo transistor of the present invention;
Fig. 4: the opto-electronic conversion gain curve figure of punch through effect enhanced type silicon photo transistor of the present invention;
As shown in Figure 1, be punch through effect enhanced type silicon photo transistor structural representation of the present invention, wherein: 1 is N-type (or P type) layer-of-substrate silicon; 2 is P trap (or N trap) layer; 3 (3 ') were N-type (or P type) The heavy doping active area; 4 (4 ') were grid oxygen silicon dioxide layer; 5 (5 ') were polysilicon layer; 6 is the place titanium dioxide Silicon layer; 7 (7 ') were metal electrode layer.
As shown in Figure 2, be punch through effect enhanced type silicon photo transistor profile of the present invention, contain long base District's phototransistor and short base phototransistor. Wherein Fig. 2 (a) is the profile along AA ', has above the expression The short base phototransistor that polysilicon covers; Fig. 2 (b) is the profile along BB ', and expression has the place titanium dioxide The growing base area phototransistor that silicon covers.
In the inside of P trap (or N trap) layer 2, the N-type of two U glyph shape (or P type) heavy doping has Source region 3 (3 ') is looped around the outside of place silicon dioxide layer 6, their upper surface all with the upper table of P trap layer 2 Face is equal, and the degree of depth of heavy doping active area 3 (3 ') (highly) is less than the degree of depth (height of place silicon dioxide layer 6 Spend), and the degree of depth of place silicon dioxide layer 6 (highly) is less than the degree of depth (highly) of P trap. The heavy doping active area 3 (3 '), two symmetrical structures that it is divided into by 4 (4 ') of grid oxygen silicon dioxide layer and polysilicon layer 5 (5 '), Each all is similar to " U " font.
As shown in Figure 3, this figure hollow core square, hollow circular institute are linked to be curve to represent respectively the punch through effect enhanced type silicon photo transistor that the embodiment of the invention prepares are 1 * 10 not having illumination and incident optical power density-6W/cm
2The time the I-V curve map. As can be seen from the figure when forward bias during in the 2V left and right sides, there is not light According to the situation that illumination is arranged under device current approximately be respectively 1 μ A and 2 μ A.
As shown in Figure 4, the punch through effect enhanced type silicon photo transistor of expression embodiment of the invention preparation is 1 * 10 in incident optical power density-6W/cm
2The time the curve map that changes with forward bias of opto-electronic conversion gain. The conversion of device Gain has maximum at forward bias during for 2V, is approximately 4 * 106。
Compare punch through effect enhanced type silicon photoelectricity crystalline substance of the present invention with the people's such as Hailin Luo result of study Body pipe photoelectric conversion gain is obviously greater than the former, and the electric current when unglazed will be much smaller than the former.
Embodiment
Embodiment 1:
Because punch through effect enhanced type silicon photo transistor of the present invention is complete and standard CMOS process compatibility, therefore can specifically implement on any one standard CMOS process line.Adopt 0.5 μ m characteristic size with one below, the NPN type punch through effect enhanced type silicon photo transistor that the two trap CMOS technologies of the standard of two-layer polysilicon, three-layer metal are made is that example illustrates concrete preparation method.
A: the selection of substrate---choose P type＜100〉silicon substrate, the resistance substrate rate is 15 Ω cm, thickness is 100 μ m;
B: the formation of well region---inject and pick into formation trap by energetic ion.Owing to be to make NPN type phototransistor, adopt the base of P trap as device, i.e. 2 among Fig. 1.Inject As, injection energy and dosage that ion injects are respectively 100keV and 5 * 10
12Cm
-2Advance 30 minutes down through 1000 ℃ of high temperature, the doping content that makes final trap is 10
17cm
-3, be shaped as cuboid, long and wide 12 μ m and the 5 μ m of being respectively, the degree of depth is 3.0 μ m;
C: carry out selective oxidation---by under steam and the following 500 ℃ of high temperature of oxygen atmosphere and substrate silicon reaction generation place silicon dioxide layer, the position is in the P trap, long and wide 8 μ m and the 2 μ m of being respectively, thick 0.4 μ m.So just formed the P trap frame of wide 1.5～2 μ m, be used for subsequent step and carry out the ion injection to form the heavy doping active area at the edge of P trap; Because pasc reaction generates SiO
2Volume increases, and is higher than chip surface so reaction finishes the back area silica surface, adopts the method for chemico-mechanical polishing to even out, has formed at last as the zone 6 among Fig. 1 and Fig. 2 (b);
D: preparation polysilicon layer---middle position, the strip grid oxygen silicon dioxide layer of growth thickness 10nm symmetrically along the axis at device surface, two ends, the narrow limit of place silicon dioxide layer.Growing method is hot oxygen oxidizing process, temperature is 1100 ℃, growth time is 1 hour, method by conventional photoetching obtains the grid oxygen silicon dioxide layer that length and width are respectively 3 μ m and 1 μ m again, it is along the axis symmetry of place silicon dioxide layer, and the length that wherein covers on the silicon dioxide layer of place is 1 μ m.The chemical gaseous phase epitaxy method that on grid oxygen silicon dioxide layer, utilizes 500 ℃ of following silane and oxygen the to react polysilicon layer of same size, thickness 200nm of growing then, zone 5 and 5 ' as shown in Figure 1.4 (4 ') and 6 composition all are silicon dioxide layers, but the growth pattern difference, 4 (4 ') were to obtain by hot oxygen oxidizing process, the 6th, and wet-oxygen oxidation obtains, and therefore 4 (4 ') are than 6 densifications;
The energetic ion injection is carried out in E: the formation of heavy doping active area---the well region center that forms in step B in the long and wide rectangular region that is respectively 10 μ m and 4 μ m.For NPN type device, inject N type impurity A s, inject energy and dosage and be respectively 20keV and 5 * 10
15Cm
-2, 1000 ℃ of following high annealings are 10 minutes then.Zone line at device, because the place silicon dioxide layer that forms among the step C has blocked the ion injection, therefore the P trap of place silicon dioxide layer below is not injected into ion, mix, base as the growing base area phototransistor, the ion implanted region territory on both sides has constituted the collector region and the emitter region of growing base area phototransistor at a distance of 2 μ m; Because the polysilicon layer that forms among the step D has blocked the ion injection equally, therefore the P trap of polysilicon layer below does not inject ion, mix, base as short base phototransistor, ion implanted region territory, both sides has constituted the collector region and the emitter region of short base phototransistor at a distance of 1 μ m.Make after the annealing that the doping content in ion implanted region territory is 10
17Cm
-3, the degree of depth is 0.15 μ m;
F: metal electrode layer---utilizing thermal evaporation method under 1000 ℃, to carry out on the device 10 minutes, obtaining thickness is the strip metal Al electrode material of 0.5 μ m, must arrive the position by photoetching and lay respectively at collector region and the center, emitter region that forms in the step e, with the long justified margin of well region, long and wide is respectively 11 μ m and 1.5 μ m, constitute collector region electrode and emitter region electrode, thereby finish preparation of devices.
Above step and standard CMOS process flow process are compatible fully, and without any need for other unnecessary step.The overall size of resulting devices is 60 μ m
2, can make device size on the basis that keeps original performance littler by the optimal design of domain.So little size can be easily carried out integratedly at standard CMOS process other auxiliary circuits that neutralize, and greatly reduces cost.
Claims (8)
1, NPN type punch through effect enhanced type silicon photo transistor, it is characterized in that: comprise layer-of-substrate silicon (1) from the bottom to top successively, be positioned at the P trap layer (2) of layer-of-substrate silicon (1), be positioned at two discrete N type heavy doping active areas (3 of P trap layer (2), 3 '), be positioned at P trap layer, by two N type heavy doping active areas (3,3 ') around place silicon dioxide layer (6), be positioned at two discrete strip grate oxygen silicon dioxide layers (4 of narrow side of P trap layer (2) and place silicon dioxide layer (6) upper surface, 4 '), cover grid oxygen silicon dioxide layer (4,4 ') on, two the discrete polysilicon layers (5,5 ') identical with grid oxygen silicon dioxide layer shape, be positioned at the wide side upper surface of P trap layer (2) and with two discrete N type heavy doping active areas (3,3 ') the bullion electrode layer (7,7 ') that links to each other respectively.
2, NPN type punch through effect enhanced type silicon photo transistor as claimed in claim 1, it is characterized in that: two discrete N type heavy doping active areas (3,3 ') the U-shaped zone of two symmetries that are divided into by grid oxygen silicon dioxide layer (4,4 ') and polysilicon layer (5,5 ').
3, NPN type punch through effect enhanced type silicon photo transistor as claimed in claim 2 is characterized in that: the upper surface of P trap layer (2), two discrete N type heavy doping active areas (3,3 ') and place silicon dioxide layer (6) is positioned at same plane.
4, as claim 2 or 3 described NPN type punch through effect enhanced type silicon photo transistor, it is characterized in that: two discrete N type heavy doping active areas (3,3 ') the degree of depth is less than the degree of depth of place silicon dioxide layer (6), and the degree of depth of place silicon dioxide layer (6) is less than the degree of depth of P trap layer (2).
5, the positive-negative-positive punch through effect enhanced type silicon photo transistor, it is characterized in that: comprise layer-of-substrate silicon (1) from the bottom to top successively, be positioned at the N trap layer (2) of layer-of-substrate silicon (1), be positioned at two discrete P type heavy doping active areas (3 of N trap layer (2), 3 '), be positioned at N trap layer, by two P type heavy doping active areas (3,3 ') around place silicon dioxide layer (6), be positioned at two discrete strip grate oxygen silicon dioxide layers (4 of narrow side of N trap layer (2) and place silicon dioxide layer (6) upper surface, 4 '), cover grid oxygen silicon dioxide layer (4,4 ') on, two the discrete polysilicon layers (5,5 ') identical with grid oxygen silicon dioxide layer shape, be positioned at the wide side upper surface of N trap layer (2) and with two discrete P type heavy doping active areas (3,3 ') the bullion electrode layer (7,7 ') that links to each other respectively.
6, positive-negative-positive punch through effect enhanced type silicon photo transistor as claimed in claim 5, it is characterized in that: two discrete P type heavy doping active areas (3,3 ') the U-shaped zone of two symmetries that are divided into by grid oxygen silicon dioxide layer (4,4 ') and polysilicon layer (5,5 ').
7, positive-negative-positive punch through effect enhanced type silicon photo transistor as claimed in claim 6 is characterized in that: the upper surface of N trap layer (2), two discrete P type heavy doping active areas (3,3 ') and place silicon dioxide layer (6) is positioned at same plane.
8, as claim 6 or 7 described positive-negative-positive punch through effect enhanced type silicon photo transistor, it is characterized in that: two discrete P type heavy doping active areas (3,3 ') the degree of depth is less than the degree of depth of place silicon dioxide layer (6), and the degree of depth of place silicon dioxide layer (6) is less than the degree of depth of N trap layer (2).
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| CN102024863A (en) * | 2010-10-11 | 2011-04-20 | 湘潭大学 | High-speed enhanced ultraviolet silicon selective avalanche photodiode and manufacturing method thereof |
| CN102497517A (en) * | 2011-11-25 | 2012-06-13 | 吉林大学 | Low-operating voltage wide dynamic range image sensor |
| CN102820287A (en) * | 2012-08-03 | 2012-12-12 | 中国科学院上海技术物理研究所 | Solar battery with pn junction array light acceptance structure |
| CN105226128A (en) * | 2014-05-30 | 2016-01-06 | 徐永珍 | Optical sensing subassembly and manufacture method thereof |
| CN106876515A (en) * | 2017-03-06 | 2017-06-20 | 中国科学院宁波材料技术与工程研究所 | Visible blind photodetector of thin-film transistor structure and preparation method thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102024863A (en) * | 2010-10-11 | 2011-04-20 | 湘潭大学 | High-speed enhanced ultraviolet silicon selective avalanche photodiode and manufacturing method thereof |
| CN102024863B (en) * | 2010-10-11 | 2013-03-27 | 湘潭大学 | High-speed enhanced ultraviolet silicon selective avalanche photodiode and manufacturing method thereof |
| CN102497517A (en) * | 2011-11-25 | 2012-06-13 | 吉林大学 | Low-operating voltage wide dynamic range image sensor |
| CN102820287A (en) * | 2012-08-03 | 2012-12-12 | 中国科学院上海技术物理研究所 | Solar battery with pn junction array light acceptance structure |
| CN105226128A (en) * | 2014-05-30 | 2016-01-06 | 徐永珍 | Optical sensing subassembly and manufacture method thereof |
| CN106876515A (en) * | 2017-03-06 | 2017-06-20 | 中国科学院宁波材料技术与工程研究所 | Visible blind photodetector of thin-film transistor structure and preparation method thereof |
| CN106876515B (en) * | 2017-03-06 | 2018-07-10 | 中国科学院宁波材料技术与工程研究所 | Visible blind photodetector of thin-film transistor structure and preparation method thereof |
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