CN101425103A - Optional waveform generator based on PCI bus - Google Patents
Optional waveform generator based on PCI bus Download PDFInfo
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- CN101425103A CN101425103A CNA2008100462236A CN200810046223A CN101425103A CN 101425103 A CN101425103 A CN 101425103A CN A2008100462236 A CNA2008100462236 A CN A2008100462236A CN 200810046223 A CN200810046223 A CN 200810046223A CN 101425103 A CN101425103 A CN 101425103A
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Abstract
The invention relates to an arbitrary waveform generator based on a PCI bus, which comprises the PCI bus being a local bus not attached to some a concrete processor. Structurally, the PCI is a primary bus which is inserted between a CPU and an original system bus, management on the layer is concretely realized by a bridge circuit, and an interface between top and bottom is realized to coordinate data transportation. An application layer buffer zone can continuously exchange data. The process of the data transportation is sponsored by an application layer program, but is executed by a chip PLX9054 of a PCI bridge interface, application layer software can carry out data generation and allocation in the process, and the whole transportation process is completed by direct memory access (DMA) and interruption. By utilizing the buffer zone to fast exchange the data, the arbitrary waveform generator can fast carry out data exchange, efficiently ensures the continuity of space signals and the fast switch of multiple signals, and has the advantages in multiple aspects such as flexibility, rapidness, changeability, controllability, high accuracy, and the like.
Description
Technical field
The present invention relates to a kind of AWG (Arbitrary Waveform Generator), particularly can satisfy the various waveform signals in fields such as communication, video and TV, telecommunications, radar, ultrasound wave and aviation checkout equipment and use, based on the AWG (Arbitrary Waveform Generator) of pci bus.
Background technology
AWG (Arbitrary Waveform Generator) is a requisite instrument and equipment in the signal Processing field.AWG (Arbitrary Waveform Generator) is used widely at aspects such as communication system, test macros.AWG (Arbitrary Waveform Generator) much can not produce fast, effectively, continuously and the signal waveform that is easy to customize in the prior art.Existing AWG (Arbitrary Waveform Generator) mainly contains based on the CPLD technical design, by upper computer software the generation waveform is set, then Wave data is downloaded to AWG, AWG send high-speed DAC to change the AWG AWG (Arbitrary Waveform Generator) that forms waveform Wave data under the High-speed Control circuit of CPLD.The course of work of this AWG AWG (Arbitrary Waveform Generator) is, at first receive the waveform digital signal that host computer sends here and store static memory SRAM into, the start-up control circuit send the DAC number to touch conversion from static memory SRAM taking-up data then, and the simulating signal after the conversion send low-pass filter to form waveform.
Another kind is that application number is 200610154451.6, publication number is the disclosed a kind of high speed arbitrary waveform generator based on FPGA of CN101017383 Chinese patent, and this AWG (Arbitrary Waveform Generator) mainly comprises CPU, parallel data phase place generating portion, waveform storage area, interpolation and compositions such as filtering part, parallel-to-serial converter and DAC.Wherein the parallel data phase place generates and adopts parallel processing, can in a clock, generate the phase place of a plurality of data simultaneously, obtain a plurality of data, and then utilize the parallel-to-serial converter among the FPGA that data are outputed to DAC successively, data-switching is become analog quantity by DAC.In a clock, can generate a plurality of data simultaneously, key breakthrough the restriction of FPGA frequency of operation, can provide above the data sampling rate more than the 1GHz to DAC.We know, can produce continuous, uninterrupted, the different simulating signal of pattern, are the key points of AWG (Arbitrary Waveform Generator).But the weak point of above-mentioned prior art AWG (Arbitrary Waveform Generator) is to produce various high-quality, sophisticated signal waveform quick, effective, continuous and that be easy to customize.
Summary of the invention
Task of the present invention is that proposition is a kind of fast, effective, continuous, and compared with prior art more flexible and variable, controlled AWG (Arbitrary Waveform Generator).
Purpose of the present invention can reach by following measure.A kind of AWG (Arbitrary Waveform Generator) based on pci bus provided by the present invention comprises: pci bus, do not depend on the local bus of certain concrete processor, and it is characterized in that, comprise
A D/A change-over circuit that is connected between power supply and the ground;
A cpu chip that contains application layer software and driver software, use high-end data processing software wherein carries out the simulation process of signal, then emulated data is directly put into the application layer buffer zone;
One include the PCI device of register and be inserted in CPU and system bus between pci bus, it is the one-level bus of between CPU and original system bus, inserting, specifically realize management, and the interface between realizing up and down is with the transmission of coordination data to this one deck by bridgt circuit;
Pci controller with multi-buffer utilizes it can make peripheral hardware and CPU concurrent working on the pci bus;
A bridgt circuit that is connected between CPU and the peripheral hardware, major function are to change between two kinds of different signal environments, and all master controllers provide consistent bus interface in system, are used for transmission information between pci bus and LOCAL bus;
One is connected programmable logic device (CPLD) with interface chip, and major function is to carry out calling of local sequential to greatest extent, to reach optimum data transmission;
After direct memory access DMA transmission beginning, at first data among the static memory SRAM1 are transmitted, notified programmable logic device (CPLD) then, the enabling address counter, data among the static memory SRAM1 are sent to D/A, produce analog signal waveform by digital-to-analog conversion.
The present invention has following beneficial effect than common waveform generator technology.
The present invention proposes a kind of buffer zone quick exchange data of utilizing, based on the AWG (Arbitrary Waveform Generator) of pci bus.This AWG (Arbitrary Waveform Generator) can be carried out the data replacing fast, guarantees the continuity of spacing wave and the quick switching of many signals effectively.Have many-sided advantages such as flexible, quick, variable, controlled, precision height.Because its performance able to programme is superior, as long as therefore can guarantee accurately to set up the mathematical model of signal, just can obtain the corresponding output of simulation accurately result, thereby for providing complicated signal generation environment and high-quality signal waveform pattern that strong assurance is provided, and can satisfy the demand of various high-quality, sophisticated signal, thereby alleviate the research precision that has influence on owing to environmental factor and waveform quality.Described application layer buffer zone has been opened up two blocks of data buffer zones, and in the driving of bottom software design, blocking and buffering carries out corresponding data buffering mapping to application layer respectively, has guaranteed that the hardware data laser propagation effect reaches optimum efficiency.The signal damping that manager provides can be supported 10 kinds of peripheral hardwares, and keeps high-performance under high clock frequency.The application layer buffer zone has been opened up two blocks of data buffer zones, and in the driving of bottom software design, blocking and buffering carries out corresponding data buffering mapping to application layer respectively, guarantee hardware the data transmission effect reach optimum efficiency.The transmission course of data is initiated by the application layer program, and software application layer does not need consumes resources just can finish the transmission of data fully.And application layer software can carry out the generation and the allotment of data in this process.Can carry out data fast and change, guarantee the continuity of spacing wave and the quick switching of many signals effectively.
Beneficial effect of the present invention also is:
1. transmission speed is fast.Maximum operation frequency 33MHz, peak value throughput are 132Mb/s in the time of 32, are 264Mb/s in the time of 64.
2. the read-write mode of supporting infinitely to burst has powerful data burst transmittability.Numerous cycle data can be followed in the back during read-write.
3. support the concurrent working mode.Pci controller has multi-buffer, utilizes it can make peripheral hardware and CPU concurrent working on the pci bus.For example during the CPU output data, earlier data are delivered in the impact damper fast, when these data constantly are sent to equipment, CPU just can then execution other work.
4. be independent of processor.PCI inserts the administration and supervision authorities of a complexity between CPU and peripheral hardware, in order to the coordination data transmission, be referred to as bridge usually.The major function of bridge is to change between two kinds of different signal environments, and all master controllers provide consistent bus interface in system.Therefore pci bus can be supported the processor of multiple series, and has created condition for processor upgrade.
5. can provide 4 kinds of specifications at least, 32/64 of definables and 5V/3.3V voltage signal.3.3V the voltage signal environment is defined as pci bus and enters the portable machine field and provide convenience.
6. the multiplexing structure data line and the address wire of Cai Yonging reduced pin number.Generally speaking, 32 word lengths, the interface of only making target device only need 47 pins, add 2 pins again as bus master's equipment interface, and can increase the signal wire expanded function selectively.Support plug-and-play feature, can realize configuration automatically.The register that comprises on the PCI device has the required device information of configuration above, and the peripheral hardware adapter can be configured when being connected with system automatically, need not manual intervention.
Description of drawings
In order more to be expressly understood the present invention, now will simultaneously with reference to accompanying drawing, the present invention be described by the embodiment of the invention, wherein:
Fig. 1 is an AWG (Arbitrary Waveform Generator) hardware configuration block scheme of the present invention.
Fig. 2 is an impact damper mapping graph of the present invention.
Fig. 3 is simulated effect figure of the present invention.
Fig. 4 is a D/A output analogous diagram of the present invention.
Embodiment
Consult Fig. 1.AWG (Arbitrary Waveform Generator) mainly comprises, D/A change-over circuit, cpu chip, pci bus, pci controller, bridgt circuit, programmable logic device (CPLD), application layer buffer zone; Described D/A change-over circuit is used for the conversion of digital signal and simulating signal; Include application layer software and driver software in the cpu chip, be used for signal simulation, and emulated data is put into the application layer buffer zone; Pci bus is the one-level bus of inserting between CPU and original system bus, and on structure, specifically by the management of a bridgt circuit realization to this one deck, the interface between being used to realize up and down is with the transmission of coordination data; Pci controller has multi-buffer, is used for administration PC I slot, make the peripheral hardware that is connected on the PCI slot can with the CPU concurrent working; Bridgt circuit is used for changing between two kinds of different signal environments, and all master controllers provide consistent bus interface in system; Programmable logic device (CPLD) is used for calling and data transmission of local sequential; Application layer buffer zone, swap data continuously.
The transmission course of data is initiated by the application layer program, but is carried out by pci bridge interface chip PLX9054.PLX9054 works in holotype.Under this pattern, software application layer does not need consumes resources just can finish the transmission of data fully.And application layer software can carry out the generation and the allotment of data in this process.Whole transmission course is finished by DMA and interruption.
After DMA transmission beginning, at first the SRAM1 that is connected with the PLX9054 interface chip is carried out data transmission, notice is connected the programmable logic device (CPLD) between PLX9054 interface chip and two SRAM then, start the address counter of CPLD inside, to be sent to D/A with the data among the SRAM1 that the PLX9054 interface chip is connected, produce analog signal waveform by digital-to-analog conversion.During D/A sent data, the application layer program began to transmit data in second static RAM (SRAM) 2 that is connected between PLX9054 and the CPLD by pci bus notice PLX9054 at SRAM1.Simultaneously, application layer software can be prepared data for the first blocks of data district again, after having transmitted data to second static RAM (SRAM), detects first static RAM (SRAM) that is connected between PLX9054 and the CPLD.If the data in first block RAM distribute at this moment, so just start second block RAM, send data to D/A, meanwhile, begin again in first static RAM (SRAM), to transmit data, it is that second block RAM is prepared data that application layer software then begins.So go round and begin again.If the condition of work design is comparatively desirable, so just can obtain the simulating signal continuous, uninterrupted, that form is different.
Consult Fig. 2, the data that the application layer program produces are sent into bottom layer driving, then by bottom layer driving software with data distribution in the storage space of hardware.Software design is carried out the simulation process of signal earlier by high-end data processing software, then emulated data is directly put into the application layer buffer zone.Because considering, native system adapts to certain fast data exchange, do not allow to occur the interruption phenomenon of spacing wave under the ideal state, therefore open up two blocks of data buffer zones in application layer, difference label buffer zone 1BUFFER1 and buffer zone 2BUFFER2, after having adorned BUFFER1, re-use data and fill BUFFER2.As long as distribute rationally, just can be at application layer swap data continuously.In the driving of bottom software design, blocking and buffering carries out corresponding data buffering mapping to application layer respectively, because bottom layer driving is directly hardware-related, therefore need design the buffer zone piecemeal that extremely mates with hardware as far as possible, to reach best hardware data laser propagation effect.
The VC++ compiler environment of MS is adopted in the establishment of application layer software.VC is one of main programming language under the Windows system, has easy maintenance upgrade, friendly interface, code efficiency height with the system of its exploitation, series of advantages such as execution speed is fast, and can be directly and system and bottom hardware swap data.The design of driver and making adopt the DriverWorks of NuMega company to drive development kit.DriverWorks is in the mode of object-oriented (OOP), with write WDM and WINNT driver required kernel mode visit and access hardware are packaged into class.As long as under the guide of its wizard program, fill in steps necessary like this, just can finish the framework of required driver easily according to the concrete parameter of hardware.At last add the driver that new class object and required code just can successfully be finished oneself according to concrete requirement.DriverWorks is based on VC++'s, and what it generated is the VC engineering of standard, as long as the engineering of being built is compiled under VC, just can generate final device driver.The pci interface circuit adopts PCI special purpose interface chip PLX9-054.
PLX9054 is that accord with PCI V2.2 standard adopts 176 pin PQFP and two kinds of packing forms of 225 pin PBGA by the advanced person's of U.S. PIX company production PCII/OAccelerator.PLX9054 provides pci bus, EEPROM, three interfaces of LOCAL bus.PLX9054 is as a kind of bridging chip, transmission information between pci bus and LOCAL bus, and the main control equipment that both can be used as two buses removes control bus, and the target device that also can be used as two buses removes response bus.PLX9054 has adopted advanced PLX data pipe structure technology, is 32, the general pci bus controller special chip of 33MHz, and is powerful, use flexibly.The static RAM (SRAM) of PLX9054 adopts the CY7C1041 static RAM (SRAM) of Cypress company.The D/A change-over circuit of PLX9054 adopts 16 D/A digital to analog converters of AD768 high speed of AnalogDevice company, and data-switching speed reaches 30MSPS, is a kind of high speed, stable current-mode d/a converter.
If only consider the way of common AWG (Arbitrary Waveform Generator), do not need so too much consideration is carried out in the design in application layer, Drive Layer and hardware buffer district, as long as open an enough big data buffer, put the static RAM (SRAM) of enough capacity, data with needs pour into static RAM (SRAM) then, just can finish the function of a high-performance AWG (Arbitrary Waveform Generator).
Native system adopts the Matlab simulation software that the data generation file of signal is carried out emulation, and the conditionally complete of emulation is set to real data analog signal output condition, and simulated program and effect are as shown in Figure 3.Be exemplified below: if produce a centre frequency is 5MHz, and the frequency modulation width is the Chip signal of 2MHz, uses the signal of 30MHz to recover sampling clock, in strict conformity with sampling thheorem.Produced the data file of a 16K by simulated program, as long as with this file pack into buffer zone, the just analog waveform that can obtain exporting.Then with the oscillograph collection of D/A output waveform, just can obtain clearly, with D/A output analogous diagram shown in Figure 4 in the living output pattern of step.
Claims (3)
1. AWG (Arbitrary Waveform Generator) based on pci bus comprises: pci bus, do not depend on the local bus of certain concrete processor, and it is characterized in that, comprise
A D/A change-over circuit that is connected between power supply and the ground;
A cpu chip that contains application layer software and driver software, use high-end data processing software wherein carries out the simulation process of signal, then emulated data is directly put into the application layer buffer zone;
One include the PCI device of register and be inserted in CPU and system bus between pci bus, it is the one-level bus of between CPU and original system bus, inserting, specifically realize management, and the interface between realizing up and down is with the transmission of coordination data to this one deck by bridgt circuit;
Pci controller with multi-buffer makes peripheral hardware and CPU concurrent working on the pci bus;
A bridgt circuit that is connected between CPU and the peripheral hardware is changed between two kinds of different signal environments, and all master controllers provide consistent bus interface in system, are used for transmission information between pci bus and local LOCAL bus;
One is connected programmable logic device (CPLD) with interface chip, is used for calling and data transmission of local sequential; After direct memory access DMA transmission beginning, at first data among the static memory SRAM1 are transmitted, notified programmable logic device (CPLD) then, the enabling address counter, data among the static memory SRAM1 are sent to D/A, produce analog signal waveform by digital-to-analog conversion.
2. the AWG (Arbitrary Waveform Generator) based on pci bus as claimed in claim 1 is characterized in that, bottom software is provided with the buffer zone piecemeal to what application layer was carried out the mapping of corresponding data buffering respectively.
3. the AWG (Arbitrary Waveform Generator) based on pci bus as claimed in claim 1 is characterized in that, the data that the application layer program produces are sent into bottom layer driving, then by bottom layer driving software with data distribution in hardware memory space.
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| CNA2008100462236A CN101425103A (en) | 2008-10-07 | 2008-10-07 | Optional waveform generator based on PCI bus |
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| CNA2008100462236A CN101425103A (en) | 2008-10-07 | 2008-10-07 | Optional waveform generator based on PCI bus |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103577243A (en) * | 2012-08-06 | 2014-02-12 | 比亚迪股份有限公司 | Signal simulation device and signal board card |
| CN103592996A (en) * | 2012-08-14 | 2014-02-19 | 长春迪派斯科技有限公司 | Structure and device of plug-in multichannel function/arbitrary waveform generator |
| CN104572527A (en) * | 2014-12-29 | 2015-04-29 | 中国船舶重工集团公司七五○试验场 | Waveform reproduction technology based on massive data |
| CN102109876B (en) * | 2009-12-28 | 2015-07-15 | 北京普源精电科技有限公司 | Signal generator with higher waveform data reading speed |
| CN107561982A (en) * | 2017-08-29 | 2018-01-09 | 广东电网有限责任公司电力科学研究院 | A kind of arbitrarily signal generating device and its output control method based on terminal fitting |
| CN109799869A (en) * | 2019-01-24 | 2019-05-24 | 中国人民解放军火箭军工程大学 | 2 channel 5.0Gsps 12bit PCI ExpressGen3FPGA of one kind |
| CN109814656A (en) * | 2018-12-28 | 2019-05-28 | 中电科仪器仪表有限公司 | A kind of signal generating apparatus and method for arbitrary waveform generator |
| CN113419597A (en) * | 2021-07-12 | 2021-09-21 | 山东浪潮科学研究院有限公司 | Working method, equipment and medium of arbitrary waveform generator |
| CN114443536A (en) * | 2022-01-26 | 2022-05-06 | 西安凯锐测控科技有限公司 | Method for changing setting parameters of signal generator |
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2008
- 2008-10-07 CN CNA2008100462236A patent/CN101425103A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102109876B (en) * | 2009-12-28 | 2015-07-15 | 北京普源精电科技有限公司 | Signal generator with higher waveform data reading speed |
| CN103577243A (en) * | 2012-08-06 | 2014-02-12 | 比亚迪股份有限公司 | Signal simulation device and signal board card |
| CN103577243B (en) * | 2012-08-06 | 2017-02-08 | 比亚迪股份有限公司 | Signal simulation device and signal board card |
| CN103592996A (en) * | 2012-08-14 | 2014-02-19 | 长春迪派斯科技有限公司 | Structure and device of plug-in multichannel function/arbitrary waveform generator |
| CN103592996B (en) * | 2012-08-14 | 2017-03-08 | 长春迪派斯科技有限公司 | A kind of structure of card insert type multichannel function/arbitrary waveform generator and device |
| CN104572527A (en) * | 2014-12-29 | 2015-04-29 | 中国船舶重工集团公司七五○试验场 | Waveform reproduction technology based on massive data |
| CN107561982A (en) * | 2017-08-29 | 2018-01-09 | 广东电网有限责任公司电力科学研究院 | A kind of arbitrarily signal generating device and its output control method based on terminal fitting |
| CN109814656A (en) * | 2018-12-28 | 2019-05-28 | 中电科仪器仪表有限公司 | A kind of signal generating apparatus and method for arbitrary waveform generator |
| CN109799869A (en) * | 2019-01-24 | 2019-05-24 | 中国人民解放军火箭军工程大学 | 2 channel 5.0Gsps 12bit PCI ExpressGen3FPGA of one kind |
| CN113419597A (en) * | 2021-07-12 | 2021-09-21 | 山东浪潮科学研究院有限公司 | Working method, equipment and medium of arbitrary waveform generator |
| CN113419597B (en) * | 2021-07-12 | 2023-04-11 | 山东浪潮科学研究院有限公司 | Working method, equipment and medium of arbitrary waveform generator |
| CN114443536A (en) * | 2022-01-26 | 2022-05-06 | 西安凯锐测控科技有限公司 | Method for changing setting parameters of signal generator |
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