CN101424654A - Copper lead wire circuit board diagram structure for testing erode of interlayer medium - Google Patents
Copper lead wire circuit board diagram structure for testing erode of interlayer medium Download PDFInfo
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- CN101424654A CN101424654A CNA2008102388139A CN200810238813A CN101424654A CN 101424654 A CN101424654 A CN 101424654A CN A2008102388139 A CNA2008102388139 A CN A2008102388139A CN 200810238813 A CN200810238813 A CN 200810238813A CN 101424654 A CN101424654 A CN 101424654A
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Abstract
The invention discloses a structure of a copper leading wire circuit map used for measuring whether interlayer media are eroded. The copper leading wire circuit map comprises a copper resistor array which comprises a plurality of equal-width copper leading wires arranged in equal distance. At least four copper leading wires are arranged. The four copper leading wires are connected end to end in series in the copper resistor array. The front end and the tail end of the copper resistor array are respectively provided with a current leading-out port. At least three copper leading wires of equal length are arranged in the copper resistor array. Both ends of each copper leading wire of equal length are respectively provided with a voltage leading-out port. The invention can be used in electricity for measuring whether the interlayer media of the copper leading wires are eroded after the CMP process of the copper leading wires. The method has simple structure, small occupied area of the map, convenient inlaying and convenient test and measurement. When the electric method is used for measurement, the influence of the wire size does not exist, the entire chip can be conveniently measured, and the uniformity of the chip CMP can be excellently verified.
Description
Technical field
The present invention relates to a kind of semiconductor device circuit domain structure, particularly a kind ofly be used to test the copper lead wire circuit domain structure whether inter-level dielectric produces erosion.
Background technology
Along with the raising of manufacturing process, constantly the reducing of device size, interconnection line postpones to become to influence the entire circuit bottleneck of performance.Postpone in order to reduce interconnection line, adopt the littler copper of resistivity as metal lead wire.And in the multilayer wiring spatial structure, guarantee that every layer can both reach the key that leveling is the realization multilayer wiring, be one of generally acknowledged preferred plan in the whole world and adopt CMP (CMP (Chemical Mechanical Polishing) process) technology.The copper lead-in wire that adopts Damascus technics to form also needs the unnecessary copper polishing with deposit by CMP, only stays the copper lead-in wire in the raceway groove.These all make copper-connection CMP become and enjoy one of core technology of countries in the world concern in ULSI (the ultra-large scale integration VLSI (very large scale integrated circuit)) manufacture process, but many because of its subject that relates to, technical difficulty is big, Related Mechanism is also treated further research.
In the CMP process of Cu wiring,, caused the out-of-flatness of chip surface because the material with different polishing speeds is polished simultaneously.Two kinds of defectives occur behind the Cu wiring CMP, wherein a kind of defective is called the pit phenomenon, promptly occurs depression in the copper cash, represents size with the difference in height between the minimum point in dielectric layer and the Cu line; Another kind of defective is exactly an erosion, refers to that interlayer dielectric layer is by a jettisoning part after the polishing of high pattern density district, and the dielectric layer height of available design and the difference of true altitude are represented.
In ULSI multilayer wiring CMP, the spill problem after the polishing has very big influence to electric properties of devices, yield rate.The appearance of copper lead-in wire concave pit has reduced the thickness of metal connecting line, has increased lead resistance, thereby has reduced the reliability of device, causes circuit malfunction thereby make device might produce broken string, produces catastrophic consequence.The spill problem has become the most scabrous technology among the copper wiring CMP, directly has influence on the realization of leveling, and the formation that reduces concave pit is to realizing that complanation is significant.
For the matrix hole of copper lead-in wire formation behind the CMP and the erosion of dielectric layer, generally be to measure with atomic force microscope (AFM), but along with constantly reducing of line thickness, the investigative range of atomic force microscope is quite limited, and the measuring process complexity.
Summary of the invention
The technical issues that need to address of the present invention just are to overcome the defective of the defect test process complexity such as erosion of the inter-level dielectric that forms for copper lead-in wire behind the CMP in the prior art, a kind of copper lead wire circuit domain structure whether inter-level dielectric produces erosion that is used to test is provided, it carries out simple electrical measurement by the copper lead-in wire figure to described circuit layout, just can know the performance that finishes the copper lead-in wire of back formation in CMP (Chemical Mechanical Polishing) process.Make after CMP forms the copper lead-in wire, can measure the copper lead-in wire inter-level dielectric that forms by electrical method and whether produce erosion.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
The present invention is a kind of to be used to test the copper lead wire circuit domain structure whether inter-level dielectric produces erosion, described copper lead wire circuit domain comprises the copper resistance array that a copper lead-in wire that equated by many width, that uniformly-spaced arrange constitutes, the radical of copper lead-in wire is greater than 3, copper lead-in wire head and the tail are in series in the described copper resistance array, described copper resistance array two ends are respectively arranged with an electric current and draw port, the copper lead-in wire that has three equal in length in the copper resistance array at least, the copper lead-in wire two ends of each equal in length are respectively arranged with a voltage leading-out ends mouth.
Distance between two voltage leading-out ends mouths on every copper lead-in wire that the voltage leading-out ends mouth arranged equates.
A preferred version of the present invention is: described copper resistance array is made of 13 copper lead-in wires.The copper lead-in wire that 5 equal in length are arranged in the described copper resistance array.
The present invention can be used for electrical measurement copper lead-in wire copper lead-in wire inter-level dielectric after the CMP process and whether produce erosion.The method is simple in structure, and it is little to take chip area, is convenient to embed in the domain, and experiment measuring is convenient.Adopt this electrical method to measure, be not subjected to the influence of line size, can measure entire chip easily, well the homogeneity of proofing chip CMP.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
As shown in Figure 1, the present invention is a kind of to be used to test the copper lead wire circuit domain structure whether inter-level dielectric produces erosion, described copper lead wire circuit domain comprises copper lead-in wire 1 a copper resistance array 10 that constitutes that is equated, uniformly-spaced arranged by 13 width, the copper lead spacing is h, width all is W, copper lead-in wire head and the tail are in series in the described copper resistance array, described copper resistance array two ends are respectively arranged with an electric current and draw port 2, the copper lead-in wire that 5 equal in length are arranged in the copper resistance array, the copper lead-in wire two ends of each equal in length are respectively arranged with a voltage leading-out ends mouth 3.Distance between two voltage leading-out ends mouths on every copper lead-in wire that the voltage leading-out ends mouth arranged equates.The distance of the voltage extension line on every flat copper lead-in wire (being copper resistance) is the same, and five copper resistances are on same circuit, thereby the size of current of five resistance of flowing through is the same.The voltage swing that flows through five resistance by measurement compares, if the voltage of the voltage ratio both sides copper resistance of copper resistance is big in the middle of recording, the resistance of the resistance value ratio both sides copper resistance of copper resistance is big just, because the length of five copper resistances and width and etching depth are just the same, equidistantly arrange side by side between the copper resistance, got rid of the influence of matrix phenomenon, thereby the cross-sectional area of copper resistance is littler in the middle of inferring, the erosion of inter-level dielectric in the CMP process, occurred.
The present invention can be used for electrical measurement copper lead-in wire copper lead-in wire inter-level dielectric after the CMP process and whether produce erosion.The method is simple in structure, and it is little to take chip area, is convenient to embed in the domain, and experiment measuring is convenient.Adopt this electrical method to measure, be not subjected to the influence of line size, can measure entire chip easily, well the homogeneity of proofing chip CMP.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1, a kind ofly is used to test the copper lead wire circuit domain structure whether inter-level dielectric produces erosion, it is characterized in that: described copper lead wire circuit domain comprises the copper resistance array that a copper lead-in wire that equated by many width, that uniformly-spaced arrange constitutes, the radical of copper lead-in wire is greater than 3, copper lead-in wire head and the tail are in series in the described copper resistance array, described copper resistance array two ends are respectively arranged with an electric current and draw port, the copper lead-in wire that has three equal in length in the copper resistance array at least, the copper lead-in wire two ends of each equal in length are respectively arranged with a voltage leading-out ends mouth.
2, as claimed in claim 1 being used to tested the copper lead wire circuit domain structure whether inter-level dielectric produces erosion, it is characterized in that: the distance between two voltage leading-out ends mouths on every copper lead-in wire that the voltage leading-out ends mouth arranged equates.
3, as claimed in claim 2 being used to tested the copper lead wire circuit domain structure whether inter-level dielectric produces erosion, it is characterized in that: described copper resistance array is made of 13 copper lead-in wires.
4, as claimed in claim 3 being used to tested the copper lead wire circuit domain structure whether inter-level dielectric produces erosion, it is characterized in that: the copper lead-in wire that 5 equal in length are arranged in the described copper resistance array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008102388139A CN101424654A (en) | 2008-12-02 | 2008-12-02 | Copper lead wire circuit board diagram structure for testing erode of interlayer medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008102388139A CN101424654A (en) | 2008-12-02 | 2008-12-02 | Copper lead wire circuit board diagram structure for testing erode of interlayer medium |
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| CN101424654A true CN101424654A (en) | 2009-05-06 |
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| CNA2008102388139A Pending CN101424654A (en) | 2008-12-02 | 2008-12-02 | Copper lead wire circuit board diagram structure for testing erode of interlayer medium |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044526B (en) * | 2009-10-16 | 2014-05-21 | 无锡华润上华半导体有限公司 | Electromigration monitoring structure |
| CN105891265A (en) * | 2015-04-29 | 2016-08-24 | 业成光电（深圳）有限公司 | Circuit detecting device and method and circuit to which circuit detecting device and method are applied |
| CN107228884A (en) * | 2017-06-09 | 2017-10-03 | 中国地质大学（武汉） | The laboratory testing rig and method of a kind of multi-electrode test soil body resistivity |
| US20210242179A1 (en) * | 2020-02-05 | 2021-08-05 | Fuji Electric Co., Ltd. | Power semiconductor module |
-
2008
- 2008-12-02 CN CNA2008102388139A patent/CN101424654A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102044526B (en) * | 2009-10-16 | 2014-05-21 | 无锡华润上华半导体有限公司 | Electromigration monitoring structure |
| CN105891265A (en) * | 2015-04-29 | 2016-08-24 | 业成光电（深圳）有限公司 | Circuit detecting device and method and circuit to which circuit detecting device and method are applied |
| CN107228884A (en) * | 2017-06-09 | 2017-10-03 | 中国地质大学（武汉） | The laboratory testing rig and method of a kind of multi-electrode test soil body resistivity |
| CN107228884B (en) * | 2017-06-09 | 2019-05-31 | 中国地质大学（武汉） | A kind of laboratory testing rig and method of multi-electrode test soil body resistivity |
| US20210242179A1 (en) * | 2020-02-05 | 2021-08-05 | Fuji Electric Co., Ltd. | Power semiconductor module |
| US11929354B2 (en) * | 2020-02-05 | 2024-03-12 | Fuji Electric Co., Ltd. | Power semiconductor module |
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Application publication date: 20090506 |