CN101425505B - Circuit layout construction for measuring whether concave falls are generated by copper wire - Google Patents
Circuit layout construction for measuring whether concave falls are generated by copper wire Download PDFInfo
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- CN101425505B CN101425505B CN2008102388143A CN200810238814A CN101425505B CN 101425505 B CN101425505 B CN 101425505B CN 2008102388143 A CN2008102388143 A CN 2008102388143A CN 200810238814 A CN200810238814 A CN 200810238814A CN 101425505 B CN101425505 B CN 101425505B
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Abstract
The invention discloses a circuit domain structure for measuring whether a copper lead wire generates a concave pit. The circuit domain structure comprises a group of independent copper lead wire cross unit arrays. The independent cross unit array is composed of at least two mutually-independent cross units; and each independent cross unit is composed of a copper lead wire with an equiarm cross structure. The invention can be used for electrically measuring whether the copper lead wire generates the concave pit during the CMP process. The invention has simple structure, small occupied domain area, and convenient laboratory measurement, and is conveniently embedded in the domain. The measurement can not be influenced by the dimension of a line by adopting the electrical method, thereby the whole chip can be conveniently measured, and the uniformity of the CMP of the chip can be better verified.
Description
Technical field
The present invention relates to a kind of semiconductor device circuit domain structure, particularly a kind ofly be used to measure the copper lead-in wire and whether produce the circuit layout construction in matrix hole.
Background technology
Along with the raising of manufacturing process, constantly the reducing of device size, interconnection line postpones to become to influence the entire circuit bottleneck of performance.Postpone in order to reduce interconnection line, adopt the littler copper of resistivity as metal lead wire.And in the multilayer wiring stereochemical structure, guarantee that every layer can both reach the key that leveling is the realization multilayer wiring, be one of generally acknowledged preferred plan in the whole world and adopt CMP (CMP (Chemical Mechanical Polishing) process) technology.The copper lead-in wire that adopts Damascus technics to form also needs the unnecessary copper polishing with deposit by CMP, only stays the copper lead-in wire in the raceway groove.These all make copper-connection CMP become and enjoy one of core technology of countries in the world concern in ULSI (the ultra-large scale integration very lagre scale integrated circuit (VLSIC)) manufacture process, but many because of its subject that relates to, technical difficulty is big, Related Mechanism is also treated further research.
In the CMP process of Cu wiring,, caused the out-of-flatness of chip surface because the material with different polishing speeds is polished simultaneously.Two kinds of defectives occur behind the Cu wiring CMP, wherein a kind of defective is called the pit phenomenon, promptly occurs depression in the copper cash, represents size with the difference in height between the minimum point in dielectric layer and the Cu line; Another kind of defective is exactly an erosion, refers to that interlayer dielectric layer is by a jettisoning part after the polishing of high pattern density district, and the dielectric layer height of available design and the difference of actual height are represented.
In ULSI multilayer wiring CMP, the spill problem after the polishing has very big influence to electric properties of devices, rate of finished products.The appearance of copper lead-in wire concave pit has reduced the thickness of metal connecting line, has increased lead resistance, thereby has reduced the reliability of device, causes circuit malfunction thereby make device might produce broken string, produces catastrophic consequence.The spill problem has become the most scabrous technology among the copper wiring CMP, directly has influence on the realization of leveling, and the formation that reduces concave pit is to realizing that complanation is significant.
For the matrix hole of copper lead-in wire formation behind the CMP and the erosion of dielectric layer, generally be to measure with atomic force microscope (AFM), but along with constantly reducing of line thickness, the investigative range of atomic force microscope is quite limited, and the measuring process complexity.
Summary of the invention
The technical issues that need to address of the present invention just are to overcome the defective of the defect test process complexity such as matrix hole that form for copper lead-in wire behind the CMP in the prior art, providing a kind of is used to measure the copper lead-in wire and whether produces the circuit layout construction in matrix hole, it carries out simple electrical measurement by the copper lead-in wire figure to described circuit layout, just can know the performance that finishes the copper lead-in wire of back formation in CMP (Chemical Mechanical Polishing) process.Make after CMP forms the copper lead-in wire, can measure the copper lead-in wire that forms by electrical method and whether produce the matrix hole.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of domain structure of the present invention with electrical testing method copper test lead-in wire concave pit, described domain structure comprises one group of independently copper lead-in wire cross cell array, described independent cross cell array is made of at least 2 separate cross unit, and each independent cross unit is made of the copper lead-in wire of equiarm cross structure.
The copper lead-in wire gash depth of each independent cross unit is identical.
The copper lead-in wire line thickness of each independent cross unit is all inequality.
The copper lead-in wire of each independent cross unit all has four outputs.
The present invention can be used for electrical measurement copper lead-in wire and whether produce concave pit after the CMP process.The method is simple in structure, and it is little to take chip area, is convenient to embed in the domain, and experiment measuring is convenient.Adopt this electrical method to measure, be not subjected to the influence of line size, can measure entire chip easily, well the uniformity of proofing chip CMP.
Description of drawings
Fig. 1 is a structural representation of the present invention.
Fig. 2-1, Fig. 2-2 and Fig. 2-3 are respectively the copper pin configuration schematic diagrames of the different in width of independent cross of the present invention unit.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiment of the present invention is described further in detail below in conjunction with accompanying drawing.
A kind of domain structure of the present invention with electrical testing method copper test lead-in wire concave pit, described domain structure comprises one group of independently copper lead-in wire cross cell array, described independent cross cell array is made of at least 2 separate cross unit, as shown in Figure 1, each independent cross unit is made of the copper lead-in wire 1 of equiarm cross structure.The copper lead-in wire of each independent cross unit all has four outputs 2.The copper lead-in wire gash depth of each independent cross unit is identical.The copper lead-in wire line thickness of each independent cross unit is all inequality.Shown in Fig. 2-1, Fig. 2-2 and Fig. 2-3, described independent cross cell array is made of 3 separate cross unit, and the copper wire widths is respectively n1, n2 and n3.Wherein n1＜n2＜n3＜.For each cross structure four outputs 2 are arranged all, arbitrarily adjacent two ports connect voltage source, measure the electric current that flows through between two other port, and record data calculate the square resistance 3 of the copper lead-in wire of different line thickness according to formula.The voltage that records is compared, if the spill phenomenon do not occur through the lead-in wire of the copper behind the CMP, the square resistance that records so should be consistent, not influenced by cross pattern line width.If the square resistance that records reduces along with the width of cross figure and descends, just can judge that the matrix hole has appearred in the copper lead-in wire in the process of CMP.
The present invention can be used for electrical measurement copper lead-in wire and whether produce concave pit after the CMP process.The method is simple in structure, and it is little to take chip area, is convenient to embed in the domain, and experiment measuring is convenient.Adopt this electrical method to measure, be not subjected to the influence of line size, can measure entire chip easily, well the uniformity of proofing chip CMP.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. one kind is used to measure the copper lead-in wire and whether produces the circuit layout construction in matrix hole, it is characterized in that: described circuit layout comprises one group of independently copper lead-in wire cross cell array, described independent cross cell array is made of at least 2 separate cross unit, each independent cross unit is made of the copper lead-in wire of equiarm cross structure, the gash depth of the described copper lead-in wire of each independent cross unit is identical, and the described copper lead-in wire line thickness of each independent cross unit is all inequality.
2. as claimed in claim 1ly be used to measure the copper lead-in wire and whether produce the circuit layout construction in matrix hole, it is characterized in that: the copper lead-in wire of each independent cross unit all has four outputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008102388143A CN101425505B (en) | 2008-12-02 | 2008-12-02 | Circuit layout construction for measuring whether concave falls are generated by copper wire |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008102388143A CN101425505B (en) | 2008-12-02 | 2008-12-02 | Circuit layout construction for measuring whether concave falls are generated by copper wire |
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| Publication Number | Publication Date |
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| CN101425505A CN101425505A (en) | 2009-05-06 |
| CN101425505B true CN101425505B (en) | 2011-10-26 |
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| CN2008102388143A Active CN101425505B (en) | 2008-12-02 | 2008-12-02 | Circuit layout construction for measuring whether concave falls are generated by copper wire |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430263A (en) * | 2001-12-29 | 2003-07-16 | 海力士半导体有限公司 | Method for forming copper lead wire in semiconductor device |
| CN1472794A (en) * | 2002-07-11 | 2004-02-04 | ����ʿ�뵼������˾ | Method for forming copper teading wires in semiconductor device |
| US7399141B2 (en) * | 2004-07-01 | 2008-07-15 | Brice Environmental Services Corporation | System for removing contaminants from soil |
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2008
- 2008-12-02 CN CN2008102388143A patent/CN101425505B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430263A (en) * | 2001-12-29 | 2003-07-16 | 海力士半导体有限公司 | Method for forming copper lead wire in semiconductor device |
| CN1472794A (en) * | 2002-07-11 | 2004-02-04 | ����ʿ�뵼������˾ | Method for forming copper teading wires in semiconductor device |
| US7399141B2 (en) * | 2004-07-01 | 2008-07-15 | Brice Environmental Services Corporation | System for removing contaminants from soil |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2008-144255A 2008.06.26 |
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| CN101425505A (en) | 2009-05-06 |
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Owner name: BEIJING YANDONG MICROELECTRNIC CO.,LTD. Free format text: FORMER OWNER: INST OF MICROELECTRONICS, C. A. S Effective date: 20150710 |
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Effective date of registration: 20150710 Address after: 100015 Beijing city Chaoyang District Dongzhimen West eight room Wanhong No. 2 West Street Patentee after: Beijing Yandong Microelectronic Co., Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Institute of Microelectronics Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |