CN101419956A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN101419956A CN101419956A CN 200810171395 CN200810171395A CN101419956A CN 101419956 A CN101419956 A CN 101419956A CN 200810171395 CN200810171395 CN 200810171395 CN 200810171395 A CN200810171395 A CN 200810171395A CN 101419956 A CN101419956 A CN 101419956A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
In a semiconductor device, a semiconductor chip is connected to a board through an interconnection layer. A plurality of first terminals, a plurality of second terminals and a plurality of third terminals are provided on the board, the interconnection layer and the semiconductor chip, respectively. The second terminals are connected to the first terminals through the board. The third terminals are connected to the second terminals. The interconnection layer is rotatable about a rotation axis perpendicular to an upper surface of the interconnection layer. A first terminal having a specific function out of the first terminals and a third terminal having the specific function out of the third terminals are connected to each other by rotating the interconnection layer.
Description
Technical field
The present invention relates to the shortening during the research and development of cost degradation in the assembling procedure of semiconductor device and semiconductor device.
Background technology
In various electronic equipments such as portable phone and digital camera, require miniaturization and multifunction.Be accompanied by requirement, the height encapsulation technology of the high speed of the processing speed in the dwindling of the size that requirement can corresponding semiconductor device, the semiconductor device and multitube pinization of semiconductor device etc. to so various electronic equipments.Especially, owing to advance dwindling and SOC (system level chip: multitube pinization system on chip) of semiconductor chip size, so need the interval of the pad (terminal) of constriction semiconductor chip, and need be when the assembled semiconductor device, overlap the to each other the pad that is configured to narrow spaced semiconductor chip and the pad on the substrate.
Now, be used in system LSI (lsi levels such as portable phone and digital camera in use more, in the encapsulation of the multilager base plate of the organic material Large Scale Intergration), if make the interval of pad (terminal) of semiconductor chip narrower than existing, pad of overlapping substrate on the pad of the semiconductor chip of the arranged spaced narrow with this then, it is difficult forming wiring like this in substrate.Therefore, in the case, need the higher special substrate of cost.
As means of head it off, think that now effective method is the middle wiring layer by silicon inserter (silicon interposer) etc., connect being connected of 2 such segment structures of substrate and semiconductor chip.Particularly, overlap the to each other and be configured to than the pad of existing narrower spaced semiconductor chip and the pad on the silicon inserter.The stacked pad of pad with semiconductor chip not only is set in the silicon inserter, also is configured to the pad of the arranged spaced wideer than the interval of this pad.The pad of placement substrate overlappingly on the pad of wide arranged spaced.
As another example that uses the silicon inserter, as the spy opens 2001-No. 257307 communiques, owing to increased the stacked semiconductor chip size that may make up, use the silicon inserter as the example of wiring layer again so also exist.Like this, the structure of encapsulation just constitutes the existing structure of encapsulation from so-called by semiconductor chip and substrate, the structure evolution of wiring layer in the middle of appending between semiconductor chip and substrate.
In addition, in semiconductor device, also regulation must satisfy following requirement.
In portable phone etc., adjoint system LSI increases the construction cycle and the cost of software, how to use same semiconductor chip (system LSI) to make multiple semiconductor device (communization of semiconductor chip) and becomes important.Its result and since use same semiconductor chip only change memory span element etc. around the kind or the configuration of parts, so need the function of semiconductor device to have difference.In the case, the configuration of the solder ball in the semiconductor device (the transmission object of signal) changes with the kind of parts or the change interlock of configuration on every side.Past is because few to the requirement of semiconductor device, so when the kind of parts around the change or configuration, open wiring layer in the middle of the use of 2001-No. 257307 communiques etc. than the spy, the wiring that reconfigures substrate is effective.But now, as mentioned above, because the requirement of semiconductor device is progressively increased, so when the kind of parts around the change or configuration, reconfigure in the method for wiring of substrate in what is called, it is corresponding fully to fail.
Summary of the invention
About the communization of semiconductor chip, only there is the configuration (the transmission object of signal) of a solder ball for a semiconductor chip, if the purposes of semiconductor device or function difference then are necessary to make once more substrate.Therefore, for the different substrate of the configuration of making solder ball, uprise, also have elongated such problem of construction cycle of semiconductor device with regard to there being cost.
In addition, in the future, make the substrate communization by multiple semiconductor chip is set on same substrate, its result can think the shortening of construction cycle of the cost degradation of realizing semiconductor device and semiconductor device.But present situation is carried out such technology and also is difficult to.
Implement the present invention in order to solve such problem, use encapsulation, multiple semiconductor chip is connected on the same substrate by on substrate, making the rotation of wiring group layer across 2 segment structures of wiring group layer.
And, under the situation of the little substrate cheaply of the degree of freedom of the layout of using wiring,, can not change the configuration of ball even if in substrate, can reduce lead-in wire, in order to change the configuration of ball, have only the method for using expensive substrate.But, in the present invention, owing to, just can use substrate cheaply by on substrate, making wiring group layer rotate the degree of freedom of the layout that increases wiring.
Semiconductor device of the present invention comprises: substrate, wiring group layer, semiconductor chip, a plurality of the 1st, the 2nd and the 3rd terminals.A plurality of the 1st terminals and wiring group layer are set on the substrate.A plurality of the 2nd terminals are set on the wiring group layer, are connected to the 1st terminal by substrate.In addition, semiconductor chip is set on the wiring group layer, and a plurality of the 3rd terminals are set on the semiconductor chip, be connected to the 2nd terminal.Wiring group layer can be the rotating shaft rotation with the top axle that vertically extends with respect to wiring group layer, by the rotation of wiring group layer, have the 3rd terminal that has specific function in the 1st terminal of specific function and a plurality of the 3rd terminal in a plurality of the 1st terminals and interconnect.
Thus, when the wire laying mode of the substrate that is used for being provided with semiconductor device (for example circuit board) is different, can not make substrate.
In preferred implementation described later, a plurality of the 2nd terminals be configured in the top of wiring group layer or below, constitute the rotation symmetry with the intersection point of reporting to the leadship after accomplishing a task with respect to rotating shaft and wiring group layer; A plurality of the 1st wirings are set in substrate, dispose an end of the 1st wiring, it is symmetrical to make its intersection point of reporting to the leadship after accomplishing a task with respect to rotating shaft and substrate constitute rotation; Dispose an end and the 2nd terminal of interconnective the 1st wiring, so that they are overlapped; The 3rd terminal connects to the 1st different terminal before the rotation of wiring group layer and after the rotation of wiring group layer.
In semiconductor device of the present invention, preferably possess the different multiple substrate of configuration of the 1st terminal, the 3rd terminal before the rotation of wiring group layer and after the rotation of wiring group layer, connects to the 1st different terminal respectively in substrate.
In semiconductor device of the present invention, preferred a plurality of the 1st terminals be set at substrate below, below substrate, be separated into the 1st power supply terminal and the 1st signal terminal; A plurality of the 2nd terminals be set at wiring group layer above, on wiring group layer, be separated into the 2nd power supply terminal and the 2nd signal terminal; Connect the wiring of the 1st signal terminal and the 2nd signal terminal, be separated from each other with the wiring that is connected the 1st power supply terminal and the 2nd power supply terminal.Thus, can easily guide power-supply wiring and signal routing.
In semiconductor device, preferable substrate has a plurality of the 1st wirings that are directed to the 1st terminal from wiring group layer, wiring group layer has a plurality of the 2nd wirings that are directed to the 2nd terminal from semiconductor chip, the 2nd wiring is reported to the leadship after accomplishing a task with a plurality of the 1st wirings respectively, dispose the 2nd terminal respectively with the position of reporting to the leadship after accomplishing a task that a plurality of the 1st wirings are reported to the leadship after accomplishing a task respectively in the 2nd wiring, 1 position of reporting to the leadship after accomplishing a task in the position of reporting to the leadship after accomplishing a task, the 2nd terminal are connected to the 1st wiring.Thus, can change the position that signal is exported below substrate.And, at this position of reporting to the leadship after accomplishing a task, be connected to the 1st wiring if be arranged on the 2nd terminal of the front end of the 2nd long side direction that connects up, just can eliminate the caused noise of open stub in the HW High Way (open stub).
In semiconductor device of the present invention, preferable substrate has a pair of the 1st terminal, and a pair of the 1st terminal is electrically connected mutually, and the 2nd terminal is connected to any 1 of a pair of the 1st terminal of mutual electrical connection.Thus, can change the position that signal is exported below substrate biglyyer.
In semiconductor device of the present invention, a plurality of the 1st wirings preferably are set in substrate, one end of the 1st wiring is separately positioned on the top of substrate and is connected to the 2nd terminal, substrate can be the rotating shaft rotation with the axle with respect to top extension vertically, before the substrate rotation and after the substrate rotation, part in one end of the 1st wiring is overlapping, and the remaining part in the end of the 1st wiring is not overlapping.Thus, even if, also can be electrically connected semiconductor device with respect to the circuit board of wire laying mode complexity.
In semiconductor device of the present invention, preferably there is the zone that the 2nd terminal is not set in the peripheral part on wiring group layer, be provided for connecting respectively the conducting body of the 1st terminal and the 2nd terminal below wiring group layer, the part of regional opposition side is provided for reinforcing the reinforcing conducting body of the intensity of wiring group layer in below wiring group layer.The intensity that can keep thus, wiring group layer.
In semiconductor device of the present invention, preferably possess normal mode, evaluation model, interpretive model.And wiring group layer also has the pad that is used to be connected to the 1st terminal, and H is fixedly connected with pad, the fixedly connected pad of using of L; Under the 1st terminal and the interconnective situation of the 2nd terminal, carry out normal mode, under any pad and the interconnective situation of the 1st terminal of mode switch terminal, carry out any one pattern of evaluation model and interpretive model.In such semiconductor device, can compare complicated parsing and evaluation.
In preferred implementation described later, substrate is a lead frame.
In another preferred implementation more described later, on substrate, vacate a plurality of wiring group of arranged spaced layer mutually, on a plurality of wiring group layers, semiconductor chip is set respectively.
Again in another preferred implementation, comprise a plurality of wiring group layers and a plurality of semiconductor chip in aftermentioned, on substrate on alternately laminated wiring group layer and semiconductor chip.
The invention effect
According to the present invention, by the multiple semiconductor chip of wiring on same substrate, just can have substrate, in addition, by do not change semiconductor chip, change on every side parts the semiconductor device of different purposes just can be provided.Therefore, can realize manufacturing cost cheap of semiconductor device and shorten development time of semiconductor device.
Description of drawings
Fig. 1 is the decomposition view of the relevant semiconductor device of the 1st execution mode.
Fig. 2 (a) is the top view of a mode of the relevant semiconductor device of the 1st execution mode, (b) is the side view of this semiconductor device.
Fig. 3 (a)～(c) is respectively the side view with the different semiconductor device of the semiconductor device shown in Fig. 2 (b).
Fig. 4 is the top view of the another way of the relevant semiconductor device of the 1st execution mode.
Fig. 5 (a) is the bottom view of the wiring group layer in the 2nd execution mode, (b) is the top view with the substrate in the execution mode.
Fig. 6 (a)～(c) is the plane graph of the connected mode of the wiring of the wiring of substrate and wiring group layer in expression the 3rd execution mode.
Fig. 7 is the plane graph of another connected mode of the wiring of the wiring of substrate and wiring group layer in expression the 3rd execution mode.
Fig. 8 is the plane graph of the connected mode of the wiring of the wiring of substrate and wiring group layer in expression the 4th execution mode.
Fig. 9 is the bottom view of a structure of the wiring group layer in expression the 5th execution mode.
Figure 10 is the top view of the substrate in the 5th execution mode.
Figure 11 is the bottom view of another structure of wiring group layer in expression the 5th execution mode.
Figure 12 is the bottom view of a structure of the substrate in expression the 5th execution mode.
Figure 13 is the bottom view of another structure again of the wiring group layer in expression the 5th execution mode.
Figure 14 is the bottom view of another structure of the substrate in expression the 5th execution mode.
Figure 15 is the bottom view of the wiring group layer in the 6th execution mode.
Figure 16 (a) is the top view of the substrate in the 6th execution mode, (b) is to be the top view of the substrate of center when making the substrate Rotate 180 shown in (a) ° with the rotating shaft.
Figure 17 is the bottom view of the wiring group layer in the 7th execution mode.
Figure 18 is the bottom view of the wiring group layer in the 8th execution mode.
Figure 19 is the top view of the relevant semiconductor device of the 9th execution mode.
Figure 20 is the top view of the relevant semiconductor device of the 10th execution mode.
Figure 21 is the side view of the relevant semiconductor device of the 11st execution mode.
Symbol description
100 semiconductor chips, 101 pads (the 3rd terminal)
110 wiring group layers, 111 pad (the 2nd terminal)
111a signal pad (the 2nd signal terminal)
The 111b power supply has pad (the 2nd power supply terminal)
112 wirings (the 2nd wiring), 120 substrates
122 wirings (the 1st wiring), 123 pads (the 1st terminal)
123a signal pad (the 1st signal terminal)
123b power supply pad (the 1st power supply terminal)
160 conducting bodies, 311 pads (the 2nd terminal)
312 wirings (the 2nd wiring), 322 wirings (the 1st wiring)
510 wiring group layers, 512 holding wire
514 power lines, 520 substrates
523 pads (the 1st terminal), 610 wiring group layers
620 substrates, 624 signals pad (the 1st signal terminal)
629 power supplys pad (the 1st power supply terminal)
710 wiring group layers, 711 pseudo-pad
760 reinforce the conducting body 810 wiring group layers of usefulness
Embodiment
Below, with reference to accompanying drawing, embodiments of the present invention are described.Have again, exist and give identical symbol, omit the situation of explanation identical key element.In addition, in the formation of accompanying drawing, in each accompanying drawing, thickness separately and length etc. are different with the shape of reality.And, about the connection electrode of semiconductor chip, splicing ear, wiring figure and the through hole (via) etc. of substrate, omit its part, adopt easy illustrated number, and adopt easy illustrated shape.
(the 1st execution mode)
Use Fig. 1, Fig. 2 A～Fig. 2 B, Fig. 3 A～Fig. 3 C and Fig. 4, the semiconductor device in the 1st execution mode of the present invention is described.
Fig. 1 is the decomposition view of the relevant semiconductor device of present embodiment.Fig. 2 A is the top view of the relevant semiconductor device of present embodiment, and Fig. 2 B is the side view of the relevant semiconductor device of present embodiment.Fig. 3 A～Fig. 3 C is respectively the side view with the different semiconductor device of the semiconductor device shown in Fig. 2 B.Fig. 4 be by with vertically extend with respect to wiring group layer the axle be rotating shaft, rotate wiring group layer from the state of Fig. 2 A, change the top view of semiconductor device of state of the transmission object of signal beyond power supply signal and the power supply signal (following " signal of power supply signal " abbreviated as " signal ").
At first, the symbol of key diagram 1, Fig. 2 A～Fig. 2 B, Fig. 3 A～Fig. 3 C and Fig. 4.
The 100th, semiconductor chip, the 101st, be configured in the pad (the 3rd terminal) on the semiconductor chip 100, in pad 101, contain signal with pad and power supply pad.
The 110th, wiring group layer.111 are arranged on the pad (the 2nd terminal) of wiring group layer 110, connect wiring group layer 110 be configured in wiring group layer 110 below, have signal with pad (the 2nd signal terminal) and power supply usefulness pad (the 2nd power supply terminal).The 112nd, be directed to the wiring (the 2nd wiring) of pad 111 from semiconductor chip 100, be the wiring that is used for sending to pad 111 signals or power supply signal from semiconductor chip 100.One end of wiring 112 is connected to the pad 101 of semiconductor chip 100, and an end of interconnective wiring 112 and the pad 101 of semiconductor chip 100 overlap the to each other configuration.S1 is the rotary middle point of wiring group layer 110, is the rotating shaft of wiring group layer 110 and the point of reporting to the leadship after accomplishing a task above of wiring group layer 110.
The 120th, substrate.123 are arranged on the following pad (the 1st terminal) of substrate 120, are electrically connected to solder ball 170.The 121st, connect the conducting body that substrate 120 is connected to pad 123, the 122nd, be directed to the wiring (the 1st wiring) of pad 123 from wiring group layer 110, be the wiring that is used for sending to pad 123 signals or power supply signal from wiring group layer 110.122a is an end of wiring 122, is connected to the pad 111 of wiring group layer 110, and an end 122a of interconnective wiring 122 and the pad 111 of wiring group layer 110 overlap the to each other configuration.S2 is the rotating shaft of wiring group layer 110 and the point that substrate 120 is reported to the leadship after accomplishing a task, and placement substrate 120 and wiring group layer 110 are so that the rotary middle point S1 of central point S2 and wiring group layer 110 is overlapping.
The 150th, be used to connect the conducting body of an end of the pad 101 of semiconductor chip 100 and the wiring 112 on the wiring group layer 110, the 160th, be used for the conducting body of an end 122a of the pad 111 of connecting wiring group layer 110 and the wiring 122 on the substrate 120, connect wiring group layer 110 and be connected to the following pad 111 that is configured in wiring group layer 110.170 are arranged on the following solder ball of substrate 120.
Have, in present embodiment and following the 2nd to the 11st execution mode, do not limit the material of each parts especially, in addition, as encapsulation, both the encapsulation that can be covered by casting resin also can be the encapsulation that is not covered by casting resin.Even if the encapsulation that encapsulation is covered by casting resin, in order to make diagram clear, the record of also omitting casting resin in the accompanying drawings.
Then, the semiconductor device that present embodiment is relevant is described.
In Fig. 1, the interval of the pad 101 of semiconductor chip 100 is narrower than existing, overlapped, an end 122a of the wiring 122 of the pad 101 of configuring semiconductor chip 100 and substrate 120 is difficult.But in wiring group layer 110, the pad 101 of overlapped, configuring semiconductor chip 100 and 112 the end of connecting up are possible.For this reason, interconnect an end of the wiring 112 of the pad 101 of semiconductor chip 100 and wiring group layer 110, be electrically connected semiconductor chip 100 and wiring group layer 110 by using microprotrusion (microbump).At this, in wiring group layer 110, wiring 112 is designed to radiate wire, so that than the interval of one end, the interval of pad 111 is wideer.Thus, can be on an end 122a of the wiring 122 of substrate 120 with pad 111 overlay configuration of wiring group layer 110.Thus, can be electrically connected semiconductor chip 100 and substrate 120 mutually by wiring group layer 110.
And, in wiring group layer 110, configuration pad 111, so that its top rotary middle point S1 with respect to wiring group layer 110 becomes the rotation symmetry, in substrate 120, laying-out and wiring 122 on substrate 120, so that one end 122a becomes the rotation symmetry with respect to the central point S2 of substrate 120.
In the present embodiment, the pad of wiring group layer 110 111 is that the center is on same circumference and with uniformly-spaced configuration, in addition, the number of establishing pad 111 is 32 with the rotating shaft.Therefore, if being the center with the rotating shaft, per 11.25 ° (=360 °/32) make 110 rotation of wiring group layer, then, just wiring group layer 110 can be electrically connected to substrate 120 because an end 122a of the wiring 122 of the pad 111 of wiring group layer 110 and substrate 120 is overlapped.Thus, as described later, the same pad 101 of semiconductor chip 100 can be connected to wiring group layer 110 and rotate the pad 123 preceding and substrate 120 that the rotation back is different.
Fig. 2 A and Fig. 2 B illustrate the semiconductor device of actual assembled state.For example, " A " of the pad 101 of semiconductor chip 100 is connected to " A ' " of solder ball 170 by conducting body 150, wiring group layer 110, conducting body 160 and substrate 120.
In Fig. 3 A～Fig. 3 C, show side view respectively with the different semiconductor device of the connection status of the connection status of Fig. 2 B semiconductor chip 100 and wiring group layer 110 or wiring group layer 110 and substrate 120.
In Fig. 3 A, from the counter-rotating of the state shown in Fig. 2 B semiconductor chip 100.Particularly, with semiconductor chip 100 counter-rotating, be arranged on wiring group layer 110 below, with the wiring group layer 110 that is provided with semiconductor chip 100 below be arranged on substrate 120 above.
In Fig. 3 B, respectively from counter-rotating semiconductor chip 100 of the state shown in Fig. 2 B and wiring group layer 110.Particularly, wiring group layer 110 and the semiconductor chip 100 that has reversed is set in order below substrate 120.
In Fig. 3 C, from the counter-rotating of the state shown in Fig. 2 B wiring group layer 110.Particularly, semiconductor chip 100 is arranged on the wiring group layer 110 that reversed above, with the wiring group layer 110 that has reversed be arranged on substrate 120 below.
At this, in the present embodiment, even if the structure shown in Fig. 3 A～3C owing to can rise and the identical effect of structure shown in Fig. 2 B, does not just have special problem to produce.
Fig. 4 is that the state from Fig. 2 A is the situation that the center makes 11.25 ° of wiring group layer 110 rotations with the rotating shaft, identical with Fig. 2 A, " A " of the pad 101 of semiconductor chip 100 is connected to solder ball 170 by conducting body 150, wiring group layer 110, conducting body 160 and substrate 120.But, in Fig. 4, different with Fig. 2 A, because the connecting object of " A " of the pad 101 of semiconductor chip 100 changes to " A " from " A ' " of solder ball 170 "; thus signal that sends from " A " of the pad 101 of semiconductor chip 100 or power supply signal be not be sent to be configured in substrate 120 below the solder ball 170 of inclined to one side central authorities, but be sent to the solder ball 170 of the following inclined to one side periphery that is configured in substrate 120.
At this, it is good by the layout decision that the wiring in the wiring of semiconductor device substrate etc. is set that the following inclined to one side central authorities that solder ball 170 is configured in substrate 120 well still are configured in inclined to one side periphery, particularly, the internal layer that also is arranged on circuit board by the top layer that wiring is arranged on circuit board in circuit board etc. decides.
In the present embodiment, from the specific pad 111 of wiring group layer 110 be configured in substrate 120 below the state that is connected of the solder ball 170 of inclined to one side central authorities, be center when making 110 rotation of wiring group layer with the rotating shaft, just can make this pad 111 be connected to the solder ball 170 of the following inclined to one side periphery that is configured in substrate 120.Therefore, no matter be to use the situation of the substrate of the inclined to one side central configuration solder ball 170 below substrate, also be to use the substrate situation of the inclined to one side circumferential arrangement solder ball 170 below substrate, can both use same wiring group layer 110 as substrate 120.Thus, when the wire laying mode in circuit board etc. is different,, when can providing semiconductor device, can also shorten the construction cycle of semiconductor device with low cost even if not making substrate 120 also is fine.
In addition, owing to be that the center just can be changed to the signal of substrate 120 or the transmission object of power supply signal when making 110 rotation of wiring group layer with the rotating shaft, even if so the semiconductor chip 100 different with respect to the configuration of terminal also can use same substrate 120 assembled semiconductor devices.Therefore, because that substrate 120 is become is common, just can realize the shortening of the construction cycle of the cost degradation of semiconductor device and semiconductor device.
In the 1st execution mode, for the purpose of simplifying the description, the situation of using a plate base has been described, but also can have used the different multiple substrate of configuration of pad.Even if use the situation of multiple substrate like this,, also can increase the degree of freedom of the layout of wiring if be that the center makes the rotation of wiring group layer with the rotating shaft.Therefore, under the situation of the little substrate cheaply of the degree of freedom of the layout of using wiring, owing to can increase the degree of freedom of the layout of wiring, so be effective.
(the 2nd execution mode)
In the 2nd execution mode of the present invention, in the wiring group layer in above-mentioned the 1st execution mode, signal terminal and power supply terminal are separated from each other.Therefore, easily layout signal routing and power-supply wiring in wiring group layer.Use the semiconductor device in Fig. 5 A and Fig. 5 B explanation present embodiment.Have, Fig. 5 A is the bottom view of wiring group layer again, and Fig. 5 B is the top view of substrate.
At first, the symbol of key diagram 5A and Fig. 5 B.
In Fig. 5 A, the 210th, wiring group layer, 111a are arranged on the signal pad (the 2nd signal terminal) of wiring group layer 210, and 111b is arranged on the power supply pad (the 2nd power supply terminal) of wiring group layer 210.215 are arranged on the wiring of wiring group layer 210, are the wirings that power supply is compiled with pad 111b.
In Fig. 5 B, the 220th, substrate, 123a are arranged on the signal pad (the 1st signal terminal) of substrate 220, and 123b is arranged on the power supply pad (the 1st power supply terminal) of substrate 220.225 are arranged on the wiring of substrate 220, are the wirings that power supply is compiled with pad 123b.This wiring 225 is also held concurrently and is the pad of the conducting body that is connected to connecting wiring group layer 210 and substrate 220.Have, 121,122 and 123 is described by above-mentioned the 1st execution mode again.
Then, the semiconductor device that present embodiment is relevant is described.
Shown in Fig. 5 A and Fig. 5 B, on wiring group layer 210, signal is separated from each other with pad 111b with pad 111a and power supply.Particularly, in the semiconductor chip in the present embodiment (not shown), power supply terminal all is set at inclined to one side central authorities, and signal terminal all is set at inclined to one side periphery.Thus, in the wiring group layer 210 in the present embodiment, the peripheral partially signalization pad 111a on wiring group layer 210 in view of the above, the inclined to one side central authorities on wiring group layer 210 are provided with power supply pad 111b.
At this moment, preferably use the impedance (impedance) in the thick wiring reduction power-supply wiring, shown in Fig. 5 A, power supply pad 111b are strengthened in the wiring 215 that the central authorities on wiring group layer 210 use the plane to look toroidal.
Even if with substrate 220 that wiring group layer 210 is connected in, signal also is separated from each other with pad 123b with pad 123a and power supply.Particularly, signal is set up the following inclined to one side periphery of substrate 220 with pad 123a, and power supply is set at the following inclined to one side central authorities of substrate 220 with pad 123b.In addition, in order to reduce the impedance in the power-supply wiring, the wiring 225 that toroidal is looked on the plane being set, is that the center makes 210 rotation of wiring group layer, the structure that the impedance of semiconductor device also can not be risen even if substrate 220 is constituted with the rotating shaft.Like this, in the present embodiment, in wiring group layer 210,, in the impedance that can reduce in the power-supply wiring, also make the transfiguration of layout signal routing easy by separation signal pad 111a and power supply pad 111b.
(the 3rd execution mode)
In the 3rd execution mode of the present invention, the configuration of the conducting body by change connecting wiring group layer and substrate is compared with above-mentioned the 1st execution mode, can change the position that signal and power supply signal are exported below substrate.
Use Fig. 6 A～6C and Fig. 7 that the semiconductor device that present embodiment is relevant is described.Fig. 6 A～Fig. 6 C and Fig. 7 are the plane graphs of the amplification of the area B shown in Fig. 2 A.Have, the connected mode of wiring group layer and substrate for lead-in wire bonding (wire bond) connects, also can be flip-chip (filp chip) mode in Fig. 7 in the present invention again.
At first, the symbol among key diagram 6A～Fig. 6 C and Fig. 7.
In Fig. 6 A～Fig. 6 C and Fig. 7,311 are arranged on the pad (the 2nd terminal) of wiring group layer, and the 312nd, be directed to the wiring (the 2nd wiring) of pad 311 from semiconductor chip, be to be used for wiring that signal or power supply signal are sent to pad 311 from semiconductor chip.The 322nd, be directed to the wiring (the 1st wiring) of substrate from wiring group layer, be to be used for wiring that signal or power supply signal are sent from wiring group course substrate.Among Fig. 6 A～Fig. 6 C 360 is the conducting bodies that are used for connection pads 311 and wiring 322, and 340 among Fig. 7 is the leads that are used for connection pads 311 and wiring 322.
In the present embodiment, be arranged on wiring 312 bending on the way of wiring group layer, particularly, in Fig. 6 A～Fig. 6 C, in wiring 312 and wiring 322 zones of reporting to the leadship after accomplishing a task, to positive direction side (right side among Fig. 6 A～Fig. 6 C) bending of X-direction, in Fig. 7 near wiring 322 zone, to positive direction side (right side among Fig. 7) bending of X-direction.At wiring 312 and wiring 322 positions of reporting to the leadship after accomplishing a task, the pad 311 of laying-out and wiring group layer.
In Fig. 6 A, conducting body 360 is connected to the pad 311 that is configured in down the wiring group layer that plays the 2nd row, and wiring 312 is connected with wiring 322, specifically 1-I, 2-II, 3-III, 4-IV, 5-V, 6-*.At this, " I " of " 1 " of " 1-I " expression wiring 312 and wiring 322 interconnects, and " 6 " of " 6-* " expression wiring 312 do not have to be connected with any one of the wiring 322 shown in Fig. 6 A.
In Fig. 6 A and Fig. 6 B, 3 conducting bodies 360 among different position is provided with 6 conducting bodies 360,1-I, 2-IV, 3-II, 4-III, 5-V, the 6-* specifically of being connected of wiring 312 and wiring 322.Like this, in Fig. 6 A and Fig. 6 B, wiring 312 " 2 ", the connecting object that " 3 " reach " 4 " are different.
In Fig. 6 C, put down in writing as above-mentioned the 1st execution mode, be center rotation wiring group layer with the rotating shaft, its result, wiring 312 to the left among the figure to displacement.Wiring 312 is connected with wiring 322, specifically 1-*, 2-III, 3-I, 4-II, 5-IV, 6-V.Like this, the connecting object (present embodiment) that changes wiring 312 by the position that makes above-mentioned the 1st execution mode and change conducting body 360 contrasts, and just can change the position that signal and power supply signal are exported below substrate.Therefore, do not change the wire laying mode in the substrate, just can tackle the requirement of installation base plate etc.
In Fig. 7, if the connecting object of change lead 340 just can access and effect that Fig. 6 A～Fig. 6 C is identical.
(the 4th execution mode)
In the 4th execution mode of the present invention, eliminate in above-mentioned the 3rd execution mode because the noise (noise) that the open short-term (open stub) in the HW High Way causes is realized the raising of the electrical characteristic of semiconductor device.
Use Fig. 8 illustrates the semiconductor device in the present embodiment.At this, Fig. 8 is the amplification view of the area B shown in Fig. 2 A, and 311 among Fig. 8,312,322 and 360 is by shown in above-mentioned the 3rd execution mode.
In Fig. 8, shorten " 2 " in the wiring 312 shown in Fig. 6 A～Fig. 6 C, " I " of " 2 " of connecting wiring 312 and wiring 322.At first, will become " I " that be connected to wiring 322 in " 2 " of wiring 312 of HW High Way, afterwards as described in above-mentioned the 3rd execution mode, will " 2 " wiring 312 in addition and other connect up and 322 be connected.
As a result, if " 4 " of connect up 312 " 2 " and wiring 312 are compared and illustrate, then connect up 312 " 4 " therefore have been subjected to the noise effect of open short-term from further extending forward with the junction of " III " of wiring 322.But,, therefore can cut down open short-term noise because wiring 312 " 2 " is cut off in the junction with " I " of wiring 322.
Like this, because wiring 312 " 2 " is cut off in the junction with " I " of wiring 322, " 2 " of wiring 312 self connection destination becomes and can't change.But because at first preferential " I " with wiring 322 of wiring 312 " 2 " be connected, thus do not need to change the connection destination of 312 " 2 " of connecting up, and can cut down open short-term noise.
(the 5th execution mode)
In the 5th execution mode of the present invention, 1 signal with respect to wiring group layer, have 2 receivers in substrate-side, the position of the conducting body of the wiring by change connecting wiring group layer and substrate can be changed the transmission object of signal widely than the situation of above-mentioned the 1st execution mode.
Use Fig. 9～Figure 14 that the semiconductor device that present embodiment is relevant is described.Have, Fig. 9 is the bottom view of wiring group layer again.Figure 10 is the top view of the substrate that connects of wiring group layer shown in Figure 9.Figure 11 and Figure 12 are respectively the bottom view of the wiring group layer in the variation in the present embodiment and the bottom view of substrate.Figure 13 and Figure 14 are respectively the bottom view of the wiring group layer during in the present embodiment another changes and the bottom view of substrate.
At first, the symbol among key diagram 9～Figure 14.
In Fig. 9, Figure 11 and Figure 13, the 510th, wiring group layer, the 512nd, holding wire, the 514th, power line.On 1 signal line 512, connect a pair of signal with pad 111a, 111a, on a power line 514, connect a pair of power supply pad 111b, 111b.
In Figure 10, the 520th, substrate, 522 are arranged on the top wiring of substrate 520, and 523 are arranged on the following pad (the 1st terminal) of substrate 520, and 524 are arranged on the following wiring of substrate 520.Have again, in pad 523, contain signal with pad and power supply pad.525 and 528 is respectively the wiring that compiles the pad that the power supply on the substrate 520 uses, and holds concurrently to be the pad of the conducting body that is connected to connecting wiring group layer 510 and substrate 520.526 and 527 are arranged on the signal pad of substrate 520 respectively.The 580th, at the conducting body of thickness direction perforation substrate 520.
In Figure 12 and Figure 14, the 520th, substrate, the 571st, the solder ball that holding wire connects, the 572nd, the ball that power line connects, the 573rd, the solder ball of what all unconnected OPEN state.
Then, the semiconductor device that present embodiment is relevant is described.
In wiring group layer 510, as shown in Figure 9, connect a pair of signal with pad 111a, 111a with respect to 1 signal line 512, connect a pair of power supply pad 111b, 111b with respect to a power line 514.Have, signal is not limited to the number of Fig. 9 record with the number of pad 111b with pad 111a and power supply again.
Inclined to one side central authorities on the substrate 520 that is connected to wiring group layer 510, as shown in figure 10, duplex configuration power supply pad compiles the power supply pad that is configured in the inboard with wiring 525, compiles the signal pads that are configured in the outside with wiring 528.In addition, the inclined to one side periphery on substrate 520, duplex configuration signal pad 526,527.
Conducting body 580 connects the thickness direction of substrate 520, and on substrate 520, connecting wiring 522 on conducting body 580, and below substrate 520, connecting wiring 524 on conducting body 580.In wiring 522, connect above-mentioned wiring 525,528 and signal pad 526,527, connection pads 523 in wiring 524.
As shown in figure 10, in substrate 520, the wiring when the wiring when receiving signal from wiring group layer 510 by signal with pad 527 being set and receiving signal from wiring group layer 510 with pad 526 by signal.When with the signal of substrate 520 during with pad 526,527 received signals, no matter which situation, all by connect up 522, conducting body 580 and connect up and 524 send to pad 523.
In addition, as shown in figure 10, in substrate 520,2 cover wirings when the wiring when receiving power supply signal from wiring group layer 510 by wiring 525 being set and receiving these power supply signals by wiring 528.When with wiring during 525,528 received signals, no matter which situation, all by connect up 522, conducting body 580 and connect up and 524 send to pad 523.
Because the top inclined to one side periphery that is configured in wiring group layer 510 all with holding wire 512, the top inclined to one side central authorities that are configured in wiring group layer 510 all with power line 514, so in wiring group layer 510, as shown in figure 11, just conducting body 160 can be configured in the signal pad 111a of a pair of signal, conducting body 160 is configured in the power supply pad 111b of a pair of power supply with inboard among pad 111b, the 111b with the outside among pad 111a, the 111a.At this moment, the configuration of the following solder ball of substrate 520 just as shown in figure 12.
In addition, owing to the top inclined to one side central authorities that the part of holding wire 512 are configured in wiring group layer 510, with the top inclined to one side periphery that is configured in wiring group layer 510 all of power line 514, so can dispose conducting body 160 as shown in figure 13.At this moment, the configuration of the following solder ball of substrate 520 just as shown in figure 14.
At this, the signal that is conceived to wiring group layer 510 uses pad 111a " C " to reach " D ".
In wiring group layer 510 shown in Figure 11, at " C " configuration conducting body 160 of signal with pad 111a, this signal is connected to " C " of the solder ball among Figure 12 with " C ' " of pad 527 by the signal of the substrate among Figure 10 520 with pad 111a ".On the other hand, in wiring group layer 510 shown in Figure 13, at " D " configuration conducting body of signal with pad 111a, this signal is connected to " D " of the solder ball among Figure 14 with " D ' " of pad 527 by the signal of the substrate among Figure 10 520 with pad 111a ".Like this, if the position of the conducting body 160 in the change wiring group layer 510 just can provide the wiring figures that overlap more.
In addition, the power supply that is conceived to wiring group layer 510 uses pad 111b " E " to reach " F ".
In wiring group layer 510 shown in Figure 11, at " E " configuration conducting body 160 of power supply with pad 111b, this power supply is connected to " E ' " of pad 111b by the wiring among Figure 10 525 and is arranged on zone shown in Figure 12 " E " " solder ball.On the other hand, in wiring group layer 510 shown in Figure 13, at " F " configuration conducting body 160 of power supply with pad 111b, this power supply is connected to " F ' " of pad 111b by the wiring among Figure 10 528 and is arranged on zone shown in Figure 14 " F " " solder ball.
Like this, in the present embodiment, compare with above-mentioned the 1st execution mode, though the wiring in the substrate 520 complicates, but it is different with above-mentioned the 1st execution mode mode, because can change widely from the position of the signal of substrate 520 outputs, so even if the wire laying mode complexity in the circuit board etc., also can be corresponding.
(the 6th execution mode)
In the 6th execution mode of the present invention, different with above-mentioned the 1st execution mode, only change the specific signal wiring.Use the relevant semiconductor device of Figure 15, Figure 16 A and Figure 16 B explanation present embodiment.Have, Figure 15 is the bottom view of wiring group layer again, and Figure 16 A and Figure 16 B are the top views of substrate, is that the center just becomes the substrate shown in Figure 16 B when making the substrate Rotate 180 ° of Figure 16 A record with the rotating shaft.
At first, symbol among Figure 15, Figure 16 A and Figure 16 B is described.
In Figure 15, the 610th, wiring group layer, the 612nd, holding wire, 111,111a, 111b and 160 be by putting down in writing in above-mentioned the 1st execution mode.At this, signal pad 111a though be set at the first half above the wiring group layer 610 in Figure 15, also can be any setting on wiring group layer 610, can be just passable for the setting that is connected to the 1st terminal in the substrate.
In Figure 16 A and Figure 16 B, the 620th, substrate.The 621st, the signal pad, the 622nd, signal routing, the 623rd, the conducting body, 624 are arranged on the following signal pad (the 1st signal terminal) of substrate 620.Signal is connected to signal pad 624 with pad 621 by signal routing 622 and conducting body 623.The 626th, the conducting body, the 627th, power-supply wiring, 629 are arranged on the following power supply pad (the 1st power supply terminal) of substrate 620.631 and 632 are arranged on the power-supply wiring of substrate 620 respectively, and also holding concurrently is the pad that is connected to the conducting body of connecting wiring group layer 610 and substrate 620.Though power-supply wiring 631,632 is connected to power supply with pad 629, owing to different at power-supply wiring 631 and power-supply wiring 632 current potentials, so power-supply wiring 631 and power-supply wiring 632 are separated from each other by conducting body 626 and power-supply wiring 627.
In the wiring group layer 610 in the present embodiment, as shown in figure 15, on one when signal is set at 2 distributing line group layers 610 top with pad 111a, be configured in the inclined to one side periphery above this.In addition, power supply is configured in the top inclined to one side central authorities of wiring group layer 610 with pad 111b, and corresponding different current potential is divided into the configuration of 2 positions.The power supply that is configured in the upside among Figure 15 is connected to VDD with pad group 614, and the power supply that is configured in the downside among Figure 15 is connected to VSS with pad group 616.
In the substrate 620 in the present embodiment, shown in Figure 16 A and Figure 16 B, the inclined to one side central configuration power-supply wiring 631,632 on substrate 620, the inclined to one side circumferential arrangement signal pad 621 on substrate 620.The power-supply wiring 631 that is configured in the upside shown in Figure 16 A is connected to the power supply pad of the central side that is configured in substrate 620, and the power-supply wiring 632 that is configured in the downside shown in Figure 16 A is connected to the power supply pad of the perimeter sides that is configured in substrate 620.And, in substrate 620, remove that to be connected to power supply from power-supply wiring 631,632 not in the know with the cloth of the wiring of pad, be that the center just becomes the H zone when making the G zone Rotate 180 shown in Figure 16 A ° with the rotating shaft.
Use wiring group layer 610 and substrate 620 in the present embodiment to make under the situation of semiconductor device, at first, laying-out and wiring group layer 610 on the substrate shown in Figure 16 A 620 is that the center makes 610 rotation of wiring group layer so that become best wiring figure with the rotating shaft.Be that the anglec of rotation of center when making 610 rotation of wiring group layer is necessary for more than 0 ° less than 90 ° with the rotating shaft.The anglec of rotation is more than 90 ° the time, because the power supply of wiring group layer 610 will be connected to the power-supply wiring 631 and power-supply wiring 632 both sides of substrate 620 with pad group 614, the power supply of wiring group layer 610 will be connected to the power-supply wiring 631 and power-supply wiring 632 both sides of substrate 620 with pad group 616, so will produce short circuit with pad 614 and power supply between with pad 616 at power supply.On the other hand, when the anglec of rotation during less than 90 °, because the power supply of wiring group layer 610 is connected to the power-supply wiring 631 of substrate 620 and any one of power-supply wiring 632 with pad group 614, the power supply of wiring group layer 610 is connected to another of the power-supply wiring 631 of substrate 620 and power-supply wiring 632 with pad group 616, thus can by power-supply wiring 631,632 be suppressed at power supply with pad group 614 and power supply with producing short circuit between the pad group 616.
Then, be that the center is when making substrate 620 Rotate 180s shown in Figure 16 A ° with the rotating shaft, just shown in Figure 16 B, exchange power-supply wiring 631 and power-supply wiring 632 can exchange the power supply that becomes the wiring of Figure 15 group layer 610 is used pad (the 1st power supply terminal) with the power supply of the substrate 620 of the connecting object of pad group 614,616 position.Certainly, the signal pad of wiring group layer 610 by point symmetry ground configuration, even if its Rotate 180 ° also can not changed, can only exchange the configuration of VDD and VSS.
In the present embodiment, as mentioned above, be the center with the rotating shaft, make wiring group layer 610 rotation, become best wiring figure after, can not change the configuration of the holding wire in the substrate 620 and the configuration of only changing power line.Therefore, in the present embodiment, compare with above-mentioned the 1st execution mode, even if the wire laying mode complexity in the circuit board etc., also can be corresponding fully.
Have again, in the present embodiment,,, also can access same effect even if only the specific signal line is under the asymmetrical situation though, distinguish with holding wire and power line in order to illustrate.
In addition, the anglec of rotation of substrate is not defined as 180 °.
(the 7th execution mode)
In the 7th execution mode of the present invention, change the shape of the wiring group layer in above-mentioned the 1st execution mode.Use Figure 17 that the semiconductor device that present embodiment is relevant is described.Have, Figure 17 is the bottom view of the wiring group layer in the present embodiment again.
Symbol among Figure 17 is described.In Figure 17, the 710th, wiring group layer, the 711st, pseudo-pad (dummypad), the 760th, be used to reinforce the conducting body of the reinforcing usefulness of wiring group layer.111,111a, 111b, 160 and 215 any one all by putting down in writing in above-mentioned the 1st execution mode.
In Figure 17, the flat shape of wiring group layer 710 is quadrangles.When (dicing or die cutting) makes the such situation of wiring group layer 710 if consider to rule, think that the flat shape of wiring group layer 710 is than more preferably quadrangle of circle.
Usually, the flat shape of wiring group layer is under the dimetric situation, as putting down in writing in above-mentioned the 1st execution mode, if pad is disposed in the top central point rotation with respect to wiring group layer symmetrically, then in zone (hereinafter referred to as " landless zone ") that dimetric 4 dihedrals become not dispose pad.In the landless zone, owing to do not dispose pad, so the conducting body that is connected to this pad is not set.Thus, if become such landless zone at dimetric 4 dihedrals, when then injecting underfilling (under fill) between wiring group layer and substrate, the balance in the zone beyond landless zone and the landless zone will degenerate, and has the worry that produces hole (void).In addition,, then there is the situation of the intensity can not keep wiring group layer, can exists the reliability of semiconductor device to be lower than the worry of benchmark if become such landless zone at dimetric 4 dihedrals.
Therefore, in the wiring group layer 710 in the present embodiment, 4 jiaos on wiring group layer 710 are provided with pseudo-pad 711, are provided for reinforcing the reinforcing conducting body 760 of each wiring group layer on this pseudo-pad 711.Thus, be under the situation of dimetric wiring group layer even if use flat shape as wiring group layer 710, also can keep the reliability of semiconductor device.
(the 8th execution mode)
In the 8th execution mode of the present invention, the special terminals in the wiring group layer of putting down in writing for above-mentioned the 1st execution mode is appended the fixing and fixing function of L (low) of H (high).Use Figure 18 that the semiconductor device that present embodiment is relevant is described.Have, Figure 18 is the bottom view of the wiring group layer in the present embodiment again.
Symbol among Figure 18 is described.In Figure 18, the 810th, wiring group layer, the 811st, mode switch terminal, the 812nd, holding wire.111,111a, 111b, 160,215,711 and 760 are by putting down in writing in above-mentioned the 1st execution mode.
In the present embodiment, utilize that gap (in Figure 18, the gap of the bottom right of wiring group layer 810) in wiring group layer 810 following can H be fixed, L fixes 3 signal line, set so like this.Having, in Figure 18, is the wiring group layer of 4 dihedrals though use flat shape as wiring group layer 810 again, does not limit the flat shape of wiring group layer 810 especially.
In the present embodiment, in semiconductor chip, be provided for importing the terminal (mode switch terminal) (not shown) of interpretive model and evaluation model.This mode switch terminal has 3 terminals, fixes or the combination of L when fixing each terminal just can switch mode by H.
This mode switch terminal also is set in wiring group layer 810.In wiring group layer 810, pad, the pad of the fixedly connected usefulness of H and 3 kinds of pads of pad 811,811,811 of the fixedly connected usefulness of L that ball connects usefulness are set, are configured in ball by conducting body 160 and are connected the pad of usefulness, the pad of the fixedly connected usefulness of H or any pad of pad of the fixedly connected usefulness of L and just can determine pattern connecting wiring group layer 810 and substrate.Do not use pad if do not need ball to connect, even if it is then open a way, also out of question.Pad, the pad of the fixedly connected usefulness of H and the pad of the fixedly connected usefulness of L that ball connects usefulness are fixed on H or L by high resistance, when pad all be the state of opening a way arbitrarily, just shift to normal mode, so set.
Using the situation of semiconductor device in normal mode, put down in writing like that as above-mentioned the 1st execution mode etc., is that the center rotates wiring group layer 810 to change connecting object with the rotating shaft.When in evaluation model and interpretive model, using semiconductor device, is that the center does not make 810 rotation of wiring group layer be fixed on angle shown in Figure 180 with the rotating shaft, the configuration of the conducting body 160 by change connecting wiring group layer 810 and substrate just can switch to a plurality of patterns such as evaluation model 1, evaluation model 2, interpretive model 1 and interpretive model 2.Thus, more complicated parsing and evaluation become possibility, can cut down the man-hour of resolving and estimating.
(the 9th execution mode)
In the 9th execution mode of the present invention, the substrate that above-mentioned the 1st execution mode is put down in writing replaces to lead frame (leadframe).Use Figure 19 that the semiconductor device that present embodiment is relevant is described.Have, Figure 19 is the top view of the relevant semiconductor device of present embodiment again.
Symbol among Figure 19 is described.Before the package lead framework, lead-in wire (lead) 923 and pressure pad (die pad) 924 link to each other by framework frame (not shown).But, when the assembling of lead frame, cut off the framework frame with the fixing back of resin.Thus, lead-in wire 923 and pressure pad 924 insulation.921 are arranged on the top pad of lead-in wire 923, and the 922nd, be directed to the wiring of pad 921 from wiring group layer 110.923a is an inner lead, and 923b is an outside lead.The 925th, sealing resin.Have, 100,101,110,111 and 112 by illustrating in above-mentioned the 1st execution mode again.
In the relevant semiconductor device of present embodiment, wiring group layer 110 is set on pressure pad 924, on wiring group layer 110, semiconductor chip 100 is set, expose the outside lead 923b of lead-in wire 923, seal with sealing resin 925 so in this wise.
The structure of the wiring group layer 110 in the present embodiment is because roughly the same with the structure of wiring group layer 110 in above-mentioned the 1st execution mode, so be center when making 110 rotation of wiring group layer with the rotating shaft, just can be for example change the connecting object of pad 111 greatly to " J " from go between 923 " I ".
(the 10th execution mode)
In the 10th execution mode of the present invention, semiconductor device comprises a plurality of wiring group layers.Use Figure 20 that the semiconductor device that present embodiment is relevant is described.Have, Figure 20 is the top view of the relevant semiconductor device of present embodiment again.
In present embodiment related semiconductor device, a plurality of wiring group layers 110,110 are vacated at interval configuration side by side sidewards mutually on substrate 120.Thus, even if under the situation of the different semiconductor chip of the guiding that wiring is set on the same substrate, if utilize the wiring in the wiring group layer 110 layout, utilize the rotation of wiring group layer 110, then can relax not the matching of transmission object of signal.
Have again, in Figure 20,, do not limit the sheet number of wiring group layer especially on substrate though 2 wiring group layers are set.
In addition, even if the structure of lift-launch semiconductor chip is also no problem below wiring group layer.
(the 11st execution mode)
In the 11st execution mode of the present invention, semiconductor device comprises a plurality of wiring group layers and a plurality of semiconductor chip.Use Figure 21 that the semiconductor device that present embodiment is relevant is described.Have, Figure 21 is the side view of the relevant semiconductor device of present embodiment again.
In present embodiment related semiconductor device, on substrate 120 on alternately laminated wiring group layer 110 and semiconductor chip 100.Thus, can be the different wiring group layer rotation of guiding that the center makes wiring respectively with the rotating shaft.Therefore, identical with above-mentioned the 10th execution mode, if utilize the wiring in the wiring group layer 110 layout, utilize the rotation of wiring group layer 110, then can relax not the matching of transmission object of signal.
Have again, in Figure 21,, do not limit the sheet number of wiring group layer especially on substrate though 2 wiring group layers are set.
In addition, even if the structure of lift-launch semiconductor chip is also no problem below wiring group layer.
Industrial utilizability
As described above, even if semiconductor device of the present invention is because of the purposes of semiconductor device The different situation of configuration (the transmission object of signal) of the solder ball in difference and substrate following, also Can use common Substrate manufacture semiconductor device. In addition, the free degree with respect to the guiding of connecting up is little Cheaply substrate, the free degree of the guiding of wiring is improved. Therefore, can realize partly leading The cost degradation of body device also shortens construction cycle of semiconductor device, is applicable to have expensive and open The electronic device field of the portable phone of the problem points that the cycle of sending out length is such or digital camera etc.
Claims (13)
1, a kind of semiconductor device comprises:
Substrate;
Be arranged on a plurality of the 1st terminals on the aforesaid substrate;
Be arranged on the wiring group layer on the aforesaid substrate;
Be arranged on the above-mentioned wiring group layer a plurality of the 2nd terminals that the process aforesaid substrate is connected with above-mentioned the 1st terminal;
Be arranged on the semiconductor chip on the above-mentioned wiring group layer; With
Be arranged on the above-mentioned semiconductor chip, a plurality of the 3rd terminals that are connected with above-mentioned the 2nd terminal,
Above-mentioned wiring group layer can be the rotating shaft rotation with the top axle that vertically extends with respect to above-mentioned wiring group layer,
By the rotation of above-mentioned wiring group layer, have the 3rd terminal that has above-mentioned specific function in the 1st terminal of specific function and above-mentioned a plurality of the 3rd terminal in above-mentioned a plurality of the 1st terminals and interconnect.
2, semiconductor device according to claim 1 is characterized in that,
A plurality of the 1st wirings are set in aforesaid substrate,
Above-mentioned a plurality of the 2nd terminal constitutes rotational symmetric mode with the intersection point of reporting to the leadship after accomplishing a task with respect to above-mentioned rotating shaft and above-mentioned wiring group layer, be configured in the top of above-mentioned wiring group layer or below,,
Dispose an end of above-mentioned the 1st wiring, it is symmetrical to make its intersection point of reporting to the leadship after accomplishing a task with respect to above-mentioned rotating shaft and aforesaid substrate constitute rotation,
Dispose an above-mentioned end and above-mentioned the 2nd terminal of interconnective above-mentioned the 1st wiring, so that they are overlapped,
Above-mentioned the 3rd terminal connects to different above-mentioned the 1st terminal before above-mentioned wiring group layer rotation and after the rotation of above-mentioned wiring group layer.
3, semiconductor device according to claim 1 is characterized in that,
The different multiple substrate of configuration with above-mentioned the 1st terminal,
Above-mentioned the 3rd terminal connects to different above-mentioned the 1st terminal before above-mentioned wiring group layer rotation and after the rotation of above-mentioned wiring group layer.
4, semiconductor device according to claim 1 is characterized in that,
Above-mentioned a plurality of the 1st terminal be set at aforesaid substrate below, and below aforesaid substrate above-mentioned, be separated into the 1st power supply terminal and the 1st signal terminal,
Above-mentioned a plurality of the 2nd terminal be set at above-mentioned wiring group layer above, and on above-mentioned wiring group layer above-mentioned, be separated into the 2nd power supply terminal and the 2nd signal terminal,
Connect the wiring of above-mentioned the 1st signal terminal and above-mentioned the 2nd signal terminal, be separated from each other with the wiring that is connected above-mentioned the 1st power supply terminal and above-mentioned the 2nd power supply terminal.
5, semiconductor device according to claim 1 is characterized in that,
Aforesaid substrate have a plurality of from above-mentioned wiring group layer be directed to above-mentioned the 1st terminal the 1st the wiring,
Above-mentioned wiring group layer have a plurality of from above-mentioned semiconductor chip be directed to above-mentioned the 2nd terminal the 2nd the wiring,
Above-mentioned the 2nd wiring is reported to the leadship after accomplishing a task with above-mentioned a plurality of the 1st wirings respectively,
Dispose above-mentioned the 2nd terminal respectively with the position of reporting to the leadship after accomplishing a task that above-mentioned a plurality of the 1st wirings are reported to the leadship after accomplishing a task respectively in above-mentioned the 2nd wiring, 1 position of reporting to the leadship after accomplishing a task in the above-mentioned position of reporting to the leadship after accomplishing a task, above-mentioned the 2nd terminal is connected with above-mentioned the 1st wiring.
6, semiconductor device according to claim 5 is characterized in that,
At the above-mentioned position of reporting to the leadship after accomplishing a task, above-mentioned the 2nd terminal and above-mentioned the 1st wiring that are arranged on the front end of the above-mentioned the 2nd long side direction that connects up are connected.
7, semiconductor device according to claim 1 is characterized in that,
Aforesaid substrate has a pair of above-mentioned the 1st terminal, and above-mentioned a pair of the 1st terminal is electrically connected mutually,
Above-mentioned the 2nd terminal is connected to any 1 of above-mentioned a pair of the 1st terminal of mutual electrical connection.
8, semiconductor device according to claim 1 is characterized in that,
A plurality of the 1st wirings are set in aforesaid substrate,
One end of above-mentioned the 1st wiring is set at respectively above aforesaid substrate above-mentioned, and is connected to above-mentioned the 2nd terminal,
Aforesaid substrate can be the rotating shaft rotation with the axle with respect to extension vertically above above-mentioned,
Before the aforesaid substrate rotation and after the aforesaid substrate rotation, the part in the above-mentioned end of above-mentioned the 1st wiring is overlapping, and the remaining part in the above-mentioned end of above-mentioned the 1st wiring is not overlapping.
9, semiconductor device according to claim 1 is characterized in that,
There is the zone that above-mentioned the 2nd terminal is not set in peripheral part on above-mentioned wiring group layer above-mentioned,
Below above-mentioned wiring group layer, be provided for connecting respectively the conducting body of above-mentioned the 1st terminal and above-mentioned the 2nd terminal,
With the part of above-mentioned zone opposition side, be provided for reinforcing the reinforcing conducting body of the intensity of above-mentioned wiring group layer in below above-mentioned wiring group layer above-mentioned.
10, semiconductor device according to claim 1,
Possess normal mode, evaluation model, interpretive model,
Above-mentioned wiring group layer also has the pad that is used to be connected to above-mentioned the 1st terminal, and H is fixedly connected with pad, the fixedly connected pad of using of L,
Under above-mentioned the 1st terminal and the interconnective situation of above-mentioned the 2nd terminal, carry out above-mentioned normal mode,
Under any one and the interconnective situation of above-mentioned the 1st terminal of the pad that is used for switch mode, carry out any one in above-mentioned evaluation model and the above-mentioned interpretive model.
11, semiconductor device according to claim 1 is characterized in that,
Aforesaid substrate is a lead frame.
12, semiconductor device according to claim 1 is characterized in that,
Comprise a plurality of above-mentioned wiring group layers and a plurality of above-mentioned semiconductor chip,
On aforesaid substrate above-mentioned, vacate a plurality of above-mentioned wiring group layers of arranged spaced each other,
On above-mentioned a plurality of wiring group layers, above-mentioned semiconductor chip is set respectively.
13, semiconductor device according to claim 1 is characterized in that,
Comprise a plurality of above-mentioned wiring group layers and a plurality of above-mentioned semiconductor chip,
Alternately laminated above-mentioned wiring group layer and above-mentioned semiconductor chip on aforesaid substrate above-mentioned.
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| CN102543923A (en) * | 2010-12-14 | 2012-07-04 | 英飞凌科技股份有限公司 | Semiconductor device and method of manufacture thereof |
| CN110689910A (en) * | 2018-07-05 | 2020-01-14 | 森富科技股份有限公司 | Memory configuration structure |
| WO2022156133A1 (en) * | 2021-01-21 | 2022-07-28 | 长鑫存储技术有限公司 | Package substrate and package structure |
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| JP2013251437A (en) * | 2012-06-01 | 2013-12-12 | Fujitsu Semiconductor Ltd | Semiconductor device |
| KR102032887B1 (en) * | 2012-12-10 | 2019-10-16 | 삼성전자 주식회사 | Semiconductor package and method for routing the package |
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| JPH07502377A (en) * | 1991-12-18 | 1995-03-09 | クロスポイント・ソルーションズ・インコーポレイテッド | Expanded architecture for field programmable gate arrays |
| JP2888755B2 (en) * | 1994-04-28 | 1999-05-10 | 株式会社メガチップス | Semiconductor device |
| JP3591909B2 (en) * | 1995-04-17 | 2004-11-24 | 沖電気工業株式会社 | Termination module |
| JPH1154884A (en) * | 1997-08-06 | 1999-02-26 | Nec Corp | Mounting structure for semiconductor device |
| JP2000156429A (en) * | 1998-07-07 | 2000-06-06 | Taiyo Yuden Co Ltd | Semiconductor package |
| JP2001102479A (en) * | 1999-09-27 | 2001-04-13 | Toshiba Corp | Semiconductor integrated circuit device and manufacturing method thereof |
| JP2001257307A (en) * | 2000-03-09 | 2001-09-21 | Sharp Corp | Semiconductor device |
| JP2003046212A (en) * | 2001-07-27 | 2003-02-14 | Seiko Epson Corp | Electronic device, its manufacturing method, its designing method, circuit board, and electronic equipment |
| JP4160447B2 (en) * | 2003-05-28 | 2008-10-01 | シャープ株式会社 | Electronic component and module, module assembling method, identification method and environment setting method |
| JP4768994B2 (en) * | 2005-02-07 | 2011-09-07 | ルネサスエレクトロニクス株式会社 | Wiring board and semiconductor device |
| JP2006310425A (en) * | 2005-04-27 | 2006-11-09 | Renesas Technology Corp | Electronic apparatus and its manufacturing method |
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2008
- 2008-04-15 JP JP2008105487A patent/JP5548342B2/en not_active Expired - Fee Related
- 2008-10-23 CN CN 200810171395 patent/CN101419956A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543923A (en) * | 2010-12-14 | 2012-07-04 | 英飞凌科技股份有限公司 | Semiconductor device and method of manufacture thereof |
| CN102543923B (en) * | 2010-12-14 | 2016-01-20 | 英飞凌科技股份有限公司 | Semiconductor device and manufacture method thereof |
| CN110689910A (en) * | 2018-07-05 | 2020-01-14 | 森富科技股份有限公司 | Memory configuration structure |
| WO2022156133A1 (en) * | 2021-01-21 | 2022-07-28 | 长鑫存储技术有限公司 | Package substrate and package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009124097A (en) | 2009-06-04 |
| JP5548342B2 (en) | 2014-07-16 |
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