JP2009004528A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2009004528A
JP2009004528A JP2007163408A JP2007163408A JP2009004528A JP 2009004528 A JP2009004528 A JP 2009004528A JP 2007163408 A JP2007163408 A JP 2007163408A JP 2007163408 A JP2007163408 A JP 2007163408A JP 2009004528 A JP2009004528 A JP 2009004528A
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pad
electrode
stitch
semiconductor device
power supply
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JP2007163408A
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Japanese (ja)
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Takafumi Ishii
貴文 石井
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NEC Electronics Corp
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NEC Electronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To realize a facilitation for a design of an internal wiring of an interposer board loading semiconductor chips, a shortening of a wire length, a miniaturization of the interposer board, and a cost reduction. <P>SOLUTION: Electrode pads 22 provided in a semiconductor chip 2 are constituted by an interior pad 22i and an exterior pad 22o. A sub signal pad 22ss electrically connected to a signal pad 22s which is constituted as the exterior pad is provided in an interior region of a power supply pad 22v constituted as the interior pad. Since the power supply pad 22v can be connected with an interior stitch 12i of an interposer board 1 by a conductive wire 4, a configuration of an internal wiring 14 for connecting the interior stitch 12i to a metal bump 13i provided in an interior region on a rear face of the interposer board 1 can be simplified, and a miniaturization of the interposer board 1 and the cost reduction become possible, and a miniaturization of a semiconductor device and the cost reduction can be realized. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体チップをインターポーザ基板に搭載し、当該半導体チップとインターポーザ基板とをワイヤボンディングにより電気接続する構成の半導体装置に関するものである。   The present invention relates to a semiconductor device having a configuration in which a semiconductor chip is mounted on an interposer substrate and the semiconductor chip and the interposer substrate are electrically connected by wire bonding.

半導体装置のパッケージの一つとして、図１及び図２に概略構成を示すように、半導体チップ２を搭載基板としてのインターポーザ基板１の表面上にマウントし、半導体チップ２に設けられた電極パッド２２とインターポーザ基板１のステッチ（接続用電極）１２とを金属ワイヤ４により電気接続した構成が提案されている。なお、半導体チップ２と金属ワイヤ４は封止用の樹脂５によって封止される。この半導体装置は、例えば、ボールグリッドアレイ型パッケージとして構成した場合には、インターポーザ基板１の裏面（ボトム面）に内部配線によって前記ステッチ１２に電気接続される金属パンプ１３を配設しており、この金属バンプ１３を実装基板３に設けた配線電極３２に圧着することにより実装が行われる。   As one of the packages of the semiconductor device, as schematically shown in FIGS. 1 and 2, the semiconductor chip 2 is mounted on the surface of the interposer substrate 1 as a mounting substrate, and the electrode pad 22 provided on the semiconductor chip 2. A configuration has been proposed in which the stitch (connecting electrode) 12 of the interposer substrate 1 is electrically connected by a metal wire 4. The semiconductor chip 2 and the metal wire 4 are sealed with a sealing resin 5. For example, when the semiconductor device is configured as a ball grid array type package, a metal pump 13 that is electrically connected to the stitch 12 by an internal wiring is disposed on the back surface (bottom surface) of the interposer substrate 1. Mounting is performed by pressing the metal bumps 13 to the wiring electrodes 32 provided on the mounting substrate 3.

近年、半導体装置の高集積化、多機能化に伴い、１つの半導体チップに配設する電極パッドの数を増大させる一方で、半導体装置の実装面積の最小化のために半導体チップの微細化が図られており、そのため半導体チップ上における電極パッドの配列として、特許文献１に示すように、電極パッドを内側パッドと外側パッドとの２列に千鳥状に配列したものが提案されている。図５は特許文献１と同じ構成の半導体装置の一例であり、半導体チップ２Ａの内部回路２３の周辺領域に配置した複数の周辺回路（Ｉ／Ｏブロック：入／出力ブロック）２４に対応する複数の電極パッド２２を当該Ｉ／Ｏブロック２３の周囲に配設している。この電極パッド２２は、外周側に配置した外側パッド２２ｏと、その内側に配置した内側パッド２２ｉとで構成しており、これらのパッドをそれぞれ接続配線２６によって対応するＩ／Ｏブロック２４に接続する。このとき互いに隣接するパッドを外側パッド２２ｏと内側パッド２２ｉとに振り分け配置することで、電極パッド２２は周方向の位置が半ピッチ寸法だけずらした千鳥状に配置されることになる。   In recent years, along with the high integration and multi-functionalization of semiconductor devices, the number of electrode pads arranged on one semiconductor chip has been increased, while the miniaturization of the semiconductor chip has been reduced in order to minimize the mounting area of the semiconductor device. Therefore, as an arrangement of electrode pads on a semiconductor chip, as shown in Patent Document 1, an arrangement in which electrode pads are arranged in two rows of an inner pad and an outer pad has been proposed. FIG. 5 shows an example of a semiconductor device having the same configuration as that of Patent Document 1, and a plurality of peripheral circuits (I / O blocks: input / output blocks) 24 arranged in the peripheral region of the internal circuit 23 of the semiconductor chip 2A. The electrode pads 22 are arranged around the I / O block 23. The electrode pad 22 is composed of an outer pad 22o disposed on the outer peripheral side and an inner pad 22i disposed on the inner side, and these pads are connected to the corresponding I / O block 24 by connection wirings 26, respectively. . At this time, by arranging the pads adjacent to each other between the outer pad 22o and the inner pad 22i, the electrode pads 22 are arranged in a zigzag pattern with the circumferential positions shifted by a half pitch dimension.

また、従来のこの種の半導体装置では、図６に半導体チップとインターポーザ基板の一部の拡大平面図を示し、図７に図６のＢ−Ｂ線断面図を示すように、半導体チップ２Ａにおいては電極パッド２２は内側パッド２２ｉの一部で構成したＶＤＤ，ＧＮＤ等の電源パッド２２ｖと、他の内側パッド２２ｉと外側パッドとで構成した信号パッド２２ｓとを備えており、これらのパッドに電気接続するためにインターポーザ基板１の表面には半導体チップ２Ａの各電極パッド２２に対応して内側ステッチ１２ｉと、その外側に配列した外側ステッチ１２ｏとが形成される。そして、内側ステッチ１２ｉを半導体チップ２Ａの外側パッド２２ｏに金属ワイヤ４で接続し、この金属ワイヤ４のループの外側を覆うようなループを形成した別の金属ワイヤ４によって外側ステッチ１２ｏを半導体チップ２Ａの内側パッド２２ｉに接続している。このようにすることで、互いに隣接して内側にループを構成する金属ワイヤ４と外側にループを構成する金属ワイヤ４とが相互接触することが防止でき、両金属ワイヤの電気的な短絡が防止される。
特開２００３−１６３２６７号公報 Further, in this type of conventional semiconductor device, FIG. 6 shows an enlarged plan view of a part of the semiconductor chip and the interposer substrate, and FIG. 7 shows a cross-sectional view taken along line BB of FIG. The electrode pad 22 includes a power supply pad 22v such as VDD, GND, etc. constituted by a part of the inner pad 22i, and a signal pad 22s constituted by another inner pad 22i and an outer pad. In order to connect, an inner stitch 12i corresponding to each electrode pad 22 of the semiconductor chip 2A and an outer stitch 12o arranged on the outer side are formed on the surface of the interposer substrate 1. Then, the inner stitch 12i is connected to the outer pad 22o of the semiconductor chip 2A by the metal wire 4, and the outer stitch 12o is connected to the semiconductor chip 2A by another metal wire 4 that forms a loop that covers the outside of the loop of the metal wire 4. To the inner pad 22i. By doing in this way, it can prevent that the metal wire 4 which comprises a loop inside adjacent to each other, and the metal wire 4 which comprises a loop on the outside can mutually contact, and an electrical short circuit of both metal wires is prevented. Is done.
JP 2003-163267 A

従来の半導体チップでは、前記したように電極パッドは信号パッドと、ＶＤＤ，ＧＮＤ等の電源パッドで構成されるが、半導体チップの内部回路の配置やＩ／Ｏブロックの配置等の設計上の制約により、電源パッドを内側パッドとして設計しなければならないことがある。電源パッドを内側パッドとして設計する理由は、内側に配置した方が電流の供給経路が多く確保でき、結果として少ない電源パッド数で電源（ＶＤＤ，ＧＮＤ）の供給能力を高めることができるためである。図６及び図７の半導体チップ２Ａの場合には、ＶＤＤやＧＮＤ等の電源パッド２２ｖが内側パッド２２ｉの一部として構成されている。そのため、この半導体チップ２Ａをインターポーザ基板１に搭載して電源パッド２２ｖをステッチ１２に対して金属ワイヤ４で電気接続する場合には、外側にループを構成する金属ワイヤ４によって外側ステッチ１２ｏに電気接続することになる。   In the conventional semiconductor chip, as described above, the electrode pad is composed of the signal pad and the power supply pad such as VDD, GND, etc., but there are design restrictions such as the arrangement of the internal circuit of the semiconductor chip and the arrangement of the I / O block. Therefore, the power supply pad may have to be designed as an inner pad. The reason why the power supply pad is designed as the inner pad is that a larger number of current supply paths can be secured by arranging the power supply pad on the inner side, and as a result, the power supply (VDD, GND) supply capability can be increased with a smaller number of power supply pads. . In the case of the semiconductor chip 2A of FIGS. 6 and 7, a power supply pad 22v such as VDD or GND is configured as a part of the inner pad 22i. Therefore, when this semiconductor chip 2A is mounted on the interposer substrate 1 and the power supply pad 22v is electrically connected to the stitch 12 by the metal wire 4, it is electrically connected to the outer stitch 12o by the metal wire 4 constituting the loop on the outside. Will do.

一方、インターポーザ基板１Ａでは、図７に示したように、ボトム面に設けた金属バンプ１３も信号バンプ１３ｓと電源バンプ１３ｖとして構成されているが、信号バンプ１３ｓは数が多数である上に、他のデバイスとの接続配線長を短くするために大部分をインターポーザ基板１Ａの周辺に沿った外側領域の外側バンプ１３ｏとして配置し、電源パンプ１３ｖは図１及び図２に示した実装基板３における配線電極３２の電気容量を稼ぎ、かつ放熱性を高めるために面積を広く設計し易いインターポーザ基板１Ａの中央寄りの内側領域の内側バンプ１３ｉとして配置することが行われている。特に、実装基板３における配線電極３２の設計は当該実装基板３のサイズ、すなわち実装基板３を内蔵する携帯型電子機器の軽薄短小化に大きく影響することになり、実装基板３の小型化を図る意味でも配線電極３２の設計は重要である。そのため、インターポーザ基板１においてそれぞれ対応するステッチ１２と金属バンプ１３を電気接続する内部配線１４Ａは、外側ステッチ１２ｏを内側領域の金属バンプ１３ｉに電気接続し、内側ステッチ１２ｉを外側領域の金属バンプ１３ｏに電気接続することが必要になり、インターポーザ基板１Ａにおける内部配線１４Ａが冗長になるとともに、配線パターンの設計が複雑になる。   On the other hand, in the interposer substrate 1A, as shown in FIG. 7, the metal bumps 13 provided on the bottom surface are also configured as signal bumps 13s and power bumps 13v, but the number of signal bumps 13s is large. In order to shorten the connection wiring length with other devices, most are arranged as outer bumps 13o in the outer region along the periphery of the interposer substrate 1A, and the power supply pump 13v is provided on the mounting substrate 3 shown in FIGS. In order to increase the electric capacity of the wiring electrode 32 and improve heat dissipation, it is arranged as an inner bump 13i in an inner region closer to the center of the interposer substrate 1A that is easy to design with a large area. In particular, the design of the wiring electrode 32 on the mounting board 3 greatly affects the size of the mounting board 3, that is, the light and thin size of the portable electronic device incorporating the mounting board 3, and the mounting board 3 is reduced in size. In terms of design, the design of the wiring electrode 32 is important. Therefore, the internal wiring 14A that electrically connects the corresponding stitch 12 and the metal bump 13 in the interposer substrate 1 electrically connects the outer stitch 12o to the inner region metal bump 13i, and the inner stitch 12i to the outer region metal bump 13o. Electrical connection is required, the internal wiring 14A in the interposer substrate 1A becomes redundant, and the design of the wiring pattern becomes complicated.

例えば、図７に示した例では、インターポーザ基板１Ａの内部配線を第１ないし第４の配線層からなる４層積層配線Ｌ１１，Ｌ１２，Ｌ１３，Ｌ１４として構成しており、同図に太線で示すように、基板表面の第１の配線層Ｌ１１を各ステッチ１２ｉ，１２ｏに接続し、基板ボトム面の第４の配線層Ｌ１４を各金属バンプ１３ｉ，１３ｏに接続し、これら第１及び第４の配線層Ｌ１１，Ｌ１４を第２及び第３の配線層Ｌ１２，Ｌ１３と各配線層の間に形成される第１ないし第３のビアＶ１１，Ｖ１２，Ｖ１３を介して接続することにより、内側ステッチ１２ｉを外周領域の金属バンプ１３ｏ、すなわち信号バンプ１３ｓに接続し、その反対に外側ステッチ１３ｏを内周領域の金属バンプ１３ｉ、すなわち電源バンプ１３ｖや信号バンプ１３ｓに接続する構成を実現している。このように内部配線１４Ａにおいてステッチ１２と金属バンプ１３の内外を交差的に接続することが必要とされているため、内部配線１４Ａを多層配線構造に形成する必要があり、これが要因になってインターポーザ基板１Ａの小型化、低コスト化を図ることが難しいという問題が生じている。   For example, in the example shown in FIG. 7, the internal wiring of the interposer substrate 1A is configured as four-layer stacked wirings L11, L12, L13, and L14 composed of the first to fourth wiring layers, which are indicated by bold lines in FIG. As described above, the first wiring layer L11 on the substrate surface is connected to the stitches 12i and 12o, and the fourth wiring layer L14 on the substrate bottom surface is connected to the metal bumps 13i and 13o. By connecting the wiring layers L11, L14 via the first and third vias V11, V12, V13 formed between the second and third wiring layers L12, L13 and each wiring layer, the inner stitch 12i Is connected to the metal bump 13o in the outer peripheral area, that is, the signal bump 13s, and on the contrary, the outer stitch 13o is connected to the metal bump 13i in the inner peripheral area, that is, the power bump 13v and the signal bump 13s. It realizes the configuration of connecting. As described above, since it is necessary to cross-connect the inside and outside of the stitch 12 and the metal bump 13 in the internal wiring 14A, it is necessary to form the internal wiring 14A in a multi-layer wiring structure, which causes the interposer. There is a problem that it is difficult to reduce the size and cost of the substrate 1A.

本発明の目的はインターポーザ基板の内部配線の設計を容易化し、かつ配線長の短縮化を実現することでインターポーザ基板の小型化、低コスト化を実現した半導体装置を提供することにある。   An object of the present invention is to provide a semiconductor device in which the design of internal wiring of an interposer substrate is facilitated and the length of the interposer substrate is reduced by reducing the wiring length.

本発明は、信号パッドと電源パッドとして構成される複数の電極パッドを有する半導体チップと、表面に半導体チップを搭載するとともに電極パッドに導電ワイヤで電気接続される複数のステッチを有する搭載基板としてのインターポーザ基板とを備え、インターポーザ基板は裏面に信号電極と電源電極を構成する複数の実装電極が配列され、各実装電極が内部配線を介してステッチにそれぞれ電気接続されている半導体装置であって、電極パッドは半導体チップの周縁に沿って配列した内側パッドと、その外側に配列した外側パッドとを備え、内側パッドのうち電源パッドとして構成されている電極パッドの内側領域にサブ電極パッドを備えることを特徴とする。このサブ電極パッドは当該電源パッドの外側に配置されている信号パッドに電気接続されたサブ信号パッドとして構成されることが好ましい。   The present invention is a mounting substrate having a semiconductor chip having a plurality of electrode pads configured as signal pads and power pads, and a plurality of stitches which are mounted on the surface and electrically connected to the electrode pads by conductive wires. An interposer substrate, the interposer substrate is a semiconductor device in which a plurality of mounting electrodes constituting a signal electrode and a power electrode are arranged on the back surface, and each mounting electrode is electrically connected to a stitch via an internal wiring, The electrode pad includes an inner pad arranged along the periphery of the semiconductor chip and an outer pad arranged on the outer side thereof, and a sub electrode pad is provided in an inner region of the electrode pad configured as a power supply pad among the inner pads. It is characterized by. The sub electrode pad is preferably configured as a sub signal pad electrically connected to a signal pad arranged outside the power supply pad.

また、本発明においては、インターポーザ基板に設けたステッチは内側に配列された内側ステッチと、この内側ステッチの外側に配列された外側ステッチを備え、内側ステッチは外側パッドに接続され、外側ステッチは内側パッドに接続され、サブ信号パッドが設けられた箇所では内側ステッチは電源パッドに接続され、外側ステッチはサブ信号パッドに接続される構成とすることが好ましい。ここで、内側領域の実装電極の少なくとも一部で電源電極が形成され、内側領域の実装電極の他の一部と外側領域の実装電極とで信号電極が形成されるようにする。さらに、実装電極のうち、インターポーザ基板の内側領域に設けられた実装電極は内部配線により内側ステッチに接続され、外側領域に設けられた実装電極は内部配線により外側ステッチに接続される構成とする。   In the present invention, the stitch provided on the interposer substrate includes an inner stitch arranged on the inner side and an outer stitch arranged on the outer side of the inner stitch. The inner stitch is connected to the outer pad, and the outer stitch is arranged on the inner side. It is preferable that the inner stitch is connected to the power supply pad and the outer stitch is connected to the sub signal pad at a place where the sub signal pad is provided. Here, the power supply electrode is formed by at least a part of the mounting electrode in the inner region, and the signal electrode is formed by the other part of the mounting electrode in the inner region and the mounting electrode in the outer region. Further, among the mounting electrodes, the mounting electrodes provided in the inner region of the interposer substrate are connected to the inner stitch by the internal wiring, and the mounting electrodes provided in the outer region are connected to the outer stitch by the internal wiring.

本発明の半導体装置によれば、電源供給能力を高めることを目的として電源パッドを内側パッドとして設計されている既存の半導体チップにおいても、半導体チップの電源パッドの内側にサブ電極パッドを配置する設計を追加するだけで、特にサブ電極パッドを電源パッドの外側に配置されている信号パッドに電気接続したサブ信号パッドとして構成することができ、これにより当該サブ信号パッドの外側に配置されることになる電源パッドをインターポーザ基板の内側ステッチに対して導電ワイヤにより接続した構成が実現できる。そのため、インターポーザ基板の裏面に設けた実装電極のうちインターポーザ基板の内側領域に配置した電源電極を内側ステッチに電気接続するための内部配線の短縮化、設計の容易化が可能になり、搭載基板の小型化、低コスト化が可能になり、半導体装置の小型化、低コスト化が実現できる。また、インターポーザ基板の種類に応じて電源パッドの外側に配置されている本来の信号パッドを用いて導電ワイヤでの接続を行うことも可能となる。さらに、サブ信号パッドは本来の半導体チップの電極パッドに対して付加的に形成すればよいので、半導体チップにおける電極パッドの設計を大幅に変更する必要もない。   According to the semiconductor device of the present invention, even in an existing semiconductor chip designed with the power supply pad as an inner pad for the purpose of increasing the power supply capability, the sub-electrode pad is designed to be arranged inside the power supply pad of the semiconductor chip. In particular, the sub-electrode pad can be configured as a sub-signal pad electrically connected to the signal pad arranged outside the power supply pad, thereby being arranged outside the sub-signal pad. A configuration in which the power supply pads to be connected to the inner stitches of the interposer substrate with conductive wires can be realized. Therefore, among the mounting electrodes provided on the back surface of the interposer board, the internal wiring for electrically connecting the power supply electrode arranged in the inner area of the interposer board to the inner stitch can be shortened and the design can be simplified. Miniaturization and cost reduction are possible, and the semiconductor device can be reduced in size and cost. In addition, it is possible to perform connection with a conductive wire using an original signal pad arranged outside the power supply pad in accordance with the type of the interposer substrate. Furthermore, since the sub signal pad may be additionally formed with respect to the electrode pad of the original semiconductor chip, it is not necessary to significantly change the design of the electrode pad in the semiconductor chip.

ここで、実装電極はグリッド状に配列された金属バンプで形成される。実装基板に設けた配線電極に対して金属バンプを圧着することにより半導体装置の実装が可能であり、同じ実装基板に実装する他のデバイスに対して電気接続が行われる。   Here, the mounting electrodes are formed of metal bumps arranged in a grid. The semiconductor device can be mounted by crimping metal bumps to the wiring electrodes provided on the mounting substrate, and electrical connection is made to other devices mounted on the same mounting substrate.

また、半導体チップの内側パッドと外側パッドは千鳥状に配列され、サブ信号パッドは前記内側パッドに対して千鳥状に配列される。各パッドに接続する導電ワイヤが隣接パッド間で短絡し難くなり、特に外側パッドや電源パッドに接続する導電ワイヤを小ループ形状とし、内側パッドやサブ信号パッドに接続する導電ワイヤを大ループ形状として両者の短絡を確実に防止する。   In addition, the inner pads and the outer pads of the semiconductor chip are arranged in a staggered manner, and the sub signal pads are arranged in a staggered manner with respect to the inner pads. Conductive wires connected to each pad are difficult to short-circuit between adjacent pads. Especially, conductive wires connected to outer pads and power supply pads are made into a small loop shape, and conductive wires connected to inner pads and sub signal pads are made into a large loop shape. The short circuit between the two is surely prevented.

また、内側パッド、外側パッド及びサブ信号パッドは同層の金属層で形成される。付加パッドを内側パッドや外側パッドと同一工程で製造でき、半導体チップの製造工程を複雑化することがない。   The inner pad, the outer pad, and the sub signal pad are formed of the same metal layer. The additional pad can be manufactured in the same process as the inner pad and the outer pad, and the manufacturing process of the semiconductor chip is not complicated.

次に、本発明の実施例１を図面を参照して説明する。実施例１の半導体装置は、基本的には図１の平面図と図２の断面図に示すように、インターポーザ基板１に半導体チップ２が搭載されており、この半導体チップ２のシリコン基板２１の表面に形成された電極パッド２２とインターポーザ基板１の絶縁基板１１の表面に形成されたステッチ１２とが金属ワイヤ等の導電ワイヤ４により接続され、封止樹脂５等によって封止されたパッケージ構造として構成される。また、インターポーザ基板１の絶縁基板１１のボトム面には内部配線によってステッチ１２に電気接続された多数の金属バンプ１３がグリッド状（格子状）に配置されており、これらの金属バンプ１３は実装基板３の絶縁基板３１の表面に設けられた配線電極３２に熱圧着等によって接続される。   Next, Embodiment 1 of the present invention will be described with reference to the drawings. The semiconductor device according to the first embodiment basically has a semiconductor chip 2 mounted on an interposer substrate 1 as shown in the plan view of FIG. 1 and the cross-sectional view of FIG. A package structure in which the electrode pads 22 formed on the surface and the stitches 12 formed on the surface of the insulating substrate 11 of the interposer substrate 1 are connected by a conductive wire 4 such as a metal wire and sealed by a sealing resin 5 or the like. Composed. In addition, on the bottom surface of the insulating substrate 11 of the interposer substrate 1, a large number of metal bumps 13 electrically connected to the stitches 12 by internal wiring are arranged in a grid (lattice shape), and these metal bumps 13 are mounted on the mounting substrate. 3 is connected to the wiring electrode 32 provided on the surface of the insulating substrate 31 by thermocompression bonding or the like.

図３は前記半導体チップ２とインターポーザ基板１の詳細を説明するための図１の一部に相当する部分の拡大図、図４は図３のＡ−Ａ線に沿う断面図である。半導体チップ２はシリコン基板２１の中央領域に形成されている内部回路２３の外周を囲むように多数のＩ／Ｏブロック２４が周方向に並んで配列されている。このＩ／Ｏブロック２４は信号を入出力するための信号ブロックや、ＧＮＤ又はＶＤＤ等の電源を入出力するための電源ブロックで構成されている。そして、実施例１ではこれらＩ／Ｏブロック２４の領域上にそれぞれのＩ／Ｏプロック２４に対応する電極パッド２２が配設されている。これらの電極パッド２２の具体的な構造の詳細については図示及び説明を省略するが、例えば広く知られているように、シリコン基板２１に形成されたＩ／Ｏブロック２４を覆う絶縁層上に金属層を積層形成し、この金属層を所要の寸法をした矩形パターンにエッチングし、その上をパッシベーション膜で覆い、このパッシベーション膜に各電極パッドに対応する部分を開口する窓を形成して各電極パッドの導電面を露呈させることによって形成する。   FIG. 3 is an enlarged view of a portion corresponding to a part of FIG. 1 for explaining the details of the semiconductor chip 2 and the interposer substrate 1, and FIG. 4 is a sectional view taken along the line AA of FIG. In the semiconductor chip 2, a large number of I / O blocks 24 are arranged in the circumferential direction so as to surround the outer periphery of the internal circuit 23 formed in the central region of the silicon substrate 21. The I / O block 24 includes a signal block for inputting / outputting a signal and a power supply block for inputting / outputting a power source such as GND or VDD. In the first embodiment, electrode pads 22 corresponding to the respective I / O blocks 24 are disposed on the I / O block 24 area. Although detailed illustration and description of the specific structure of these electrode pads 22 are omitted, for example, as is widely known, a metal is formed on an insulating layer covering the I / O block 24 formed on the silicon substrate 21. Layers are formed, this metal layer is etched into a rectangular pattern having a required dimension, and the metal layer is covered with a passivation film. A window corresponding to each electrode pad is formed in the passivation film to form each electrode. It is formed by exposing the conductive surface of the pad.

各電極パッド２２は前記したように同じ金属層の一部で形成されており、それぞれ対応するＩ／Ｏブロック２４に電気接続されているが、電極パッド２２の高密度配置を実現するために外周パッド２２ｏと内周パッド２２ｉとに振り分けて千鳥状の配置を行っている。そして、この際に半導体チップの設計上の制約により、電源Ｉ／Ｏブロック２４に接続されるＧＮＤパッド又はＶＤＤパッド等の電源パッド２２ｖを内側パッド２２ｉの一部に配置し、その外側に信号パッド２２ｓを配置せざるを得ない場合があることは前述した通りである。このように電源パッド２２ｖを信号パッド２２ｓの内側に配置せざるを得ない領域において、実施例１では電源パッド２２ｖのさらに内側にサブ信号パッドと称する信号パッド２２ｓｓを形成している。ここではＩ／Ｏブロック２４よりも更に内側の内部回路２３の領域上にサブ信号パッド２２ｓｓを形成している。このサブ信号パッド２２ｓｓは、半導体チップ２の製造工程において前記各電源パッド２２ｖや信号パッド２２ｓと同時に形成することが可能である。そして、このサブ信号パッド２２ｓｓはそれぞれ電源パッド２２ｖの外側に配置されている外側パッド２２ｏとしての信号パッド２２ｓに１対１で対応されており、図には表れないが例えば下層の接続配線によって相互に電気接続されている。あるいは、サブ信号パッド２２ｓｓと外側パッド２２ｏとしての信号パッド２２ｓはそれぞれ独自に同じＩ／Ｏブロック２４に電気接続されることで相互に電気接続される。実施例１ではＧＮＤ，ＶＤＤ，ＶＤＤの３つの電源パッド２２ｖの内側領域に４つのサブ信号パッド２２ｓｓを配設し、これら４つのサブ信号パッド２２ｓｓを当該電源パッド２２ｖの外側に配置した４つの信号パッド２２ｓにそれぞれ電気接続されている。   Each electrode pad 22 is formed of a part of the same metal layer as described above, and is electrically connected to the corresponding I / O block 24. However, in order to realize a high-density arrangement of the electrode pads 22, the outer periphery is formed. The pad 22o and the inner peripheral pad 22i are distributed in a staggered manner. At this time, due to restrictions on the design of the semiconductor chip, a power pad 22v such as a GND pad or a VDD pad connected to the power I / O block 24 is disposed in a part of the inner pad 22i, and a signal pad is disposed outside the power pad 22i. As described above, 22s may be inevitably arranged. Thus, in the region where the power pad 22v must be disposed inside the signal pad 22s, in the first embodiment, the signal pad 22ss called a sub signal pad is formed further inside the power pad 22v. Here, the sub signal pad 22 ss is formed in the region of the internal circuit 23 further inside than the I / O block 24. The sub signal pads 22ss can be formed simultaneously with the power supply pads 22v and the signal pads 22s in the manufacturing process of the semiconductor chip 2. Each of the sub signal pads 22ss has a one-to-one correspondence with the signal pad 22s as the outer pad 22o disposed on the outer side of the power supply pad 22v. Is electrically connected. Alternatively, the sub signal pad 22ss and the signal pad 22s as the outer pad 22o are electrically connected to each other by being electrically connected to the same I / O block 24, respectively. In the first embodiment, four sub signal pads 22ss are arranged in the inner region of the three power supply pads 22v of GND, VDD, and VDD, and these four sub signal pads 22ss are arranged outside the power supply pad 22v. Each pad 22s is electrically connected.

一方、インターポーザ基板１は樹脂等からなる絶縁基板１１を主体に構成した積層回路基板として形成されており、その表面の中央領域に設けられた図には表れない半導体チップ２のマウント部を囲むように金属膜を所要のパターンに形成したステッチ１２が設けられている。ステッチ１２はマウント部の周囲に沿って配列された複数のステッチからなる内側ステッチ１２ｉと、この内側ステッチ１２ｉの外周に沿って配列された複数のステッチからなる外側ステッチ１２ｏとで構成される。これらのステッチは信号ステッチ１２ｓと、ＧＮＤやＶＤＤ等の電源ステッチ１２ｖとして構成されるが、特に内側ステッチ１２ｉの一部は電源ステッチ１２ｖとして構成されている。   On the other hand, the interposer substrate 1 is formed as a laminated circuit substrate mainly composed of an insulating substrate 11 made of resin or the like, and surrounds the mount portion of the semiconductor chip 2 that is not shown in the figure provided in the central region of the surface. In addition, a stitch 12 in which a metal film is formed in a required pattern is provided. The stitch 12 includes an inner stitch 12i composed of a plurality of stitches arranged along the periphery of the mount portion, and an outer stitch 12o composed of a plurality of stitches arranged along the outer periphery of the inner stitch 12i. These stitches are configured as signal stitches 12s and power supply stitches 12v such as GND and VDD. In particular, a part of the inner stitch 12i is configured as a power supply stitch 12v.

また、インターポーザ基板１の絶縁基板１１のボトム面（裏面）には、図１に示した実装基板３の配線電極３２に圧着される多数の金属バンプ１３が平面配置でグリッド状に配列されている。これらの金属バンプ１３は信号バンプ１３ｓと、ＧＮＤやＶＤＤ等の電源バンプ１３ｖとして構成されるが、特に電源バンプ１３ｖはインターポーザ基板１の中心寄りの内側領域に配設された金属バンプ１３ｉの一部として配設し、信号バンプ１３ｓは電源バンプ１３ｖ以外の内側領域に配設された金属バンプ１３ｉの他の一部として、及び外側領域に配設された金属バンプ１３ｏとして構成している。   Further, on the bottom surface (back surface) of the insulating substrate 11 of the interposer substrate 1, a large number of metal bumps 13 that are crimped to the wiring electrodes 32 of the mounting substrate 3 shown in FIG. 1 are arranged in a grid pattern in a planar arrangement. . These metal bumps 13 are configured as signal bumps 13 s and power supply bumps 13 v such as GND and VDD. In particular, the power supply bumps 13 v are part of the metal bumps 13 i disposed in the inner region near the center of the interposer substrate 1. The signal bump 13s is configured as another part of the metal bump 13i disposed in the inner region other than the power bump 13v and as the metal bump 13o disposed in the outer region.

そして、前記ステッチ１２と金属バンプ１３は絶縁基板１１の内部配線１４によって相互に電気接続されている。実施例１では前記内部配線１４は第１及び第２の配線層Ｌ１，Ｌ２を積層した２層配線構造に形成されており、第１配線層Ｌ１は絶縁基板１１の表面に形成されて前記ステッチ１２に接続され、第２配線層Ｌ２は絶縁基板１１のボトム面に形成されて表面に前記金属バンプ１３が一体化されている。第１配線層Ｌ１と第２配線層Ｌ２は絶縁基板１１の厚さ方向に貫通するビアＶ１を介して電気接続されている。ここで、内部配線１４により内側ステッチ１２ｉを内周領域に配置された電源バンプ１３ｖを含む金属バンプに接続し、外側ステッチ１２ｏを外周領域の金属バンプ１３ｏに接続しているので、ステッチ１２と金属バンプ１３を接続する内部回路１４においては内外を交差的に接続する必要がなくなり、インターポーザ基板１の内部配線１４を図７に示した従来の４層積層構造から２層構造に簡略化できる。   The stitch 12 and the metal bump 13 are electrically connected to each other by the internal wiring 14 of the insulating substrate 11. In the first embodiment, the internal wiring 14 is formed in a two-layer wiring structure in which the first and second wiring layers L1 and L2 are laminated. The first wiring layer L1 is formed on the surface of the insulating substrate 11 and the stitches are formed. 12, the second wiring layer L2 is formed on the bottom surface of the insulating substrate 11, and the metal bumps 13 are integrated on the surface. The first wiring layer L1 and the second wiring layer L2 are electrically connected through a via V1 penetrating in the thickness direction of the insulating substrate 11. Here, since the inner stitch 12i is connected to the metal bump including the power supply bump 13v arranged in the inner peripheral region by the internal wiring 14, and the outer stitch 12o is connected to the metal bump 13o in the outer peripheral region, the stitch 12 and the metal In the internal circuit 14 for connecting the bumps 13, it is not necessary to connect the inside and the outside in a crossing manner, and the internal wiring 14 of the interposer substrate 1 can be simplified from the conventional four-layer laminated structure shown in FIG.

以上の構成の半導体チップ２とインターポーザ基板１でパッケージを構成する際には、半導体チップ２をインターポーザ基板１のマウント部に接着材やろう材等のマウント材２５によりマウントし、半導体チップ２の各電極パッド２２をインターポーザ基板１の各ステッチ１２にそれぞれ金属ワイヤ４により電気接続する。このとき、内側ステッチ１２ｉを外側パッド２２ｏに接続し、外側ステッチ１２ｏを内側パッド２２ｉに接続するが、外側ステッチ１２ｏに接続する金属ワイヤ４はそのループが内側ステッチ１２ｉと外側パッド２２ｏを接続する金属ワイヤ４のループを覆うような大ループにして接続を行っている。このようにすることで、互いに隣接する金属ワイヤ４の一方は内側にループを形成し、他方は外側にループを形成することになり、両金属ワイヤ４が相互接触することが防止でき、両金属ワイヤの電気的な短絡が防止される。このとき、電源パッド２２ｖの内側にサブ信号パッド２２ｓｓが形成されている箇所では、電源パッド２２ｖの外側に隣接する信号パッド２２ｓに対しては金属ワイヤ４を接続せず、電源パッド２２ｖを内側ステッチ１２ｉに金属ワイヤ４で接続した上で、その外側にループを形成するようにサブ信号パッド２２ｓｓを外側ステッチ１２ｏに金属ワイヤ４で接続する。しかる上で、半導体チップ２や金属ワイヤ４を封止樹脂５により封止する。   When a package is configured with the semiconductor chip 2 and the interposer substrate 1 having the above-described configuration, the semiconductor chip 2 is mounted on the mount portion of the interposer substrate 1 with a mounting material 25 such as an adhesive or a brazing material, The electrode pads 22 are electrically connected to the stitches 12 of the interposer substrate 1 by the metal wires 4 respectively. At this time, the inner stitch 12i is connected to the outer pad 22o, and the outer stitch 12o is connected to the inner pad 22i. The metal wire 4 connected to the outer stitch 12o is a metal whose loop connects the inner stitch 12i and the outer pad 22o. The connection is made in a large loop that covers the loop of the wire 4. By doing so, one of the metal wires 4 adjacent to each other forms a loop on the inner side and the other forms a loop on the outer side, so that the two metal wires 4 can be prevented from contacting each other. An electrical short circuit of the wire is prevented. At this time, in a place where the sub signal pad 22ss is formed inside the power pad 22v, the metal wire 4 is not connected to the signal pad 22s adjacent to the outside of the power pad 22v, and the power pad 22v is stitched inside. After being connected to the metal wire 4 to 12i, the sub signal pad 22ss is connected to the outer stitch 12o with the metal wire 4 so as to form a loop on the outside. Then, the semiconductor chip 2 and the metal wire 4 are sealed with a sealing resin 5.

このようなパッケージ構造を有する半導体装置では、半導体チップ２の内側パッド２２ｉの一部に電源パッド２２ｖが配設され、これに隣接する外側パッド２２ｏに信号パッド２２ｓが形成されている箇所には、電源パッド２２ｖのさらに内側に当該信号パッド２２ｓに電気接続されている、あるいは電気的に等価なサブ信号パッド２２ｓが形成されており、このサブ信号パッド２２ｓｓが金属ワイヤ４によりインターポーザ基板１の外側ステッチ１２ｏに接続され、電源パッド２２ｖは金属ワイヤ４により内側ステッチ１２ｉに接続される。外側ステッチ１２ｏは内部配線１４によってインターポーザ基板１の外側領域の金属バンプ１３ｏに接続されているので、半導体チップ２の信号パッド２２ｓ及びサブ信号パッド２２ｓｓは信号バンプ１３ｓとして外側領域の金属バンプ１３ｏに接続されることになる。また、内側ステッチ１２ｉは内部配線１４によって内側領域の金属バンプ１３ｉに接続されているので、電源パッド２２ｖは電源バンプ１３ｖとして内側領域の金属バンプ１３ｉに接続されることになる。   In the semiconductor device having such a package structure, the power supply pad 22v is disposed on a part of the inner pad 22i of the semiconductor chip 2, and the signal pad 22s is formed on the outer pad 22o adjacent thereto. A sub-signal pad 22s that is electrically connected to or electrically equivalent to the signal pad 22s is formed further inside the power supply pad 22v, and the sub-signal pad 22ss is stitched to the outside of the interposer substrate 1 by the metal wire 4. The power pad 22v is connected to the inner stitch 12i by the metal wire 4. Since the outer stitch 12o is connected to the metal bump 13o in the outer region of the interposer substrate 1 by the internal wiring 14, the signal pad 22s and the sub signal pad 22ss of the semiconductor chip 2 are connected to the metal bump 13o in the outer region as the signal bump 13s. Will be. Further, since the inner stitch 12i is connected to the metal bump 13i in the inner region by the internal wiring 14, the power pad 22v is connected to the metal bump 13i in the inner region as the power bump 13v.

このパッケージ構造の半導体装置の金属バンプ１３を図１及び図２に示したような実装基板３の配線電極３２に圧着して実装を行うと、金属バンプ１３の多数を占める信号バンプ１３ｓはインターポーザ基板１の外側領域に配設されているので、同じ実装基板３に実装される他のデバイスとの接続配線長を短くすることができ、信号伝送路としての配線抵抗を低減し、信号伝送速度を向上して高性能な回路が構成できる。一方、電源パンプ１３ｖはインターポーザ基板１の内側領域に配設されているので、実装基板３のインターポーザ基板１のボトム面に対向する領域での配線電極３２の広面積化が可能になり、電源バンプ１３ｖに接続される配線電極の電気容量を稼ぎ、また放熱性を高めることも可能になる。したがって、実施例１の半導体装置では、実装基板３に要求される信号接続配線の短縮化や電源接続配線の高容量化、高放熱性を満たし、サイズを縮小化して軽薄短小化を図った携帯型電子機器への適用を可能にする一方で、半導体装置を構成するインターポーザ基板１の内部配線１４の積層数を低減して配線設計の容易化や製造の簡略化を図り、インターポーザ基板１の薄型化や低コスト化を実現することができる。   When the metal bumps 13 of the semiconductor device having this package structure are pressure-bonded to the wiring electrodes 32 of the mounting board 3 as shown in FIGS. 1 and 2, the signal bumps 13s occupying the majority of the metal bumps 13 are interposer boards. Since it is disposed in the outer region of 1, the connection wiring length with other devices mounted on the same mounting substrate 3 can be shortened, the wiring resistance as a signal transmission path can be reduced, and the signal transmission speed can be reduced. Improve and configure a high-performance circuit. On the other hand, since the power supply pump 13v is disposed in the inner region of the interposer substrate 1, it is possible to increase the area of the wiring electrode 32 in the region facing the bottom surface of the interposer substrate 1 of the mounting substrate 3, and the power bump It is also possible to increase the electric capacity of the wiring electrode connected to 13v and to improve heat dissipation. Therefore, in the semiconductor device of the first embodiment, the signal connection wiring required for the mounting substrate 3 is shortened, the capacity of the power supply connection wiring is increased, the high heat dissipation is satisfied, the size is reduced, and the mobile phone is reduced in size and thickness. While enabling application to a type electronic device, the number of the internal wirings 14 of the interposer substrate 1 constituting the semiconductor device is reduced to facilitate the wiring design and simplify the manufacturing, thereby reducing the thickness of the interposer substrate 1. And cost reduction can be realized.

実施例１では電源パッドとして、ＧＮＤとＶＤＤの各電極パッドの例を示したが、その他の電源用の電極パッドを内側パッドとして備える半導体チップを搭載した半導体装置についても本発明を同様に適用することが可能である。   In the first embodiment, the GND and VDD electrode pads are shown as power supply pads. However, the present invention is similarly applied to a semiconductor device on which a semiconductor chip having other power supply electrode pads as inner pads is mounted. It is possible.

また、実施例１では内側及び外側の各パッド及びサブ電極パッドからなる電極パッドをＩ／Ｏブロックの上部領域に配設した例を示したが、図５に示した半導体チップのようにＩ／Ｏブロックの外周領域に電極パッドを千鳥状に配置する半導体チップの場合でも、Ｉ／Ｏブロックの外周領域にスペースが確保できる場合、あるいはＩ／Ｏブロック上にスペースが確保できる場合にはこれらのスペースにサブ電極パッドを配置することで本発明が適用できる。   Further, in the first embodiment, an example in which the electrode pads including the inner and outer pads and the sub-electrode pads are arranged in the upper region of the I / O block is shown. However, like the semiconductor chip shown in FIG. Even in the case of a semiconductor chip in which electrode pads are arranged in a staggered manner in the outer peripheral area of the O block, if a space can be secured in the outer peripheral area of the I / O block, or if a space can be secured on the I / O block, these The present invention can be applied by arranging the sub-electrode pads in the space.

本発明の対象となる半導体装置の概略構成を示す平面図である。It is a top view which shows schematic structure of the semiconductor device used as the object of this invention. 図１の概略断面図である。It is a schematic sectional drawing of FIG. 本発明の半導体装置の実施例の図１の一部に相当する部分の拡大図である。FIG. 2 is an enlarged view of a portion corresponding to a part of FIG. 1 of the embodiment of the semiconductor device of the present invention. 図３のＡ−Ａ線に沿う断面図である。It is sectional drawing which follows the AA line of FIG. 半導体チップの電極パッドの千鳥配列を示す概略平面図である。It is a schematic plan view showing a staggered arrangement of electrode pads of a semiconductor chip. 従来の半導体装置の一部の拡大平面図である。It is a one part enlarged plan view of the conventional semiconductor device. 図６のＢ−Ｂ線に沿う断面図である。It is sectional drawing which follows the BB line of FIG.

符号の説明Explanation of symbols

１，１Ａ インターポーザ基板（搭載基板）
２，２Ａ 半導体チップ
３ 実装基板
４ 導電ワイヤ（金属ワイヤ）
５ 封止樹脂
１１ 絶縁基板
１２ ステッチ
１２ｉ 内側ステッチ
１２ｏ 外側ステッチ
１３ 金属バンプ
１３ｉ 内側バンプ
１３ｏ 外側バンプ
１４，１４Ａ 内部配線
２１ シリコン基板
２２ 電極パッド
２２ｉ 内側パッド
２２ｏ 外側パッド
２２ｓ 信号パッド
２２ｖ 電源パッド
２２ｓｓ サブ信号パッド（サブ電極パッド）
２３ 内部回路
２４ Ｉ／Ｏブロック 1,1A interposer board (mounting board)
2,2A Semiconductor chip 3 Mounting substrate 4 Conductive wire (metal wire)
5 sealing resin 11 insulating substrate 12 stitch 12i inner stitch 12o outer stitch 13 metal bump 13i inner bump 13o outer bump 14, 14A internal wiring 21 silicon substrate 22 electrode pad 22i inner pad 22o outer pad 22s signal pad 22v power pad 22ss sub signal Pad (sub electrode pad)
23 Internal circuit 24 I / O block

Claims (8)

信号パッド及び電源パッドとして構成される複数の電極パッドを有する半導体チップと、表面に前記半導体チップを搭載するとともに前記電極パッドに導電ワイヤで電気接続される複数のステッチを有する搭載基板とを備え、前記搭載基板は裏面に信号電極と電源電極を構成する複数の実装電極が配列され、各実装電極が内部配線を介して前記ステッチにそれぞれ電気接続されている半導体装置であって、前記電極パッドは半導体チップの周縁に沿って内側に配列した内側パッドと、その外側に配列した外側パッドとを備え、前記内側パッドのうち電源パッドとして構成されている電極パッドの内側領域にサブ電極パッドを備えることを特徴とする半導体装置。   A semiconductor chip having a plurality of electrode pads configured as a signal pad and a power supply pad; and a mounting substrate having a plurality of stitches mounted on the surface and electrically connected to the electrode pads by conductive wires, The mounting substrate is a semiconductor device in which a plurality of mounting electrodes constituting a signal electrode and a power supply electrode are arranged on the back surface, and each mounting electrode is electrically connected to the stitch via an internal wiring, and the electrode pad is An inner pad arranged inside along a peripheral edge of the semiconductor chip and an outer pad arranged outside thereof are provided, and a sub-electrode pad is provided in an inner region of the electrode pad configured as a power pad among the inner pads. A semiconductor device characterized by the above. 前記サブ電極パッドは前記電源パッドの外側に配置されている信号パッドに電気接続されたサブ信号パッドとして構成されていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the sub electrode pad is configured as a sub signal pad electrically connected to a signal pad arranged outside the power supply pad. 前記ステッチは内側に配列された内側ステッチと、この内側ステッチの外側に配列された外側ステッチを備え、前記内側ステッチは前記外側パッドに接続され、前記外側ステッチは前記内側パッドに接続され、前記サブ信号パッドが設けられた箇所では前記内側ステッチは前記電源パッドに接続され、前記外側ステッチは前記サブ信号パッドに接続されていることを特徴とする請求項１又は２に記載の半導体装置。   The stitch comprises an inner stitch arranged inside and an outer stitch arranged outside the inner stitch, the inner stitch connected to the outer pad, the outer stitch connected to the inner pad, and the sub-stitch 3. The semiconductor device according to claim 1, wherein the inner stitch is connected to the power supply pad and the outer stitch is connected to the sub signal pad at a location where a signal pad is provided. 前記内側領域の実装電極の少なくとも一部で電源電極が形成され、前記内側領域の実装電極の他の一部と外側領域の実装電極とで信号電極が形成されていることを特徴とする請求項３に記載の半導体装置。   The power supply electrode is formed by at least a part of the mounting electrode in the inner region, and the signal electrode is formed by the other part of the mounting electrode in the inner region and the mounting electrode in the outer region. 3. The semiconductor device according to 3. 前記実装電極のうち、前記搭載基板の内側領域に設けられた実装電極は前記内部配線により前記内側ステッチに接続され、外側領域に設けられた実装電極は前記内部配線により前記外側ステッチに接続されていることを特徴とする請求項４に記載の半導体装置。   Among the mounting electrodes, the mounting electrodes provided in the inner region of the mounting substrate are connected to the inner stitch by the internal wiring, and the mounting electrodes provided in the outer region are connected to the outer stitch by the internal wiring. The semiconductor device according to claim 4. 前記実装電極はグリッド状に配列された金属バンプで形成されていることを特徴とする請求項４又は５に記載の半導体装置。   6. The semiconductor device according to claim 4, wherein the mounting electrode is formed of metal bumps arranged in a grid. 前記内側パッドと外側パッドは千鳥状に配列され、前記サブ電極パッドは前記内側パッドに対して千鳥状に配列されていることを特徴とする請求項１ないし６のいずれかに記載の半導体装置。   7. The semiconductor device according to claim 1, wherein the inner pads and the outer pads are arranged in a zigzag pattern, and the sub electrode pads are arranged in a zigzag pattern with respect to the inner pad. 前記内側パッド、外側パッド及びサブ信号パッドは同層の金属層で形成されていることを特徴とする請求項７に記載の半導体装置。

8. The semiconductor device according to claim 7, wherein the inner pad, the outer pad, and the sub signal pad are formed of the same metal layer.

JP2007163408A 2007-06-21 2007-06-21 Semiconductor device Pending JP2009004528A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8811055B2 (en) 2011-09-19 2014-08-19 Samsung Electronics Co., Ltd. Semiconductor memory device
TWI494929B (en) * 2013-06-06 2015-08-01 Winbond Electronics Corp Flash memory and layout method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8811055B2 (en) 2011-09-19 2014-08-19 Samsung Electronics Co., Ltd. Semiconductor memory device
TWI494929B (en) * 2013-06-06 2015-08-01 Winbond Electronics Corp Flash memory and layout method thereof

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