CN101419921A - Chip dimension encapsulation method for image sensor - Google Patents
Chip dimension encapsulation method for image sensor Download PDFInfo
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- CN101419921A CN101419921A CNA2007100473645A CN200710047364A CN101419921A CN 101419921 A CN101419921 A CN 101419921A CN A2007100473645 A CNA2007100473645 A CN A2007100473645A CN 200710047364 A CN200710047364 A CN 200710047364A CN 101419921 A CN101419921 A CN 101419921A
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Abstract
The invention provides a chip scale sealing method of an image sensor. The image sensor comprises a wafer provided with a sensing circuit and an optical element; the scale sealing method comprises: at first, the manufacture of a silicon run-through electrode is carried out on the wafer; then the optical element of the image sensor is prepared on the wafer. The method can effectively solve the problems that the optical element of the image sensor in the traditional chip scale sealing method of an image sensor is easily deformed, polluted or damaged during the forming process of the silicon run-through electrode, ensure the reliability and the stability of the performances of the optical element, improve the depositing temperature of an insulating layer in preparing the silicon run-through electrode, ensure the excellent quality of the insulating layer and finally improve the qualified rate for the chip scale sealing of the image sensor by putting the step of preparing the optical element behind the forming step of the silicon run-through electrode.
Description
Technical field
The present invention relates to the chip scale package field of semiconductor device, relate in particular to a kind of image sensor chip dimension encapsulation method.
Background technology
At present, chip scale package (chip scale packaging) has become the main flow encapsulation technology of consumer electronics product.Chip scale package has merged the very ripe micro fabrication of large scale integrated circuit, makes electronic device more and more microminiaturized, and electronic product is more and more lighter and handier, more and more functional diversities.
Imageing sensor in the common consumption electronic product is charge-coupled device (CCD) transducer or cmos image sensor normally.The encapsulation of this class image sensor chip yardstick all is the sensing circuit part of making imageing sensor on wafer (wafer) usually, realizes being connected of sensing circuit and imageing sensor optical element by silicon through electrode method.The appearance of silicon through electrode (through silicon via) technology makes these imageing sensors can carry out the chip scale package of smaller szie, and the packaging density of imageing sensor is further improved.Silicon through electrode technology generally includes silicon via etch step, insulating barrier depositing step, via bottom opening step, metal electrode formation step etc.
Traditional method all is the optical elements that prepare imageing sensor earlier on wafer, makes the silicon through electrode then.Because optical element is fragile, high-temperature capability is poor, and therefore on the wafer for preparing optical element, the insulating barrier deposition temperature during the silicon through electrode is made is unsuitable too high.The deposition insulating layer material is a silicon oxide material at present, and deposition temperature generally is no more than 200 ℃.The quality of Si oxide insulating barrier is inhomogeneous easily under such temperature range, and is second-rate.The making step of silicon through electrode easily makes optical element distortion or the contaminated and damage that has been produced on the wafer.Thereby the instability that causes the image sensor chip performance, yields reduces.
Summary of the invention
The object of the present invention is to provide a kind of image sensor chip dimension encapsulation method, with the optical element that solves imageing sensor in encapsulation process yielding or be subjected to polluting the problem of damage and silicon connect make in the second-rate problem of insulating barrier of deposit.
To achieve the above object, the chip dimension encapsulation method of imageing sensor of the present invention, described imageing sensor comprise wafer and the optical element with sensing circuit, and this method comprises carries out earlier the making of silicon through electrode on described wafer; The optical element that on wafer, prepares imageing sensor then.
Made the metal crimp solder joint that the silicon through electrode connects on the described wafer.The making of described silicon through electrode comprises that silicon via etch step, insulating barrier depositing step, via bottom are opened step, metal electrode forms step.The temperature range of described insulating barrier deposit comprises 300～400 ℃.Comprise also before the described silicon via etch step that the adding wafer thins, polishing step.Described polishing wafer, thin also to be included in before the step and load silicon substrate on the wafer.Silicon substrate is to load by coating adhesive on wafer in the described loading.
The optical element of described preparation imageing sensor add before the described optical element of preparation remove earlier described on silicon substrate and back load under two steps of silicon substrate.Or the optical element of described preparation imageing sensor adding before the described optical element of preparation remove earlier described on silicon substrate and back load under two steps of silicon substrate.Silicon substrate is by loading at wafer rear coating adhesive under the described loading.
Compared with prior art, the chip dimension encapsulation method of imageing sensor of the present invention is placed on after the step of silicon through electrode formation by the preparation process with optical element, can effectively solve the easily problem of distortion or contaminated damage in the manufacturing process of silicon through electrode of optical element in the conventional image sensor chip dimension encapsulation method, can improve simultaneously insulating barrier deposition temperature in the preparation of silicon through electrode, guarantee the insulating barrier quality, improve the optical element performance reliability and stability, finally guarantee the yields of the chip scale package of imageing sensor.
Description of drawings
By following examples and in conjunction with the description of its accompanying drawing, can further understand the purpose and the characteristics of its invention.Wherein, accompanying drawing is:
Fig. 1 is the flow chart that silicon through electrode of the present invention forms.
Fig. 2 is the preparation process flow chart of imageing sensor optical element of the present invention.
Fig. 3 is another preparation process flow chart of imageing sensor optical element of the present invention.
Fig. 4 is a protective mulch schematic diagram in the image sensor package of the present invention.
Fig. 5 is the whole flow chart of the chip scale package of imageing sensor of the present invention.
Fig. 6 is another schematic flow sheet of chip scale package of imageing sensor of the present invention.
Embodiment
Below will be described in further detail image sensor chip dimension encapsulation method of the present invention.Described imageing sensor comprises the wafer of the sensing circuit part of carrying out the imageing sensor specific function and the optical element of imageing sensor.Chip dimension encapsulation method improves the packaging density of imageing sensor in order to the micro-optical component of realization imageing sensor and being connected of wafer upper sensor sensing circuit part.
Specific embodiments of the invention comprise the making of carrying out the silicon through electrode earlier on the wafer of carrying out imageing sensor sensing circuit part.Usually the making of silicon through electrode comprises that silicon via hole (Through hole) etch step, insulating barrier depositing step, via bottom are opened step, metal electrode forms step.Wherein insulating barrier adopts Si oxide usually in the insulating barrier depositing step.At present for satisfying littler and the chip scale package of video high density transducer more, can before silicon via etch step, carry out thinning and polishing step of wafer, when if the thickness of wafer is thinned to several to dozens of microns, can load silicon substrate (dummy substrate) on the wafer so that carry out the making of silicon through electrode.The loading of last silicon substrate generally is to load by coating adhesive on wafer.
The manufacturing process of above-mentioned silicon through electrode sees also Fig. 1,1 has made the metal crimp solder joint 4 that the silicon through electrode connects on the wafer among Fig. 1, and silicon through electrode manufacturing process comprises: load silicon substrate 3 at coating adhesive 2 on the wafer 1 earlier; Then wafer 1 is thinned, polishes; Last wafer 1 after polishing carries out silicon via hole 5 etchings with particular mask version pattern, the deposit silicon oxide is with isolated wafer 1 and the copper electrode 6 that is about to form again, further, the oxide that etches away the bottom, hole is got through silicon via hole 5 bottoms so that the copper electrode 6 that is about to form forms excellent contact with metal crimp solder joint 4, further, can adopt chemical plating method to form copper electrode 6.So just finished the making of the silicon through electrode on the wafer.
The optical element that on the wafer of the above-mentioned described silicon through electrode of making, prepares imageing sensor then.Preparation process sees also Fig. 2 or Fig. 3, and this step comprises step, coating adhesive 7 that remove to go up the adhesive 2 on silicon substrate 3 and the wafer, loads down silicon substrate 8, preparation optical element 9, removes adhesive 7 and following silicon substrate 8 down as shown in Figure 2.This step as shown in Figure 3 comprises coating adhesive 7, load down silicon substrate 8, remove adhesive 2 and last silicon substrate 3 steps, preparation optical element 9, remove under adhesive 7 and following silicon substrate 8.Loading down among Fig. 2 or Fig. 3, silicon substrate 8 loads by applying adhesive 7 at wafer rear.Adopt the method for Fig. 2 or Fig. 3 all can be implemented in the optical element step for preparing imageing sensor on the wafer.
Generally can be behind the optical element of preparation imageing sensor at the protective layer 10 that on wafer, covers one deck imageing sensor.See also Fig. 4, the protective layer of covering is a glassy layer, and adds isolation pad 11 between the plumbous pressure welding point of protective layer and wafer.
Consult Fig. 5, Fig. 5 is based on the whole flow chart of chip dimension encapsulation method of entire image transducer of optical element preparation process of the imageing sensor of Fig. 2.Consult Fig. 6, the optical element that Fig. 6 is based on the imageing sensor of Fig. 3 is made the flow chart of another image sensor chip dimension encapsulation method of process.
Claims (11)
1, a kind of chip dimension encapsulation method of imageing sensor, described imageing sensor comprise wafer and the optical element with sensing circuit, it is characterized in that, described chip dimension encapsulation method comprises: carry out earlier the making of silicon through electrode on described wafer; The optical element that on wafer, prepares imageing sensor then.
2, chip dimension encapsulation method as claimed in claim 1 is characterized in that: made the metal crimp solder joint that the silicon through electrode connects on the described wafer.
3, chip dimension encapsulation method as claimed in claim 1 is characterized in that: the making of described silicon through electrode comprises that silicon via etch step, insulating barrier depositing step, via bottom are opened step, metal electrode forms step.
4, chip scale package as claimed in claim 3 is characterized in that: described insulating barrier is silicon oxide layer or silicon-nitride layer.
5, chip dimension encapsulation method as claimed in claim 4 is characterized in that: the deposition temperature scope of described insulating barrier comprises 300～400 ℃.
6, chip dimension encapsulation method as claimed in claim 3 is characterized in that: comprise also before the described silicon via etch step that the adding wafer thins, polishing step.
7, chip dimension encapsulation method as claimed in claim 6 is characterized in that: described wafer thins, polishing step also is included in and loads silicon substrate on the wafer before.
8, chip dimension encapsulation method as claimed in claim 7 is characterized in that: silicon substrate is to load by coating adhesive on wafer in the described loading.
9, chip dimension encapsulation method as claimed in claim 6 is characterized in that: the optical element of described preparation imageing sensor is silicon substrate on removal earlier before the described optical element of preparation is described, and the back loads silicon substrate down.
10, chip dimension encapsulation method as claimed in claim 6 is characterized in that: the optical element of described preparation imageing sensor is silicon substrate under loading earlier before the described optical element of preparation, and the described silicon substrate of going up is removed in the back.
11, as claim 9 or 10 described chip dimension encapsulation methods, it is characterized in that: silicon substrate is by loading at wafer rear coating adhesive under the described loading.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100473645A CN101419921A (en) | 2007-10-24 | 2007-10-24 | Chip dimension encapsulation method for image sensor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100473645A CN101419921A (en) | 2007-10-24 | 2007-10-24 | Chip dimension encapsulation method for image sensor |
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| CN101419921A true CN101419921A (en) | 2009-04-29 |
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| CNA2007100473645A Pending CN101419921A (en) | 2007-10-24 | 2007-10-24 | Chip dimension encapsulation method for image sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020103214A1 (en) * | 2018-11-20 | 2020-05-28 | 中芯集成电路（宁波）有限公司上海分公司 | Camera assembly and packaging method therefor, lens module, and electronic device |
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2007
- 2007-10-24 CN CNA2007100473645A patent/CN101419921A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020103214A1 (en) * | 2018-11-20 | 2020-05-28 | 中芯集成电路（宁波）有限公司上海分公司 | Camera assembly and packaging method therefor, lens module, and electronic device |
| JP2021511654A (en) * | 2018-11-20 | 2021-05-06 | 中芯集成電路（寧波）有限公司上海分公司Ｎｉｎｇｂｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｒｐｏｒａｔｉｏｎ（Ｓｈａｎｇｈａｉ Ｂｒａｎｃｈ） | Imaging assembly and its packaging method, lens module, electronic equipment |
| JP6993726B2 (en) | 2018-11-20 | 2022-01-14 | 中芯集成電路（寧波）有限公司上海分公司 | Imaging assembly and its packaging method, lens module, electronic device |
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Open date: 20090429 |