CN101414815A - Linear voltage stabilization delay circuit - Google Patents

Abstract

The invention relates to a liner voltage-regulation time delay circuit which is applied to the power technical field. The circuit comprises a sampling circuit, a compensating pipe connected between an input power and an output load in series and a voltage error amplifier; the sampling circuit is connected with the output terminal of the liner voltage-regulation time delay circuit in parallel, a negative input terminal of the voltage error amplifier is connected with a dividing point of the sampling circuit, an anode thereof is connected with a control terminal of the compensating pipe by a driving resistance R1; a time delay driving circuit is connected between the input terminal of the liner voltage-regulation time delay circuit and the anode of the voltage error amplifier and is used for controlling the formative time of the driving voltage of the compensating pipe, thus leading the formative time of the output voltage to lag behind the input voltage. In the liner voltage-regulation time delay circuit of the invention, not only the output voltage precision is higher, but also harsher time delaying requirement can be met; besides, the output voltage whether have or not is controlled.

Description

A kind of linear voltage stabilization delay circuit

Technical field

The present invention relates to power technique fields, relate in particular to a kind of linear voltage stabilization delay circuit of realizing importing and exporting time-delay.

Background technology

In large-scale power-supply system, multiple power supplies output is realized by a plurality of topological structures usually, promptly be equivalent to form by a plurality of one-board power supplies, the electrifying timing sequence of multichannel output can be realized by the power supply of control corresponding PWM (pulse-width modulation) control chip, and the supply power voltage of the pwm chip of these circuit may be different.The realization of linear power supply has multiple mode, comprises that discrete component is realized and three terminal regulator is realized.In order fundamentally to realize input and the time-delay of exporting, generally adopt discrete component to realize, wherein be divided into tandem linear power supply and parallel linear power supply again; Because of the efficient height of tandem linear power supply than parallel linear power supply, thus commonly used be the tandem linear power supply; The prior art of tandem linear power supply has:

A, the voltage stabilizing didoe power supply of adjusting in parallel, as shown in Figure 1, be that series resistance places between power input and the voltage stabilizing didoe, be used for limiting the electric current that flows to load and diode, the variation of voltage stabilizing didoe compensating load electric current, this pressurizer typically are used in the local voltage adjusting of load less than 200mW; Realize that the time-delay of importing and exporting can only be by strengthening output capacitance, the time constant that output is set up becomes big, thereby is made after the moment that output voltage sets up in the moment that input voltage is set up.

B, single-transistor tandem type linear power supply, as shown in Figure 2, be about to a transistor and be added to basic diode voltage stabilizing circuit, can utilize bipolar transistor to have the advantage of gain, transistor is connected into emitter follower, can provide very big electric current to load under the less situation of the current ratio of voltage stabilizing didoe, this moment, transistor was as an error amplifier basically.When load current increases, the voltage of base stage is improved, transistorized conducting degree also increases, thereby makes voltage be returned to original value.This method can be by selecting transistorized capacity satisfy load and adjust the requirement of voltage loss, but it remains by increasing output capacitance and make output be longer than input settling time settling time, makes lag output set up in input thus.

C, as shown in Figure 3, adjusting pipe is connected between input power supply and the load, come constantly output voltage and stable benchmark voltage to be made comparisons with voltage error amplifier, the difference that draws is amplified many times by voltage error amplifier, error voltage after the amplification is directly controlled the conducting resistance of series connection adjustment unit, to keep specified output voltage.If load increases, output voltage descends, and the output of voltage error amplifier will increase, and make more current direction load; If load current reduces, output voltage can rise, and then the output of voltage error amplifier will make adjustment unit flow to the electric current minimizing of load.It realizes that the method for time-delay is negative input end (being that output voltage is through the voltage behind the divider resistance) electric capacity in parallel at error amplifier, make the negative terminal voltage rise time of error amplifier elongated, its essence has still increased by a big electric capacity at output, thereby realizes that lag output powers in input.

More than the electrifying timing sequence of three kinds of technical schemes shown in Fig. 4 a, this shows that in the existing tandem linear power supply, realization output is delayed time and powered in input, its essence all is to strengthen electric capacity at output, the slope that change output is risen, it is steep to make output not import the slope that powers on, and the big more charging interval of output capacitance is long more, then the rise of output voltage slope is slow more than the rate of rise of input, the time that arrives specified output is long more, but the starting point that both rise is identical, is to begin to rise from 0V simultaneously.On essence, be not time-delay truly; As C scheme the inside, the discharge time of delay capacitor is unadjustable in addition, as long as after feedback parameter setting and delay time were set, also just decided discharge time, concerning the circuit of the frequent switch output of needs, realizes that difficulty is bigger.

Summary of the invention

Primary and foremost purpose of the present invention is: a kind of linear voltage stabilization delay circuit is provided, and this circuit is delayed time the foundation of output voltage and is powered on constantly in input, can realize linear voltage stabilization again simultaneously.

Further aim of the present invention is: make the having or not of linear voltage stabilization delay circuit may command output voltage, simultaneously, under the fixed situation of delay time, the discharge time of scalable delay capacitor, satisfy the environment for use of frequent switch.

For solving the problems of the technologies described above, according to an aspect of the present invention, a kind of linear voltage stabilization delay circuit is provided, comprise a sample circuit, one is connected on the adjustment pipe between input power supply and the output loading, and voltage error amplifier, described sample circuit is connected in parallel on the output of this linear voltage stabilization delay circuit, the negative input end of voltage error amplifier connects the dividing point of sample circuit, its anode connects the control end of described adjustment pipe by driving resistor R1, be connected a delay driving circuit between the input that also is included in this linear voltage stabilization delay circuit and the anode of described error amplifier, be used to control the settling time of described adjustment pipe driving voltage, make the foundation of described output voltage lag behind described input voltage.

Described linear voltage stabilization delay circuit, wherein: described delay driving circuit comprises time delay resistance and the delay capacitor C2 that is linked in sequence between described input and ground, the anode of described error amplifier connects the tie point of described delay capacitor C2 and time delay resistance, after described input powers on, charge to delay capacitor through described time delay resistance, until the conducting of described adjustment pipe, set up output voltage at described output; Also comprise a discharge circuit, described delay capacitor C2 is by this discharge circuit discharge.

Described linear voltage stabilization delay circuit, wherein: described discharge circuit is an ON-OFF control circuit, control this ON-OFF control circuit by control signal and be conducting or cut-off state, when this switching circuit ends, described output has normal output voltage, and when the switching circuit conducting, the anode of error amplifier is pulled to ground, described output no-output voltage, and described delay capacitor C2 is by this ON-OFF control circuit discharge.

Described linear voltage stabilization delay circuit, wherein: described time delay resistance is in series by resistance R 3 and resistance R 2, the described input of resistance R 3 one terminations, and an end of resistance R 2 connects described delay capacitor C2; Described ON-OFF control circuit comprises a switching tube, and the collector electrode of described switching tube connects the tie point of resistance R 3 and resistance R 2, its grounded emitter, and its control utmost point is by resistance R 4 connection control signal.

Described linear voltage stabilization delay circuit, wherein: described adjustment pipe is a N channel field-effect pipe, and described control signal is a pulse signal.

Described linear voltage stabilization delay circuit, wherein: described ON-OFF control circuit can also be made of resistance R 5 and commutator K1, one end of described resistance R 5 and the closing end of commutator K1 all are connected to the node of described resistance R 2 and R3, the other end of described resistance R 5 is connected with another closing end of described commutator K1, the control end ground connection of described commutator K1.

Described linear voltage stabilization delay circuit, wherein: the value of described delay capacitor C2, resistance R 2 and R3 satisfies following formula:

${\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="A200710124069E00161.png"\; state="\{\{state\}\}">t</figure-callout>}}_1=(R_2+R_3)\&times;{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A200710124069E00161.png"\; state="\{\{state\}\}">C</figure-callout>}}_2\ln \frac{V_{\mathrm{in}}}{V_{\mathrm{in}}-V_{\mathrm{GS}\left(\mathrm{th}\right)}-V_{\mathrm{out}}}$ And t ₂=R ₂* C ₂

Wherein: t1 is that output voltage was delayed time in the time of input voltage;

T2 be the shortest time of control signal when just changing at interval;

Vin is an input voltage;

Vout is an output voltage;

VGS (th) is the grid of adjustment pipe and the conducting voltage threshold value between the source electrode.

The beneficial effect of a technical scheme in the technique scheme is: the moment of adjusting the pipe conducting is controlled in the driving of adjusting pipe by delay driving circuit control, thereby control output voltage moment of setting up effectively, make the output voltage of linear voltage stabilization delay circuit different with the moment that input powers on from the moment that 0V rises, initial time has just embodied the function of time-delay from power on, can satisfy more harsh time-delay demand.And this linear voltage stabilization delay circuit not only has higher output voltage precision, but also can be by the having or not of ON-OFF control circuit control output voltage, and makes this linear voltage stabilization delay circuit whether can control output voltage, applying flexible as required.Simultaneously, can under the fixed situation of delay time,, regulate the discharge time of delay capacitor, make the restriction that is not subjected to feedback parameter and delay time discharge time, satisfy the environment for use of frequent switch by adjusting the ratio of resistance R 2, R3.

Description of drawings

Fig. 1 adopts the voltage stabilizing circuit of voltage stabilizing didoe for prior art;

Fig. 2 adopts the single-transistor tandem type linear power supply of discrete component for prior art;

Fig. 3 adopts the linearity time-delay power supply of departure amplifier for prior art;

Fig. 4 a is a prior art electrifying timing sequence curve;

Fig. 4 b is an electrifying timing sequence curve of the present invention;

Fig. 5 is a principle of the invention block diagram;

Fig. 6 is the circuit diagram of one embodiment of the present invention;

Fig. 7 is the circuit diagram of another embodiment of the present invention.

Embodiment

With embodiment the present invention is described in further detail with reference to the accompanying drawings below:

Linear voltage stabilization delay circuit of the present invention at first satisfies linear voltage stabilization and output is delayed time in the function of input voltage, its design principle as shown in Figure 5, comprise the voltage stabilizing part identical: comprise the sample circuit of forming by resistance R a and resistance R b with prior art C, this sample circuit is connected in parallel on the output of this linear voltage stabilization delay circuit, the end ground connection of Rb, an end links to each other with Ra; One is connected on the adjustment pipe Q1 between input power supply and the output loading, adjusts pipe and can adopt N channel field-effect pipe (MOSFET), also can adopt NPN transistor, is provided with to adjust plumber's work at linear zone.When adopting N channel field-effect pipe, Q1 source electrode (the S utmost point) connects the output of this linear voltage stabilization delay circuit, and drain electrode (the D utmost point) connects the input of this linear voltage stabilization delay circuit, and input and output voltage altogether.Also comprise a voltage error amplifier U1, U1 can realize with LM431.The negative input end of LM431 (is also referred to as reference edge or VREF end, negative input end for the LM431 internal amplifier) dividing point of connection sample circuit, it is the contact of resistance R a and Rb, output voltage after Ra, Rb dividing potential drop near the reference voltage of LM431, the anode of LM431 connects the control end (grid (the G utmost point)) of Q1 by driving resistor R1, its minus earth, and between the anode of LM431 and benchmark, add a capacitor C 1 compensation (this is compensated for as the compensation of feedback loop).Its principle of stabilized voltage is same as the prior art, and when load increased, output voltage can descend, the internal amplifier backward end input of LM431 just reduces, amplifier output will increase like this, and promptly the anode voltage of LM431 can raise, and the electric current that makes MOSFET flow to load increases; When load reduced, output voltage can raise, and the input of LM431 internal amplifier backward end just raises, and amplifier output will reduce like this, and promptly the anode voltage of LM431 can reduce, and the electric current that makes MOSFET flow to load reduces.The voltage negative feedback realizes the stable of electric power output voltage.

Different is with prior art, between the anode of the input of this linear voltage stabilization delay circuit and error amplifier LM431, be connected a delay driving circuit, as shown in Figure 5, this delay driving circuit is used to control the driving of adjusting pipe Q1, promptly control the settling time of this driving voltage, just make the grid of MOSFET pipe conducting, source electrode (G, S) settling time of conducting voltage threshold value between, control the moment of adjusting the pipe conducting, thereby the moment that control output voltage is set up, make the foundation of output voltage lag behind described one scheduled time of input voltage, this scheduled time is the required output of this circuit and delays time in the delay time of input.Delay driving circuit can take multiple circuit to realize, Figure 6 shows that a kind of concrete enforcement circuit that the present invention adopts.

In the embodiment shown in fig. 6, the voltage stabilizing part does not repeat them here as mentioned above.For the purpose that realizes delaying time, delay driving circuit comprises time delay resistance and the delay capacitor C2 that is linked in sequence between input and ground, the tie point of delay capacitor C2 and time delay resistance is connected to the anode of error amplifier, and time delay resistance can adopt a resistance also can adopt 2 resistance R 2, the R3 realization of connecting.The anode voltage of LM431 is charged to C2 by R2, R3 by input voltage vin and sets up, thus, the G of capacitor C 2 control MOSFET, S voltage settling time, (this value must can make the MOSFET conducting when the anode voltage of LM431 is charged to certain value, be referred to as G, S threshold value, with VGS (th) expression, by the parameter decision of MOSFET), output end voltage is set up and past the rising since 0; And after this voltage on the C2 is still charged to it by R2, R3 by Vin, therefore the slope of output voltage rising is consistent with the slope that the anode voltage of U1 (LM431) rises, when output voltage rises to the output voltage of setting, the anode voltage of LM431 will no longer rise, therefore delay time be C2 from the time that 0V is charged to (Vout+VGS (th)), determine by the value of delay capacitor C2 and time delay resistance R2, R3.The relation of input and output voltage is shown in Fig. 4 b, as seen from Figure 4, embodiments of the invention unlike the prior art, the moment that output voltage is set up lags behind input voltage and powers on constantly, the two starting point difference, having controlled output voltage effectively and initially set up constantly, is delay circuit truly.

Delay driving circuit also comprises a discharge circuit, gives C2 one discharge loop, makes C2 pass through this discharge circuit discharge.Discharge circuit can be simply be connected a discharge resistance between resistance R 2, R3 tie point and ground, this discharge resistance and R2 form discharge loop, and C2 is discharged by resistance R 2 and discharge resistance.It is enough big that this discharge resistance will satisfy input voltage dividing potential drop in the above, can drive Q1, satisfies the minimum available machine time again at interval.The preferred embodiment for the present invention is that discharge circuit adopts an ON-OFF control circuit to realize that ON-OFF control circuit is controlled it by control signal and is conducting or cut-off state, and control signal can be a pulse signal, also can be other signal.When this switching circuit ends, the output of this linear voltage stabilization delay circuit has normal output voltage, when the switching circuit conducting, move the anode voltage of LM431 to ground by resistance R 2, make the output no-output voltage of this linear voltage stabilization delay circuit, at this moment, delay capacitor C2 is by this ON-OFF control circuit discharge.Can realize the function of discharge loop with ON-OFF control circuit as discharge circuit, again can control output voltage have or not.Concrete ON-OFF control circuit as shown in Figure 6, on the node that R2, R3 join, increase the collector electrode of NPN triode Q2, control signal (POFF signal) is received the base stage of Q2 by a resistance R 4, and base stage is to increasing by a decoupling capacitor C3 between the ground, and the emitter of Q2 receives ground.When needs output voltage V out, it is low providing the POFF signal, and Q2 ends, the rising of normally delaying time of the anode voltage of LM431, circuit operate as normal; When not needing Vout output, providing the POFF signal is a high level signal, and Q2 is with conducting, and the anode of LM431 is pulled to ground, the MOSFET Triggerless, and output Vout can not set up; Simultaneously because the passage of a discharge of charge stored on C2 is given in the conducting of Q2, C2 will be by R2, Q2 discharge, and this discharge time constant determines by C2 and R2 value size, and C2 and R2 value size are then by minimum switching time of the interval determination of needs.Determine by the value of delay capacitor C2 and time delay resistance R2, R3 according to aforementioned delay time as can be known, this shows, can be under the fixed situation of delay time, by adjusting the ratio of resistance R 2, R3, regulate the discharge time of delay capacitor C2, make the restriction that is not subjected to feedback parameter and delay time discharge time, satisfy the environment for use of frequent switch.

Below be quantitative and qualitative analysis to circuit of the present invention, and each CALCULATION OF PARAMETERS:

1, calculate the method for Ra, Rb: the voltage on the Rb is near the reference voltage 2.5V of U1 (LM431), therefore

$\frac{2.5}{R_b}\&times;(R_a+R_b)=V_{\mathrm{out}}$

2, the time-delay partial parameters calculates:

${\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="A200710124069E00161.png"\; state="\{\{state\}\}">t</figure-callout>}}_1=({\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="A200710124069E00161.png"\; state="\{\{state\}\}">R</figure-callout>}}_2+R_3)\&times;{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A200710124069E00161.png"\; state="\{\{state\}\}">C</figure-callout>}}_2\ln \frac{V_{\mathrm{in}}}{V_{\mathrm{in}}-V_{\mathrm{GS}\left(\mathrm{th}\right)}-V_{\mathrm{out}}}$

Wherein: t1 is for needing between time-delay;

Vin is an input voltage;

Vout is an output voltage;

VGS (th) is the grid of MOSFET and the conducting voltage threshold value between the source electrode;

t ₂＝R ₂×C ₂

Wherein, t2 be the shortest time of POFF signal when just changing at interval;

3, the POFF control section calculates:

Make Q2 be in the saturation conduction state during for high level, then at POFF

$R_4\&le;\frac{V_{\mathrm{poff}}-0.7}{I_B}$

Voltage magnitude when wherein, Vpoff is high level for the POFF signal;

Minimum current when Ib is the Q2 saturation conduction.

Another embodiment of the present invention as shown in Figure 7, this circuit and above-mentioned circuit difference shown in Figure 6 are: Q1 has adopted NPN transistor, ON-OFF control circuit is realized by resistance R 5 and commutator K1, one of resistance R 5 is connected to the node of resistance R 2 and R3, the other end is connected with a closing end (2 end) of K switch 1, another closing end of K switch 1 (1 end) also is connected to the node of resistance R 2 and R3, its control end 3 ground connection.When needs output voltage V out, K switch 1 is thrown to 2 ends, and the output of linear voltage stabilization delay circuit is normally exported, and when not needing Vout output, K switch 1 is thrown to 2 ends, and Q1 does not have driving voltage, and output Vout can not set up.

The experiment of the present invention's process, and on five classification blood cell analyzers, use, actual this scheme of proof can realize delay function, and the energy reliability service.Linear voltage stabilization delay circuit of the present invention can be applied in the multiple-output electric power, and power supply is respectively organized in output in order, and in large-scale power-supply system, controls the power supply of each chip for driving.

Be understandable that, for those of ordinary skills, can be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, and all these changes or replacement all should belong to the protection range of the appended claim of the present invention.

Claims (7)

1, a kind of linear voltage stabilization delay circuit, comprise a sample circuit, one is connected on the adjustment pipe between input power supply and the output loading, and voltage error amplifier, described sample circuit is connected in parallel on the output of this linear voltage stabilization delay circuit, the negative input end of voltage error amplifier connects the dividing point of sample circuit, its anode connects the control end of described adjustment pipe by driving resistor R1, it is characterized in that: between the anode of the input of this linear voltage stabilization delay circuit and described error amplifier, be connected a delay driving circuit, be used to control the settling time of described adjustment pipe driving voltage, make the foundation of described output voltage lag behind described input voltage.

2, linear voltage stabilization delay circuit according to claim 1, it is characterized in that: described delay driving circuit comprises time delay resistance and the delay capacitor C2 that is linked in sequence between described input and ground, the anode of described error amplifier connects the tie point of described delay capacitor C2 and time delay resistance, after described input powers on, charge to delay capacitor through described time delay resistance, until the conducting of described adjustment pipe, set up output voltage at described output; Also comprise a discharge circuit, described delay capacitor C2 is by this discharge circuit discharge.

3, linear voltage stabilization delay circuit according to claim 2, it is characterized in that: described discharge circuit is an ON-OFF control circuit, control this ON-OFF control circuit by control signal and be conducting or cut-off state, when this switching circuit ended, described output had normal output voltage; When the switching circuit conducting, the anode of error amplifier is pulled to ground, described output no-output voltage, and described delay capacitor C2 is by this ON-OFF control circuit discharge.

4, linear voltage stabilization delay circuit according to claim 3 is characterized in that: described time delay resistance is in series by resistance R 3 and resistance R 2, the described input of resistance R 3 one terminations, and an end of resistance R 2 connects described delay capacitor C2; Described ON-OFF control circuit comprises a switching tube, and the collector electrode of described switching tube connects the tie point of resistance R 3 and resistance R 2, its grounded emitter, and its control utmost point is by resistance R 4 connection control signal.

5, linear voltage stabilization delay circuit according to claim 4 is characterized in that: described adjustment pipe is a N channel field-effect pipe, and described control signal is a pulse signal.

6, linear voltage stabilization delay circuit according to claim 3 is characterized in that: described time delay resistance is in series by resistance R 3 and resistance R 2, the described input of resistance R 3 one terminations, and an end of resistance R 2 connects described delay capacitor C2; Described ON-OFF control circuit is made of resistance R 5 and commutator K1, one end of described resistance R 5 and the closing end of commutator K1 all are connected to the node of described resistance R 2 and R3, the other end of described resistance R 5 is connected with another closing end of described commutator K1, the control end ground connection of described commutator K1.

7, according to the described linear voltage stabilization delay circuit of the arbitrary claim of claim 4 to 6, it is characterized in that: the value of described delay capacitor C2, resistance R 2 and R3 satisfies following formula:

$t_1=(R_2+R_3)\&times;C_2\ln \frac{V_{\mathrm{in}}}{V_{\mathrm{in}}-V_{\mathrm{GS}\left(\mathrm{th}\right)}-V_{\mathrm{out}}}$ And t ₂=R ₂* C ₂

Wherein: t1 is that output voltage was delayed time in the time of input voltage;

T2 be the shortest time of control signal when just changing at interval;

Vin is an input voltage;

Vout is an output voltage;

VGS (th) is the grid of adjustment pipe and the conducting voltage threshold value between the source electrode.

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