CN101409302A - Phase-change memory array and manufacturing method thereof - Google Patents
Phase-change memory array and manufacturing method thereof Download PDFInfo
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- CN101409302A CN101409302A CNA2007101801558A CN200710180155A CN101409302A CN 101409302 A CN101409302 A CN 101409302A CN A2007101801558 A CNA2007101801558 A CN A2007101801558A CN 200710180155 A CN200710180155 A CN 200710180155A CN 101409302 A CN101409302 A CN 101409302A
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- 229910052718 tin Inorganic materials 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 229910010038 TiAl Inorganic materials 0.000 claims description 5
- 229910010037 TiAlN Inorganic materials 0.000 claims description 5
- 150000004770 chalcogenides Chemical class 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
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- 238000005229 chemical vapour deposition Methods 0.000 description 8
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- 239000007772 electrode material Substances 0.000 description 8
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
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Abstract
The invention discloses a phase change memory array and a manufacturing method thereof. The phase change memory array comprises a first unit and a second unit; wherein, the first unit comprises a graphic phase change layer, and the second unit comprises a graphic phase change layer. The graphic phase change layer of the first unit and the graphic phase change layer of the second unit are positioned at different layers.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly a kind of phase-change memory array and manufacture method thereof.
Background technology
Ovonics unified memory has competitive characteristics such as speed, power, capacity, reliability, process integration degree and cost, for being fit to be used as the stand alone type or the Embedded memory application of higher density.Because the unique advantage of Ovonics unified memory technology, make it be considered to might replace very much highly competititve static memory SRAM of present commercialization and dynamic random access memory DRAM volatile storage, with flash memory Flash non-volatility memorizer technology, be expected to become the new generation semiconductor memory that will have potentiality future.
Phase change memory device is the mechanism that the resistance value difference of utilizing phase-transition material to be caused in crystalline state and amorphous reversible Structure Conversion is used as data storing.Writing, wiping or during read operation, mainly be to utilize the control of electric current pulse wave to reach, for example, fashionable when writing, one short time (for example 50 nanoseconds) and higher relatively electric current (for example 0.6 milliampere) can be provided, make phase change layer fusing and quick cooling and the formation amorphous state.Because the amorphous state phase change layer has higher resistance (for example 10
5～10
7Ohm), make it when read operation, providing one, to read the available voltage of electric current higher relatively.In the time will wiping, a long period (for example 100 nanoseconds) and relatively low electric current (for example 0.3 milliampere) can be provided, make the amorphous state phase change layer convert crystalline state to because of crystallization.Because the crystalline state phase change layer has lower resistance (for example 10
2～10
4Ohm), it is when read operation, and providing one, to read the available voltage of electric current relatively low.In view of the above, can carry out the operation of phase change memory device.
In recent years, the size of phase change memory device continues micro, and as shown in Figure 1, after the size micro, unit 102 promptly can reduce with the neighbor distance d of unit 102.The unit are micro of supposing unit 102 is to 5.8F
2The time (F represents the minimum feature size (minimum feature size) of technology), adjacent Ovonics unified memory unit 102 have only 2.4F approximately apart from d.Therefore, micro along with the unit cell size of Ovonics unified memory 100, the distance that unit 102 and unit are 102 promptly can reduce, make 102 of Ovonics unified memory unit that the problem that heat is disturbed (thermal disturb or thermal crosstalk) can take place, that is the state of Ovonics unified memory unit 102 can be subjected to the interference of adjacent cells 102 when operation.
Summary of the invention
According to the problems referred to above, the present invention by with Ovonics unified memory unit vertical interlaced be stacked among the different levels, make the distance of adjacent Ovonics unified memory unit to elongate effectively, and then the problem of avoiding Ovonics unified memory heat to disturb.
The invention provides a kind of phase-change memory array, comprise first module and Unit second.This first module comprises a graphical phase change layer, and this Unit second comprises a graphical phase change layer, and wherein the graphical phase change layer of the graphical phase change layer of first module and Unit second is positioned at different layers.
The invention provides a kind of manufacture method of phase-change memory array.Substrate is provided, forms the bottom electrode of first module, graphical phase change layer and top electrode are in substrate.Behind the top electrode that forms first module, form the bottom electrode of Unit second, graphical phase change layer and top electrode.
Description of drawings
Fig. 1 shows the plane graph of general phase-change memory array.
Fig. 2 A～2H discloses the manufacture method of one embodiment of the invention phase-change memory array.
Fig. 3 shows the plane graph of one embodiment of the invention phase-change memory array.
Fig. 4 shows the plane graph of another embodiment of the present invention phase-change memory array.
Fig. 5 shows the present invention's plane graph of another embodiment phase-change memory array again.
Fig. 6 A～6H discloses the manufacture method of another embodiment of the present invention phase-change memory array.
Description of reference numerals
100～phase-change memory array; 102～unit;
200～phase-change memory array; 202～substrate;
204～switch element; 205～the first dielectric layers;
206～first module; Unit 208～the second;
The bottom electrode of 210～first module; Connect in the part of Unit 212～the second;
214～phase-transition material; 216～electrode material;
The graphical phase change layer of 218～first module; The top electrode of 220～first module;
222～the second dielectric layers; Connect in the part of 224～first module;
Connect in 226～the second cell mesh; The interior connection of Unit 228～the second;
230～the 3rd dielectric layers; Connect in the part of 232～first module;
The bottom electrode of Unit 234～the second; 236～phase-transition material;
238～electrode material; The graphical phase change layer of Unit 240～the second;
The top electrode of Unit 242～the second; 244～the 4th dielectric layers;
Connect in the part of 246～first module; The interior connection of 248～first module;
The interior connection of Unit 250～the second; 252～bit line;
402～first module; Unit 404～the second;
604～switch element; 605～the first dielectric layers;
606～first module; Unit 608～the second;
The bottom electrode of 610～first module; 612～phase-transition material;
614～electrode material; The graphical phase change layer of 616～first module;
The top electrode of 618～first module; 620～the second dielectric layers;
Connect in the part of 622～first module; The interior connection of Unit 624～the second;
626～the 3rd dielectric layers; The bottom electrode of Unit 628～the second;
630～phase-transition material; 632～electrode material;
The graphical phase change layer of Unit 634～the second; The top electrode of Unit 636～the second;
638～the 4th dielectric layers; The interior connection of 642～first module;
The interior connection of Unit 644～the second; 646～bit line.
Embodiment
Below go through the manufacturing and the use of the preferred embodiment of the present invention, yet according to notion of the present invention, it can comprise or apply to technical scope widely.It is noted that embodiment is only in order to disclose the ad hoc approach of manufacturing of the present invention and use, not in order to limit the present invention.
Fig. 2 A～2H discloses the manufacture method of one embodiment of the invention phase-change memory array 200.At first, please refer to Fig. 2 A, substrate 202 is provided, in the preferred embodiment of the present invention, substrate 202 is a silicon base, but the invention is not restricted to this, and substrate 202 can be made up of other semi-conducting material.Then, form a plurality of switch elements 204 in substrate 202, the switch element 204 of present embodiment comprises the vertical diode (vertical diode) that p type semiconductor layer and n type semiconductor layer are formed, but the invention is not restricted to this, switch element 204 can also be bipolar junction transistor (bipolar junction transistor, BJT) or metal oxide semiconductcor field effect transistor (metal oxide semiconductor field effect transistor, MOSFET).Follow-up, form first dielectric layer 205 in switch element 204 and substrate 202 with for example chemical vapour deposition technique, first dielectric layer 205 can comprise silica, silicon nitride or silicon oxynitride.
Then, please refer to Fig. 2 B, with for example photoetching and etch process, 205 layers of graphical first dielectrics, form the opening (not illustrating) that exposes switch element 204, follow-up, in opening, insert for example electric conducting material of Ti, W, Ta, TiN, TiW, TaN, TaW, TiAl, TiWN, TiAlN or polysilicon etc., be connected 212 in the part with the bottom electrode 210 that forms first module 206 and second unit 208.
Next, please refer to Fig. 2 C, the phase-transition material 214 that deposits to the blanket property covered Ge-Te-Sb chalcogenide for example is on first dielectric layer 205, and the electrode material 216 that then deposits to the blanket property covered TiN for example or TiW is on phase-transition material 214.Continue it, please refer to Fig. 2 D, with for example photoetching and etch process, patterned electrodes material 216 and phase-transition material 214, with the graphical phase change layer 218 that forms first module 206 on the bottom electrode 210 of first module 206 and the top electrode 220 of first module 206 on graphical phase change layer 218.Follow-up, form second dielectric layer 222 on the top electrode 220 and first dielectric layer 205 with for example chemical vapour deposition technique, second dielectric layer 222 can comprise silica, silicon nitride or silicon oxynitride.
, please refer to Fig. 2 E, grind second dielectric layer 222, and then with for example photoetching and etch process, graphical second dielectric layer 222 forms a plurality of openings (not illustrating) with for example chemical mechanical polishing method thereafter.Then, in opening, insert for example electric conducting material of W, to connect 224 in the part that on the top electrode 220 of first module 206, forms first module 206, and in the part of second unit 208, connect 226 in formation another part in the connection 212, to constitute the interior connection 228 under Unit second 208 phase change layers.
Please refer to Fig. 2 F, form the 3rd dielectric layer 230 on second dielectric layer 222 with for example chemical vapour deposition technique, the 3rd dielectric layer 230 can comprise silica, silicon nitride or silicon oxynitride.With for example photoetching and etch process, graphical the 3rd dielectric layer 230 forms a plurality of openings (not illustrating).Follow-up, in opening, insert for example electric conducting material of Ti, W, Ta, TiN, TiW, TaN, TaW, TiAl, TiWN, TiAlN or polysilicon etc., in the part of first module 206, to connect on 224, form in another part and connect 232, and in the interior connection 228 of second unit 208, form the bottom electrode 234 of second unit 208.Thereafter, the phase-transition material 236 that deposits to the blanket property covered Ge-Te-Sb chalcogenide for example is on the 3rd dielectric layer 230, and the electrode material 238 that then deposits to the blanket property covered TiN for example or TiW is on phase-transition material 236.Continue it, please refer to Fig. 2 G, with for example photoetching and etch process, patterned electrodes material 238 and phase-transition material 236, with the graphical phase change layer 240 that forms second unit 208 on the bottom electrode 234 of second unit 208 and the top electrode 242 of second unit 208 on graphical phase change layer 240.Note that the graphical phase change layer 240 of second unit 208 and the graphical phase change layer 218 of first module 206 are positioned at different layers, and horizontal-shift fixed range each other.
Follow-up, please refer to Fig. 2 H, form the 4th dielectric layer 244 on the top electrode 242 and the 3rd dielectric layer 230 of second unit 208 with for example chemical vapour deposition technique, the 4th dielectric layer 244 can comprise silica, silicon nitride or silicon oxynitride.With for example photoetching and etch process, graphical the 4th dielectric layer 244 forms a plurality of openings (not illustrating).Then, in opening, insert for example electric conducting material of W, in the part of first module 206, connect form on 232 and another part in connect 246, with the interior connection 248 on the top electrode 220 that constitutes first module 206, and connection 250 on the top electrode 242 of second unit 208, forming.Follow-up, formation multiple bit lines 252 connects first module 206 respectively and the interior of second unit 208 is connected 248,250.
So, finish one embodiment of the invention phase-change memory array 200, shown in Fig. 2 H, first module 206 is adjacent with second unit 208, and the graphical phase change layer 240 of the graphical phase change layer 218 of first module 206 and second unit 208 is positioned at different layers.In an embodiment of the present invention, the horizontal range of the first module 206 and second unit 208 is substantially less than 250nm.In addition, in an embodiment of the present invention, the interior connection of adjacent cells has different length, and for instance, shown in Fig. 2 H, the interior connection 248 on the top electrode 220 of first module 206 is long than the interior connection on the top electrode 242 of second unit 208 250.
Fig. 3 shows the plane graph of one embodiment of the invention phase-change memory array.In this embodiment, the graphical phase change layer of the graphical phase change layer of adjacent first module 206 and second unit 208 lays respectively at the ground floor and the second layer, yet, the invention is not restricted to this, the graphical phase change layer of the graphical phase change layer of first module 206 and second unit 208 can lay respectively at other layer of different layers.For example, the graphical phase change layer of the graphical phase change layer of first module 206 and second unit 208 lays respectively at ground floor and N layer, and N is 2～10.
Fig. 4 shows the plane graph of another embodiment of the present invention phase-change memory array.As shown in the figure, first module 402 is adjacent with second unit 404, and the horizontal range of 402 of the 3rd unit 406 and first modules, and is far away than the horizontal range of 402 of second unit 404 and first modules.The number of plies that the graphical phase change layer of first module 402 and the graphical phase change layer of this Unit second 404 differ, the number of plies that differs than the graphical phase change layer of the graphical phase change layer of first module 402 and the 3rd unit 406 is many.In an example, the graphical phase change layer of first module 402 is positioned at ground floor, the graphical phase change layer that is positioned at second unit 404 of first module 402 both sides is positioned at the 3rd layer, and the graphical phase change layer that is positioned at the 3rd unit 406 at first module 402 oblique angles is positioned at the second layer.Note that the embodiment that the present invention includes three-layer unit, be not limited to the arrangement mode of Fig. 4, it can adopt alternate manner to arrange.
Fig. 5 shows the present invention's plane graph of another embodiment phase-change memory array again.As shown in the figure, the first module 502 and second unit 504 are adjacent with the 3rd unit 506, and the phase change layer of first, second and the 3rd unit 502,504,506 lays respectively at different layers.The horizontal range that the 4th unit 508 and first module are 502 is far away than the horizontal range of 502 of the second and the 3rd unit 504,506 and first modules, the number of plies that the graphical phase change layer of the 4th unit 508 and the graphical phase change layer of first module 502 differ, the number of plies that differs than the graphical phase change layer of the graphical phase change layer of first module 502 and the second and the 3rd unit 504,506 is few.In an example, the graphical phase change layer of first module 502 is positioned at ground floor, be positioned at second unit 504 of first module 502 both sides and the graphical phase change layer of the 3rd unit 506 and lay respectively at the 3rd layer and the 4th layer, the graphical phase change layer that is positioned at the 4th unit 508 at first module 502 oblique angles is positioned at the second layer.Note that the embodiment that the present invention includes four layers of unit is not limited to the arrangement mode of Fig. 5, it can adopt alternate manner to arrange.
Fig. 6 A～6H discloses the manufacture method of another embodiment of the present invention phase-change memory array.At first, please refer to Fig. 6 A, substrate 602 is provided, then, form a plurality of switch elements 604 in substrate 602.Follow-up, form first dielectric layer 605 in switch element 604 and substrate 602 with for example chemical vapour deposition technique, first dielectric layer 605 can comprise silica, silicon nitride or silicon oxynitride.
Shown in Fig. 6 B, with for example photoetching and etch process, graphical first dielectric layer 605, form the opening (not illustrating) that exposes switch element 604, follow-up, in opening, insert for example electric conducting material of Ti, W, Ta, TiN, TiW, TaN, TaW, TiAl, TiWN, TiAlN or polysilicon etc., to form the bottom electrode 610 of first module 606.Next, please refer to Fig. 6 C, the phase-transition material 612 that deposits to the blanket property covered Ge-Te-Sb chalcogenide for example is on first dielectric layer 605, and the electrode material 614 that then deposits to the blanket property covered TiN for example or TiW is on phase-transition material 612.
Continue it, please refer to Fig. 6 D, with for example photoetching and etch process, patterned electrodes material 614 and phase-transition material 612, with the graphical phase change layer 616 that forms first module 606 on the bottom electrode 610 of first module 606 and the top electrode 618 of first module 606 on graphical phase change layer 616.Follow-up, form second dielectric layer 620 on the top electrode 618 and first dielectric layer 605 with for example chemical vapour deposition technique, second dielectric layer 620 can comprise silica, silicon nitride or silicon oxynitride.
, please refer to Fig. 6 E, grind second dielectric layer 620, and then with for example photoetching and etch process, graphical second dielectric layer 620 forms a plurality of openings (not illustrating) with for example chemical mechanical polishing method thereafter.Follow-up, in opening, insert for example electric conducting material of W, connect 622 in the part with formation first module 606 on the top electrode 618 of first module 606, and form the interior connection 624 under Unit second 608 phase change layers.
Then, please refer to Fig. 6 F, form the 3rd dielectric layer 626 on second dielectric layer 620 with for example chemical vapour deposition technique, the 3rd dielectric layer 626 can comprise silica, silicon nitride or silicon oxynitride.With for example photoetching and etch process, graphical the 3rd dielectric layer 626 forms a plurality of openings (not illustrating).Follow-up, in opening, insert for example electric conducting material of Ti, W, Ta, TiN, TiW, TaN, TaW, TiAl, TiWN, TiAlN or polysilicon etc., in the interior connection 624 of second unit 608, form the bottom electrode 628 of second unit 608.Thereafter, the phase-transition material 630 that deposits to the blanket property covered Ge-Te-Sb chalcogenide for example is on the 3rd dielectric layer 626, and the electrode material 632 that then deposits to the blanket property covered TiN for example is on phase-transition material 630.
Continue it, please refer to Fig. 6 G, with for example photoetching and etch process, patterned electrodes material 632 and phase-transition material 630, with the graphical phase change layer 634 that forms second unit 608 on the bottom electrode 628 of second unit 608 and the top electrode 636 of second unit 608 on graphical phase change layer 634.Note that the graphical phase change layer 634 of second unit 608 and the graphical phase change layer 616 of first module 606 are positioned at different layers, and horizontal-shift fixed range each other.
Please refer to Fig. 6 H, form the 4th dielectric layer 638 on the top electrode 636 and the 3rd dielectric layer 626 of second unit 608 with for example chemical vapour deposition technique, the 4th dielectric layer 638 can comprise silica, silicon nitride or silicon oxynitride.With for example photoetching and etch process, graphical the 4th dielectric layer 638 forms a plurality of openings (not illustrating).Follow-up, in opening, insert for example electric conducting material of W, in the part of first module 606, connect to form in another part on 622 and connect 640, and constitute interior connection 642 on the top electrode 618 of first module 606, and on the top electrode 636 of second unit 608, form the interior connection 644 of second unit 608.Then, formation multiple bit lines 646 connects first module 606 respectively and the interior of second unit 608 is connected 642,644.
According to the above embodiment of the present invention, the unit of phase-change memory array be vertical interlaced be stacked in the different levels, make the distance of adjacent Ovonics unified memory unit to elongate effectively, thereby reduce the problem that Ovonics unified memory unit heat is disturbed.In addition, method and structure of the present invention does not increase under the condition of the size of unit cell in the memory array or area haply, reduces the problem that Ovonics unified memory unit heat is disturbed, so can reach the high density phase change memory.
The embodiment that more than provides is in order to the different technical characterictic of description the present invention, but according to notion of the present invention, it can comprise or apply to technical scope widely.It is noted that embodiment is only in order to disclose the ad hoc approach of technology of the present invention, device, composition, manufacturing and use, not in order to limiting the present invention, those skilled in the art without departing from the spirit and scope of the present invention, when doing a little change and retouching.Therefore, protection scope of the present invention is when looking being as the criterion that accompanying Claim defines.
Claims (20)
1. phase-change memory array comprises:
First module comprises a graphical phase change layer;
Unit second comprises a graphical phase change layer,
Wherein the graphical phase change layer of the graphical phase change layer of this first module and this Unit second is positioned at different layers.
2. phase-change memory array as claimed in claim 1, wherein this first module is adjacent with this Unit second.
3. phase-change memory array as claimed in claim 2 also comprises Unit the 3rd, comprises a graphical phase change layer, and wherein the graphical phase change layer of the graphical phase change layer of Unit the 3rd and this Unit first and second is positioned at different layers.
4. phase-change memory array as claimed in claim 3, the horizontal range between Unit the 3rd and this first module wherein, far away than the horizontal range between this Unit second and this first module, and the number of plies that the graphical phase change layer of this first module and the graphical phase change layer of this Unit second differ, the number of plies that differs than the graphical phase change layer of the graphical phase change layer of this first module and Unit the 3rd is many.
5. phase-change memory array as claimed in claim 4, wherein the graphical phase change layer of this first module is positioned at ground floor, the graphical phase change layer that is positioned at Unit second of these first module both sides is positioned at the 3rd layer, and the graphical phase change layer that is positioned at Unit the 3rd at this first module oblique angle is positioned at the second layer.
6. phase-change memory array as claimed in claim 3 also comprises Unit the 4th, comprises a graphical phase change layer, wherein the graphical phase change layer of Unit the 4th and this first, second and the graphical phase change layer of Unit the 3rd be positioned at different layers.
7. phase-change memory array as claimed in claim 6, the horizontal range between Unit the 4th and this first module wherein, far away than the horizontal range between this Unit the second and the 3rd and this first module, and the number of plies that the graphical phase change layer of this first module and the graphical phase change layer of Unit the 4th differ, the number of plies that differs than the graphical phase change layer of the graphical phase change layer of this first module and this Unit the second and the 3rd is few.
8. phase-change memory array as claimed in claim 7, wherein the graphical phase change layer of this first module is positioned at ground floor, be positioned at the Unit second of these first module both sides and the graphical phase change layer of Unit the 3rd and lay respectively at the 3rd layer and the 4th layer, the graphical phase change layer that is positioned at Unit the 4th at this first module oblique angle is positioned at the second layer.
9. phase-change memory array as claimed in claim 1, wherein the graphical phase change layer of the graphical phase change layer of this first module and this Unit second differs one deck at least.
10. phase-change memory array as claimed in claim 9, wherein the graphical phase change layer of the graphical phase change layer of this first module and this Unit second differs two-layer at least.
11. phase-change memory array as claimed in claim 1, wherein this first module or this Unit second electrically connect switch element.
12. phase-change memory array as claimed in claim 11, wherein this switch element is vertical diode, bipolar junction transistor or metal oxide semiconductcor field effect transistor.
13. phase-change memory array as claimed in claim 1, wherein the horizontal range of this first module and this Unit second is substantially less than 250nm.
14. phase-change memory array as claimed in claim 1, the wherein interior connection on the top electrode of this first module, long than the interior connection on the top electrode of Unit second.
15. phase-change memory array as claimed in claim 1, wherein this graphical phase change layer comprises the formed phase-transition material of chalcogenide.
16. the manufacture method of a phase-change memory array comprises:
Substrate is provided;
Form the bottom electrode of first module, graphical phase change layer and top electrode are in this substrate; And
Behind the top electrode that forms this first module, form the bottom electrode of Unit second, graphical phase change layer and top electrode.
17. the manufacture method of phase-change memory array as claimed in claim 16, wherein before the bottom electrode that forms this Unit second, form interior connection of part of this Unit second, and the bottom electrode of the interior connection of the part of this Unit second and this first module is to make simultaneously.
18. the manufacture method of phase-change memory array as claimed in claim 17 wherein connects in the part of this Unit second and the bottom electrode of this first module comprises Ti, W, Ta, TiN, TiW, TaN, TaW, TiAl, TiWN, TiAlN or polysilicon.
19. the manufacture method of phase-change memory array as claimed in claim 16, after wherein forming the top electrode of this first module, also be included in the part that forms this first module on the top electrode of this first module and connect, and form the bottom electrode that is positioned at this Unit second part connection down of this Unit second simultaneously.
20. the manufacture method of phase-change memory array as claimed in claim 16 comprises that also forming the part that this first module is positioned on this top electrode simultaneously connects, and is positioned at whole connection under the bottom electrode with this Unit second.
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|---|---|---|---|
| CN200710180155A CN100580944C (en) | 2007-10-10 | 2007-10-10 | Phase-change memory array and manufacturing method thereof |
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| CN200710180155A CN100580944C (en) | 2007-10-10 | 2007-10-10 | Phase-change memory array and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680606A (en) * | 2012-08-29 | 2014-03-26 | 国际商业机器公司 | Semiconductor stack |
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2007
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680606A (en) * | 2012-08-29 | 2014-03-26 | 国际商业机器公司 | Semiconductor stack |
| CN103680606B (en) * | 2012-08-29 | 2016-05-25 | 国际商业机器公司 | Semiconductor stack |
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| CN100580944C (en) | 2010-01-13 |
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