CN114975513A

CN114975513A - Memory and manufacturing method thereof

Info

Publication number: CN114975513A
Application number: CN202210530705.9A
Authority: CN
Inventors: 刘峻; 张恒; 刘国强
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-08-30

Abstract

The embodiment of the invention provides a memory and a manufacturing method thereof, wherein the method comprises the following steps: forming a plurality of first address lines, a plurality of first phase change memory units and a plurality of second address rings which are arranged in a stacked mode; the first address wire extends along a first direction, the second address ring extends along a second direction which is vertical to the first direction, and the first phase change memory unit is vertical to the first direction and the second direction; forming a plurality of second phase change memory cell rings each extending in a second direction on the second address ring; the second address ring and the second phase change memory unit ring are provided with a first end and a second end which are oppositely arranged in the second direction; simultaneously removing the first ends and the second ends of the second address rings and the second phase change memory unit rings to form a plurality of second address lines and a plurality of second phase change memory unit lines; a plurality of second phase change memory cells perpendicular to both the first direction and the second direction are formed using a second phase change memory cell line.

Description

Memory and manufacturing method thereof

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a memory and the memory.

Background

Three-dimensional cross-point memories, such as Phase Change Memories (PCMs), are a Memory technology that uses chalcogenides as the storage medium to store data by using the difference in resistance of materials in different states. PCM has the advantages of bit-addressable, no data loss after power-off, high storage density, fast read-write speed, etc., and is considered as the most promising next-generation memory.

However, in the related art, three-dimensional cross-point memories also present various challenges.

Disclosure of Invention

In order to solve the related technical problems, embodiments of the present invention provide a memory and a method for manufacturing the same.

The embodiment of the invention provides a manufacturing method of a memory, which comprises the following steps:

forming a plurality of first address lines, a plurality of first phase change memory units and a plurality of second address rings which are arranged in a stacked mode; the first address line extends in a first direction, the second address ring extends in a second direction perpendicular to the first direction, and the first phase change memory cell is perpendicular to both the first direction and the second direction;

forming a plurality of second phase change memory cell rings each extending in the second direction on the second address ring; the second address ring and the second phase change memory unit ring are provided with a first end and a second end which are oppositely arranged in the second direction;

simultaneously removing the first ends and the second ends of the second address rings and the second phase change memory unit rings to form a plurality of second address lines and a plurality of second phase change memory unit lines;

and forming a plurality of second phase change memory cells perpendicular to both the first direction and the second direction by using the second phase change memory cell line.

In the above-mentioned scheme, the first and second light sources,

the removing the second address ring and the first end and the second end of the second phase change memory cell ring at the same time to form a plurality of second address lines and a plurality of second phase change memory cell lines includes:

forming a first mask layer on the second phase change memory unit ring;

and performing first etching by using the first mask layer, and removing the second address ring and the first end and the second end of the second phase change memory unit ring at the same time to form a plurality of second address wires and a plurality of second phase change memory unit wires.

In the above scheme, before forming the second phase change memory cell, a third address line material layer is formed on the second phase change memory cell line;

the forming a plurality of second phase change memory cells perpendicular to both the first direction and the second direction using the second phase change memory cell line includes:

performing second etching on the third address line material layer and the second phase change memory cell line to form a third address ring and a second phase change memory cell; the third address ring extends along a first direction and is provided with a third end and a fourth end which are oppositely arranged in the first direction, and the second phase change memory cell is vertical to the first direction and the second direction;

the method further comprises the following steps:

and forming a plurality of third address lines each extending in the first direction on the second phase change memory unit by using the third address ring.

In the above-mentioned scheme, the first step of the method,

the method further comprises the following steps:

forming a third ring of phase change memory cells on the third address ring prior to forming the third address line; the third phase change memory cell ring extends along the first direction and is provided with a third end and a fourth end which are oppositely arranged in the first direction;

the forming a plurality of third address lines each extending in a first direction on the second phase change memory cell using the third address ring includes:

simultaneously removing the third address ring and the third end and the fourth end of the third phase change storage unit ring to form a third address line and a third phase change storage unit line;

the method further comprises the following steps:

and forming a plurality of third phase change memory cells perpendicular to the first direction and the second direction by using the third phase change memory cell line.

In the above-mentioned scheme, the first step of the method,

the method further comprises the following steps:

forming a fourth address line material layer on a third phase change memory cell line before forming the third phase change memory cell;

the forming a plurality of third phase change memory cells perpendicular to both the first direction and the second direction using the third phase change memory cell line includes:

and performing third etching on the fourth address line material layer and the third phase change memory cell line to form a third phase change memory cell and a fourth address ring, wherein the third phase change memory cell is perpendicular to the first direction and the second direction.

In the above scheme, the method further comprises:

forming a fourth ring of phase change memory cells on the fourth address ring after forming the fourth address ring; the fourth address ring and the fourth phase change memory unit ring extend along the second direction and are provided with a first end and a second end which are oppositely arranged in the second direction;

simultaneously removing the first end and the second end of the fourth address ring and the fourth phase change memory unit ring to form a fourth address line and a fourth phase change memory unit line;

and forming a plurality of fourth phase change memory cells perpendicular to the first direction and the second direction by using the fourth phase change memory cell line, and forming a plurality of fifth address lines extending along the first direction on the fourth phase change memory cells.

In the above scheme, the method further comprises:

forming a sixth address ring on the second address ring before forming a plurality of second phase change memory cell rings each extending in the second direction on the second address ring; the sixth address ring extends along the second direction and has a first end and a second end which are oppositely arranged in the second direction;

the forming a plurality of second phase change memory cell rings each extending in the second direction on the second address ring includes:

forming a plurality of second phase change memory cell rings each extending in the second direction on the sixth address ring;

and simultaneously removing the first ends and the second ends of the second address ring, the sixth address ring and the second phase change memory unit ring to form a second address line, a sixth address line and a second phase change memory unit line.

In the above solution, the forming a plurality of first address lines, a plurality of first phase change memory cells, and a plurality of second address rings includes:

forming a first address line material layer and a first phase change memory unit material layer which are arranged in a stacked mode;

performing fourth etching on the first address line material layer and the first phase change memory unit material layer, and dividing the first address line material layer and the first phase change memory unit material layer into a first address ring and a first phase change memory unit ring which extend along a first direction; the first address ring and the first phase change memory cell ring are provided with a third end and a fourth end which are oppositely arranged in the first direction;

simultaneously removing the third end and the fourth end of the first address ring and the first phase change memory unit ring to form a first address line and a first phase change memory unit line;

forming a second address line material layer on the first phase change memory cell line;

and performing fifth etching on the second address line material layer and the first phase change memory cell line to form a second address ring and a first phase change memory cell.

In the above scheme, two adjacent second address rings in the plurality of second address rings are separated by a first distance along the first direction; adjacent two second address lines of the plurality of second address lines are a second distance apart along the first direction;

the first distance is twice the second distance.

In the above scheme, the first phase change memory cell includes a first electrode, a gate element, a second electrode, a phase change memory element, and a third electrode, which are stacked.

The embodiment of the invention also provides a memory which is formed by adopting the method in any scheme of the schemes.

The manufacturing method of the memory provided by the embodiment of the invention comprises the following steps: forming a plurality of first address lines, a plurality of first phase change memory units and a plurality of second address rings which are arranged in a stacked mode; the first address line extends in a first direction, the second address ring extends in a second direction perpendicular to the first direction, and the first phase change memory cell is perpendicular to both the first direction and the second direction; forming a plurality of second phase change memory cell rings each extending in the second direction on the second address ring; the second address ring and the second phase change memory unit ring are provided with a first end and a second end which are oppositely arranged in the second direction; simultaneously removing the first ends and the second ends of the second address rings and the second phase change memory unit rings to form a plurality of second address lines and a plurality of second phase change memory unit lines; and forming a plurality of second phase change memory cells perpendicular to both the first direction and the second direction by using the second phase change memory cell line. In the embodiment of the invention, after the second address ring and the second phase change memory unit ring are formed, the first end and the second end of the second address ring and the second phase change memory unit ring are removed at the same time to form a plurality of second address lines and a plurality of second phase change memory unit lines, and compared with the method of respectively removing the first end and the second end of the second address ring and the first end and the second end of the second phase change memory unit ring, the process steps can be simplified; and meanwhile, the second address ring and the first end and the second end of the second phase change memory unit ring are removed, so that the times of removing the first end and the second end can be reduced, the damage caused by removing the connecting parts of the first end and the second end to the address lines is reduced, the process cost can be saved, and the performance of the memory can be improved.

Drawings

FIG. 1 is a partial three-dimensional architecture of a phase change memory according to an embodiment of the invention;

FIG. 2a is a top view of a bit line layer structure of a phase change memory according to an embodiment of the present invention;

FIG. 2b is a top view of a word line layer structure of a phase change memory according to an embodiment of the present invention;

FIG. 3a is a schematic top view of a phase change memory according to an embodiment of the invention;

FIG. 3b is an enlarged top view of a phase change memory according to an embodiment of the invention;

FIG. 3c is a partial Z-direction schematic diagram of a phase change memory cell array with a four-layer stack according to an embodiment of the present invention;

fig. 4a to fig. 4h are schematic perspective views illustrating an implementation process of a method for manufacturing a phase change memory according to an embodiment of the invention;

FIGS. 5a to 5f are schematic cross-sectional views illustrating an implementation process of a method for fabricating a phase change memory according to an embodiment of the invention;

FIG. 6 is a flowchart illustrating a method for manufacturing a phase change memory according to an embodiment of the invention;

FIGS. 7a to 7m are schematic perspective views illustrating an implementation process of another phase change memory manufacturing method according to an embodiment of the invention;

fig. 8a to 8l are schematic cross-sectional views illustrating an implementation process of another method for fabricating a phase change memory according to an embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …", "directly adjacent to … …", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

The Memory according to the embodiment of the present invention may include a Memory including bit lines, word lines and Memory cells that are staggered horizontally and vertically, and includes, but is not limited to, a phase change Memory, a Ferroelectric Memory (FeRAM), a magnetic Memory (MRAM), a Resistive Random Access Memory (RRAM), and the like. Hereinafter, the phase change memory will be described as an example.

Fig. 1 is a schematic diagram of a partial three-dimensional architecture of a phase change memory according to an embodiment of the invention. As shown in fig. 1, the phase change memory includes a first address line 101, a first phase change memory unit 102, a second address line 103, a second phase change memory unit 104, and a third address line 105, which are stacked in sequence from bottom to top; the first phase change memory unit 102 and the second phase change memory unit 104 each include a first electrode 1021, a gating element 1022, a second electrode 1023, a phase change memory element 1024, and a third electrode 1025, which are sequentially stacked from bottom to top. The phase change memory may be based on heating and quenching the phase change memory element 1024 to cause the phase change memory element 1024 to switch between the amorphous and crystalline states, thereby storing data using the difference between the resistivity of the phase change memory element 1024 in the amorphous state and the resistivity of the crystalline state.

As can be seen from fig. 1: the first address line 101 is parallel to the third address line 105, and both the first address line 101 and the third address line 105 are perpendicular to the second address line 103; meanwhile, the first phase change memory cell 102 is perpendicular to both the first address line 101 and the second address line 103, and the second phase change memory cell 104 is perpendicular to both the second address line 103 and the third address line 105. The first address Line 101 and the third address Line 105 may be Bit lines (expressed in english as Bit Line), and the second address Line 103 may be Word lines (expressed in english as Word Line). In practical application, the selection of the phase change memory cell connected with the selected word line and the selected bit line is realized through the activation of the selected word line and the selected bit line.

In practical applications, the first address Line 101, the second address Line 103, and the third address Line 105 are typically formed of lines of equal width (L/S, Line/Space) of 20nm/20nm formed after a patterning process. Considering that the distribution density of address lines (word lines and bit lines) in a memory is generally designed to be relatively high, i.e. the gaps between word lines or between bit lines are small, the resolution of a general lithography machine is not sufficient to directly form a stripe pattern with a small gap (i.e. a stripe pattern with a small gap is used as a mask for word lines or bit lines). In some embodiments, in the process of forming the phase change memory address lines, a Double Self-aligned Double Patterning (SADP) process may be used to form the address lines.

The specific process of twice self-aligning the double pattern may include a series of processes to obtain a plurality of bit line loops of the middle state like the zigzag shape before cutting as shown in fig. 2a and a plurality of word line loops of the middle state like the zigzag shape before cutting as shown in fig. 2 b; next, both sides of the bit line loop of each loop-like intermediate state are cut, for example, at the position of the dotted line in fig. 2a, to form two adjacent bit lines, and both sides of the word line loop of each loop-like intermediate state are cut, for example, at the position of the dotted line in fig. 2b, to form two adjacent word lines.

That is, in the related art, due to the insufficient resolution of photolithography, a mask that can be used to form the final word line and bit line is not directly formed, but a structure similar to a zigzag is first obtained as a word line ring or a bit line ring in an intermediate state, and then both sides of the structure of the zigzag are cut to obtain the final word line or bit line, thereby reducing the need for resolution. However, when the word line loop or the bit line loop in the intermediate state is cut, problems may be caused, for example, the extra cutting process not only increases the manufacturing cost of the memory, but also may cause damage to the word line connection (here, the connection may be expressed as Contact, and the connection may also be referred to as a Contact) and the bit line connection during the cutting process.

FIG. 3a is a schematic top view of a phase change memory according to an embodiment of the invention; FIG. 3b is an enlarged top view of a phase change memory according to an embodiment of the invention; FIG. 3c is a partial view of a phase change memory cell array with a four-layer stack in the Z-direction according to an embodiment of the present invention. As can be seen from fig. 3a to 3c, a plurality of connecting portions for connecting word lines and bit lines are distributed in a phase change memory according to an embodiment of the present invention.

Fig. 4a to 4h are schematic perspective views illustrating an implementation process of a method for manufacturing a memory according to an embodiment of the present invention, and fig. 5a to 5f are schematic cross-sectional views illustrating an implementation process of a method for manufacturing a memory according to an embodiment of the present invention. The following describes a method for manufacturing a memory according to an embodiment of the present invention with reference to the accompanying drawings.

as shown in fig. 4a, performing a fourth etching on the first address line material layer and the first phase change memory cell material layer, so as to divide the first address line material layer and the first phase change memory cell material layer into a first address ring 101 'and a first phase change memory cell ring 102' extending along the first direction; the first address ring 101 'and the first phase change memory cell ring 102' have a third end and a fourth end which are oppositely arranged in the first direction;

as shown in fig. 4b, the third end and the fourth end of the first address ring 101 ', the first phase-change memory cell ring 102' are removed at the same time to form a first address line 101, a first phase-change memory cell line 102 ";

forming a second address line material layer over the first phase change memory cell line 102 ";

as shown in fig. 4c and fig. 5a, the second address line material layer and the first phase-change memory cell line 102 ″ are subjected to a fifth etching process to form a second address ring 103' and a first phase-change memory cell 102. The first address line 101 extends in a first direction, the second address ring 103' extends in a second direction perpendicular to the first direction, and the first phase change memory cell 102 is perpendicular to both the first direction and the second direction; the second address ring 103' has a first end and a second end oppositely arranged in the second direction;

as shown in fig. 4d and fig. 5b, the first end and the second end of the second address ring 103' are removed to form a plurality of second address lines 103;

as shown in fig. 4e and 5c, a plurality of second phase change memory cell rings 104' each extending in the second direction are formed on the second address line 103; the second phase change memory cell rings 104' each have a first end and a second end oppositely arranged in the second direction;

as shown in fig. 4f and fig. 5d, the first ends and the second ends of the second phase change memory cell rings 104' are removed to form a plurality of second phase change memory cell lines 104 ";

a plurality of second phase change memory cells 104, which are perpendicular to both the first direction and the second direction, are formed using the second phase change memory cell lines 104 ″, and a plurality of third address lines 105, which extend in the first direction, are formed on the second phase change memory cells 104.

In some embodiments, the forming a plurality of second phase change memory cells 104 perpendicular to both the first direction and the second direction using the second phase change memory cell lines 104 ″ and forming a plurality of third address lines 105 extending in the first direction on the second phase change memory cells 104 includes:

forming a third layer of address line material over the second phase change memory cell line 104 ";

as shown in fig. 4g and fig. 5e, a second etching is performed on the third address line material layer and the second phase change memory cell line 104 ″ to form a third address ring 105' and a second phase change memory cell 104; the third address ring 105' extends along a first direction and has a third end and a fourth end opposite to each other in the first direction, and the second phase change memory cell 104 is perpendicular to both the first direction and the second direction;

a plurality of third address lines 105 each extending in the first direction are formed on the second phase change memory cell 104 using the third address ring 105'.

In some embodiments, the forming a plurality of third address lines 105 each extending in the first direction on the second phase change memory cells 104 by using the third address ring 105' includes:

as shown in fig. 4h and 5f, the third and fourth ends of the third address ring 105' are removed, and a plurality of third address lines 105 extending along a first direction are formed on the second phase change memory cell 104;

the method further comprises the following steps:

forming a third phase change memory cell loop 106' on the third address line 105; the third phase change memory cell ring 106' extends along the first direction and has a third end and a fourth end oppositely arranged in the first direction;

removing the third and fourth ends of the third phase change memory cell ring 106' to form a third phase change memory cell line 106 ";

a plurality of third phase change memory cells 106, which are perpendicular to both the first direction and the second direction, are formed using the third phase change memory cell lines 106 ″, and a plurality of fourth address lines 107, which each extend in the second direction, are formed on the third phase change memory cells 106.

The phase change memory further includes a plurality of connection portions connected to the first address line 101, the second address line 103, the third address line 105, and the fourth address line 107. Phase change memory requires that each of a plurality of phase change memory cells be coupled to an address line adjacent the respective phase change memory cell. In order to access the phase change memory cell, each address line needs to be connected to the peripheral circuit through a corresponding connection portion.

It can be understood that in the method for manufacturing the phase change memory provided in the above embodiment, the first address ring 101 ', the first phase change memory cell ring 102', the second address ring 103 ', the second phase change memory cell ring 104', the third address ring 105 ', the fourth memory cell ring, and the fourth address ring 107' of the middle state similar to the zigzag shape are formed first, and then both sides of the zigzag structure are cut to obtain the final address line and the phase change memory cell. Since the first end, the second end, the third end and the fourth end need to be removed by performing a plurality of cutting processes, and the number of stacked layers of the three-dimensional phase change memory increases, the number of required cutting processes also increases, and the increase of the number of cutting processes is not only an increase of one process, but also causes additional defect problems, such as damage to the connection portion of the address line.

Based on the above problem, an embodiment of the present invention provides another method for manufacturing a memory, where fig. 6 is a schematic flow chart illustrating an implementation of the method for manufacturing a memory, and as shown in fig. 6, the method for manufacturing a memory includes:

step 601: forming a plurality of first address lines 101, a plurality of first phase change memory cells 102, and a plurality of second address rings 103' in a stacked arrangement; the first address line 101 extends in a first direction, the second address ring 103' extends in a second direction perpendicular to the first direction, and the first phase change memory cell 102 is perpendicular to both the first direction and the second direction;

step 602: forming a plurality of second phase change memory cell rings 104 'each extending in the second direction on the second address ring 103'; the second address ring 103 'and the second phase change memory cell ring 104' each have a first end and a second end that are oppositely arranged in the second direction;

step 603: simultaneously removing the second address ring 103 ', the first end and the second end of the second phase change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase change memory cell lines 104 ";

step 604: a plurality of second phase change memory cells 104 perpendicular to both the first direction and the second direction are formed using the second phase change memory cell lines 104 ".

Fig. 7a to 7m are schematic perspective views illustrating an implementation process of a method for manufacturing a memory according to an embodiment of the invention. FIGS. 8a to 8l are schematic cross-sectional views illustrating an implementation process of a method for manufacturing a memory according to an embodiment of the invention. The following describes the manufacturing process of the memory according to the embodiment of the invention in detail with reference to fig. 7a to 7m and fig. 8a to 8 l.

In step 601, referring to fig. 7 a-7 c, a plurality of first address lines 101, a plurality of first phase change memory cells 102, and a plurality of second address rings 103' are formed.

In some embodiments, the forming the plurality of first address lines 101, the plurality of first phase change memory cells 102, the plurality of second address rings 103' includes:

as shown in fig. 7a, performing a fourth etching on the first address line material layer and the first phase change memory cell material layer, so as to divide the first address line material layer and the first phase change memory cell material layer into a first address ring 101 'and a first phase change memory cell ring 102' extending along the first direction; the first address ring 101 'and the first phase change memory cell ring 102' have a third end and a fourth end which are oppositely arranged in the first direction;

as shown in fig. 7b, the third terminal and the fourth terminal of the first address ring 101 ', the first phase-change memory cell ring 102' are removed at the same time to form a first address line 101, a first phase-change memory cell line 102 ";

as shown in fig. 7c and fig. 8 a-8 b, a fifth etching process is performed on the second address line material layer and the first phase-change memory cell line 102 ″ to form a second address ring 103' and a first phase-change memory cell 102.

Here, a constituent material of the first address line material layer includes a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or polysilicon, etc.

In some embodiments, the first phase change memory cell 102 includes a first electrode, a gate element, a second electrode, a phase change memory element, and a third electrode, which are stacked.

The following second phase change memory cell 104, third phase change memory cell 106, and fourth phase change memory cell 108 may each include a first electrode, a gate element, a second electrode, a phase change memory element, and a third electrode that are stacked.

Here, the lamination may be from top to bottom on the substrate, or from bottom to top on the substrate.

Here, forming the first phase change memory cell material layer includes: and forming a first electrode material layer, a gating material layer, a second electrode material layer, a phase change storage material layer and a third electrode material layer which are arranged in a stacked mode.

In practical applications, the first address line material Layer, the first electrode material Layer, the gate material Layer, the second electrode material Layer, the phase change memory material Layer, and the third electrode material Layer may be formed on the surface of the substrate by a Deposition process, including, but not limited to, a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

Here, the constituent material of the substrate may include a semiconductor material such as silicon, germanium, or gallium arsenide, or the like.

Here, the constituent materials of the gate layer may include: threshold selection switch (OTS) materials such as zinc telluride (ZnaTeb), germanium telluride (GeaTeb), niobium oxide (NbaOb), or silicon arsenic telluride (SiaAsbTec). The composition materials of the phase-change memory layer may include: chalcogenide-based alloys, such as, but not limited to, GST (Ge-Sb-Te) alloys. The constituent material of the phase-change memory layer may also include any other suitable phase-change material. When the phase change memory layer undergoes a phase change, the resistance of the phase change memory layer changes. The phase change memory can store data according to the resistance state change of the phase change memory layer.

Here, the material of the electrode may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), carbon (C), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes comprises carbon, such as amorphous carbon.

The first direction and the second direction may be directions parallel to the substrate. In practical applications, the first direction may be understood as an X-axis direction shown in the drawings of the present invention, and it is understood that the first direction is not limited to the X-axis direction. The second direction may be understood as a Y-axis direction shown in the drawings of the present invention, and it is understood that the second direction is not limited to the Y-axis direction.

In practical applications, the fourth etching and the fifth etching include, but are not limited to, dry plasma etching.

Therein, in step 602, a second phase change memory cell ring 104' is mainly formed.

As shown in fig. 7d and 8c, a second phase change memory cell ring 104 'is formed on the second address ring 103'.

In practical applications, the forming the second phase change memory cell ring 104 'on the second address ring 103' includes forming a second phase change memory cell material layer on the second address ring 103 ', and performing an etching process on the second phase change memory cell material layer to form the second phase change memory cell ring 104'.

In some embodiments, the method further comprises:

forming a sixth address ring 1010 'on the second address ring 103' before forming a plurality of second phase change memory cell rings 104 'each extending in the second direction on the second address ring 103'; the sixth address ring 1010' extends along the second direction and has a first end and a second end oppositely arranged in the second direction;

the forming of a plurality of second phase change memory cell rings 104 'each extending in the second direction on the second address ring 103' includes:

forming a plurality of second phase change memory cell rings 104 'each extending in the second direction on the sixth address ring 1010';

the simultaneously removing the first ends and the second ends of the second address ring 103 'and the second phase change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase change memory cell lines 104 ″ includes:

and simultaneously removing the first end and the second end of the second address ring 103 ', the sixth address ring 1010 ' and the second phase change memory cell ring 104 ' to form a second address line 103, a sixth address line 1010 and a second phase change memory cell line 104 ".

In step 603, as shown in fig. 7e and fig. 8d, a plurality of second address lines 103 and a plurality of second phase change memory cell lines 104 ″ are mainly formed.

Here, the second phase change memory cell ring 104 'may be understood as a second phase change memory cell ring 104' having a hollow ring structure, and the second phase change memory cell line 104 "may be understood as a second phase change memory cell line 104" having a solid line structure. Specifically, the second phase change memory cell ring 104 ' may be understood with reference to fig. 7d, and the second phase change memory cell ring 104 ' is a hollow ring-shaped structure, for example, the second phase change memory cell ring 104 ' may be a rectangular ring having two long sides and two short sides, when the second phase change memory cell ring 104 ' is cut to form the second phase change memory cell line 104 ″, the two short sides are removed, and portions of the two long sides close to the two short sides are removed at the same time, and the remaining two long sides are two linear structures parallel to each other, that is, the second phase change memory cell line 104 ″ shown in fig. 7e is formed, and one second phase change memory cell ring 104 ' may form two second phase change memory cell lines 104 ″. It should be noted that the second phase change memory cell loop 104 'is a rectangular loop, which is only an exemplary illustration and is not used to limit the shape of the second phase change memory cell loop 104' in the present invention. The "ring" and "line" in other parts of the embodiments of the present invention can also be understood by referring to the above explanation of the second phase change memory cell ring 104' and the second phase change memory cell line 104 ".

In some embodiments, the removing the first ends and the second ends of the second address ring 103 ', the second phase change memory cell ring 104' simultaneously to form a plurality of second address lines 103 and a plurality of second phase change memory cell lines 104 ″ includes:

forming a first mask layer on the second phase change memory cell ring 104';

and performing a first etching by using the first mask layer, and removing the first ends and the second ends of the second address ring 103 ', the second phase change memory cell ring 104' to form a plurality of second address lines 103 and a plurality of second phase change memory cell lines 104 ″.

Here, the first mask layer may include a photoresist mask or a hard mask patterned based on a photolithography mask, for example, silicon nitride, etc.

It can be understood that, here, the second address ring 103 'and the first end and the second end of the second phase change memory unit ring 104' are removed simultaneously, and the second address ring 103 'and the second phase change memory unit ring 104' are not removed separately, so that the process steps can be saved, the amount of the mask layer can be saved, the process window can be improved, and the damage to the connection portion of the address line can be reduced.

In some embodiments, two adjacent second address rings 103 'of the plurality of second address rings 103' are a first distance apart along the first direction; adjacent two second address lines 103 of the plurality of second address lines 103 are a second distance apart along the first direction;

the first distance is twice the second distance.

It is understood that after removing the first end and the second end of the second address ring 103 ', one second address ring 103' forms two second address lines 103, and the number of the second address lines 103 is twice the number of the second address rings 103 ', so that the distance between adjacent second address rings 103' is twice the distance between adjacent second address lines 103, and the pitch between each word line and each bit line is exactly the same.

In step 604, the second phase change memory cell 104 and the third address line 105 are mainly formed.

In some embodiments, a third address line material layer is formed over the second phase change memory cell line 104 ″ prior to forming the second phase change memory cell 104;

the forming of a plurality of second phase change memory cells 104 perpendicular to both the first direction and the second direction using the second phase change memory cell lines 104 ″ includes:

as shown in fig. 7f and fig. 8e, a second etching is performed on the third address line material layer and the second phase change memory cell line 104 ″ to form a third address ring 105' and a second phase change memory cell 104; the third address ring 105' extends along a first direction and has a third end and a fourth end opposite to each other in the first direction, and the second phase change memory cell 104 is perpendicular to both the first direction and the second direction;

the method further comprises the following steps:

a plurality of third address lines 105 each extending in the first direction are formed on the second phase change memory cells 104 using the third address ring 105'.

In some embodiments, the method further comprises:

as shown in fig. 7g and 8f, before the third address line 105 is formed, a third phase change memory cell loop 106 'is formed on the third address loop 105'; the third phase change memory cell loop 106' extends along the first direction and has a third end and a fourth end oppositely arranged in the first direction;

the forming of the plurality of third address lines 105, each extending in the first direction, on the second phase change memory cells 104 using the third address ring 105' includes:

as shown in fig. 7h and fig. 8g, the third address ring 105 ', the third phase change memory cell ring 106', the third end and the fourth end are removed at the same time to form a third address line 105, a third phase change memory cell line 106 ";

the method further comprises the following steps:

a plurality of third phase change memory cells 106 perpendicular to both the first direction and the second direction are formed using the third phase change memory cell lines 106 ".

In some embodiments, the method further comprises:

forming a fourth address line material layer on a third phase change memory cell line 106 ″ before forming the third phase change memory cell 106;

the forming a plurality of third phase change memory cells 106 perpendicular to the first direction and the second direction using the third phase change memory cell lines 106 ″ includes:

as shown in fig. 7i and 8h, a third etching is performed on the fourth address line material layer and the third phase change memory cell line 106 ″ to form a third phase change memory cell 106 and a fourth address ring 107', and the third phase change memory cell 106 is perpendicular to both the first direction and the second direction.

In some embodiments, the method further comprises:

as shown in fig. 7j and 8i, after the fourth address ring 107 ' is formed, a fourth phase change memory cell ring 108 ' is formed on the fourth address ring 107 '; the fourth address ring 107 'and the fourth phase change memory cell ring 108' both extend along the second direction and have a first end and a second end that are oppositely arranged in the second direction;

as shown in fig. 7k and fig. 8j, the first end and the second end of the fourth address ring 107 'and the fourth phase change memory cell ring 108' are removed at the same time to form a fourth address line 107 and a fourth phase change memory cell line 108 ";

as shown in fig. 7l to 7m and fig. 8k to 8l, a plurality of fourth phase change memory cells 108 perpendicular to both the first direction and the second direction are formed using the fourth phase change memory cell lines 108 ″, and a plurality of fifth address lines 109 each extending in the first direction are formed on the fourth phase change memory cells 108.

In some embodiments, the forming a plurality of fourth phase change memory cells 108 perpendicular to both the first direction and the second direction using the fourth phase change memory cell lines 108 ″ and forming a plurality of fifth address lines 109 extending in the first direction on the fourth phase change memory cells 108 includes:

forming a fifth layer of address line material over the fourth phase change memory cell line 108 ";

etching the fifth address line material layer and the fourth phase change memory cell line 108 ″ to form a fifth address ring 109' and a fourth phase change memory cell 108; the fifth address ring 109' extends in a first direction and has a third end and a fourth end oppositely disposed in the first direction;

the third and fourth ends of the fifth address ring 109' are removed to form a fifth address line 109.

It can be understood that, in the embodiment of the present invention, through common adjustment of layout design and process, the first end and the second end of the second address ring 103 'and the second phase change memory cell ring 104' are removed at the same time, the third end and the fourth end of the third address ring 105 'and the third phase change memory cell ring 106' are removed at the same time, and the first end and the second end of the fourth address ring 107 'and the fourth phase change memory cell ring 108' are removed at the same time, so that three masks can be omitted, three processes for removing the ring-shaped end portions are omitted at the same time, the number of the omitted photoresist is correspondingly increased with different increases of the number of stacked layers of the three-dimensional phase change memory, a process window is also increased while the photoresist is saved, and damage to the connection portion of the address line is reduced.

Based on the manufacturing method of the memory, an embodiment of the invention further provides a memory, and the memory is formed by adopting the method in any embodiment of the above embodiments.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention. The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided by the present invention can be combined arbitrarily without conflict to obtain new method embodiments.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.

Claims

1. A method for manufacturing a memory, comprising:

2. The method of claim 1,

the removing the second address ring and the first end and the second end of the second phase change memory unit ring at the same time to form a plurality of second address lines and a plurality of second phase change memory unit lines includes:

forming a first mask layer on the second phase change memory unit ring;

and performing first etching by using the first mask layer, and removing the second address ring and the first end and the second end of the second phase change memory unit ring at the same time to form a plurality of second address lines and a plurality of second phase change memory unit lines.

3. The method of claim 1, wherein prior to forming the second phase change memory cell, forming a layer of a third address line material over the second phase change memory cell line;

the method further comprises the following steps:

4. The method of claim 3,

the method further comprises the following steps:

5. The method of claim 4,

the method further comprises the following steps:

and carrying out third etching on the fourth address line material layer and the third phase change memory unit line to form a third phase change memory unit and a fourth address ring, wherein the third phase change memory unit is vertical to the first direction and the second direction.

6. The method of claim 5,

the method further comprises the following steps:

7. The method of claim 1, further comprising:

8. The method of claim 1, wherein forming a plurality of first address lines, a plurality of first phase change memory cells, a plurality of second address rings comprises:

9. The method of claim 1, wherein two adjacent second address rings of the plurality of second address rings are a first distance apart along the first direction; adjacent two second address lines of the plurality of second address lines are a second distance apart along the first direction;

the first distance is twice the second distance.

10. The method of claim 1, wherein the first phase change memory cell comprises a first electrode, a gating element, a second electrode, a phase change memory element, and a third electrode arranged in a stack.

11. A memory formed by the method of any of claims 1-10.