CN101405868A - Monolithic integration of enhancement- and depletion-mode AlGaN/GaN HFET - Google Patents

Abstract

Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

Description

The monolithic of enhancement mode and depletion-mode AlGaN/GaN HFET is integrated

The cross reference of related application

The application requires the priority of U.S. Provisional Patent Application of submitting on November 29th, 2,005 60/740256 and the U.S. Provisional Patent Application of submitting on December 8th, 2,005 60/748339, by reference the two is incorporated into this.

Background of invention and general introduction

The application relates to the single chip integrated method that is used for enhancing and depletion type HFET (" HFET "), specifically, relates to and adopts the integrated making aluminium gallium nitride alloy/gallium nitride of this monolithic (" AlGaN/GaN ") HFET.

For example in conjunction with those III group-III nitride (" the III-N ") compound semiconductor of AlGaN/GaN have have broad-band gap, the advantage of high breakdown field and big thermal conductivity, they can be the design of hetero-structure field effect transistor and utilize the application of HFET to bring remarkable benefit.Because their high power handling ability, AlGaN/GaN HFET can be used for RF power amplifier and high power switch.But, adopt most of power amplifiers and the switch of AlGaN/GaN HFET mainly to comprise depletion type (" D type ") HFET as building block.Because D type HFET is threshold voltage (V _Th) be the transistor of negative value, so D type HFET needs positive and negative voltage biasing with conducting with end.If it is available that enhancement mode (" E type ") HFET may become, then only need positive voltage source, thereby simplify circuit and reduce cost for circuit application.

In addition, because based on the broad-band gap of the semi-conducting material of GaN, AlGaN/GaN HFET can hot operation (may up to 600 ℃), thereby is applicable to the high temperature integrated circuit, required integrated circuit during for example aviation and automobile are used.In addition, for the logical circuit based on HFET, the FET logic that directly is coupled (" DCFL ") is a characteristic with simple configuration.In DCFL, E type HFET is as driver, and D type HFET is then as load.

Notice that when zero gate bias, D type HFET can conduction current and is called " normal open ", and for E type HFET, transistor non-conducting electric current also is called " normal off ".

Fig. 1 illustrates and adopts thin AlGaN barrier layer 12, the E type HFET 10 of Doped GaN layer 18 and the substrate layer 20 that for example can be made by sapphire, silicon or carborundum not.By means of the Schottky barrier 14 between gate metal 16 and the AlGaN potential barrier, as long as the AlGaN potential barrier is enough thin, the raceway groove between source electrode 22 and the drain electrode 24 just can be by pinch off when zero gate bias.But the E type HFET of Zhi Zuoing has bad performance characteristics by this way, for example low mutual conductance, big conducting resistance and high knee voltage.This inserts resistance by height and causes.As shown in Figure 1, because thin AlGaN potential barrier, the access zone between grid and the source electrode also has extremely low carrier density.Therefore, inserting the zone also is the E type, and it needs positive bias with conducting.To have the low E type HFET that inserts resistance in order producing, to need " autoregistration " manufacture craft, wherein have only the channel region below gate electrode directly to be only the E type.Noting, is not that self aligned grid needs crossover, and this increases device size and stray capacitance.

Existing some trials aspect the making of E type AlGaN/GaN High Electron Mobility Transistor (" HEMT ").Notice that term " HEMT " and " HFET " are synonyms.The both be comprise knot between two kinds of materials with different band gap, as the field-effect transistor of heterostructure as raceway groove.The effect of this heterostructure is to set up the thin layer that Fermi energy wherein is higher than conduction band, thereby for raceway groove provides extremely low resistance, for example " high electron mobility ".As other all types of FET, be applied to the conductance of the voltage change thin layer on the grid.

Utilize thin AlGaN potential barrier (10nm), people such as Khan have made the E type HEMT of the peak value mutual conductance with 23mS/mm.

" enhanced AlGaN/GaNHFET " (in April, 2000 of people such as Hu with PN junction grid of selective growth, IEE Electronics Letters, Vol.36, No.8, the 753-754 page or leaf) reports another trial of making the E type HFET in the AlGaN/GaN system, by reference it intactly has been incorporated into this.In this document, adopt the P/N knot grid of selective growth.The P type layer of selective growth can improve the electromotive force of raceway groove, thereby exhausts the charge carrier from raceway groove when zero gate bias.But this method is not self aligned, and does not still have to solve the big problem that inserts resistance.

People such as Moon have reported the another kind of making the E type HFET in the AlGaN/GaN system and have attempted, and he adopts inductively coupled plasma reactive ion etching (" ICP-RIE ") to carry out the grid groove etching." sub-micron enhanced AlGaN/GaNHEMT " (in June, 2002, Digest of 60th Device Research Conference, 23-24 page or leaf) referring to people such as Jeong S.Moon intactly is incorporated into this with it by reference.

People such as Kumar adopt similar approach.Notice that the AlGaN potential barrier under the grid can be come attenuation by groove etching, threshold voltage then rise on the occasion of.But ICP-RIE may cause badly damaged to the AlGaN potential barrier, and produces the grid leakage current that increases.In order to eliminate the damage that ICP-RIE causes, the groove etching pattern must be eliminated, and carries out high temperature (about 700 ℃) annealing afterwards again.Like this, gate pattern must be set up once more by photoetching process, and this can't accurately align with the groove etching window that is before produced in the grid groove stage.Therefore, dual photoetching of this process need or aligning are not self aligned.Covered fully by gate electrode in order to ensure notch window, gate electrode need be greater than notch window, thereby obtains bigger grid size, as previously described.Another problem relevant with the ICP-RIE etching is the bad consistency of etch depth, and this is nonconforming for integrated circuit, because it has a strong impact on the consistency of threshold voltage.

Another kind method adopts gate metal, for example platinum (" Pt ") or molybdenum (" Mo "), and they have bigger work function, and have the tendency that reacts with the III/V compound semiconductor.(work function represents to discharge the energy that the electron institute needs when electronics passes through the metal surface.) for example, be used to realize E type indium arsenide aluminium/InGaAsP HFET in the past based on the buried grid technology of Pt.For AlGaN/GaN HFET, people such as Endoh are from having the D type HFET establishment E type HFET based on the gate electrode of Pt.By high temperature grid annealing, the gate metal front end can be made into and be absorbed in the AlGaN potential barrier, and reduce effectively potential barrier thickness and threshold voltage raise on the occasion of.This method requires D type HFET to have threshold voltage near zero because the Pt grid to be absorbed in the degree of depth restricted.But,, wish that D type HFET (as load) has the bigger negative threshold voltage of amplitude for single chip integrated E/D type HFET circuit.

The title of authorizing people such as Miroslav Micovic disclose a kind of grid groove technology for the U.S. Patent application 20030218183 of " high-power low-noise microwave GaN hetero-structure field effect transistor ", as a kind of existing process technology of making E type HFET.But in AlGaN/GaN HFET, owing to lack effective Wet-type etching technology, groove etching is undertaken by dry-etching.For example, as previously mentioned, ICP-RIE is used for groove etching, wherein is accompanied by the badly damaged and defective of device.

A kind of utilization is used for making technology based on the method for the E type HFET of the material system of GaN having the gate metal of work function greatly to the title of authorizing people such as Yoshimi Yamashita for the U.S. Patent application 2005059197 of " semiconductor device and manufacture method thereof " disclose.But, do not find that any metal has the work function greater than 1 electron-volt (" eV ").Therefore, make E type HFET, need present the sample of the threshold voltage of more approaching zero volt for the method that adopts people such as Yamashita.This is not suitable for the integrated of E type and D type HEMT, and they all are the DCFL circuits needed.

The grid groove technology also is used for realizing that the monolithic of the E/DHFET in the AlGaN/GaN heterostructure is integrated always.As mentioned above, this method requires the dual masks grid technology, compares with single mask grid technology, introduces extra procedure of processing and cost.

Realize high density and the high consistency of E/D HEMT in integrated, three-dimensional table top has applied strict restriction to photoetching and interconnection.Therefore, as what see, need a kind of planar technique from the successful development of commercial GaAs MESFET integrated circuit.

In addition, owing to lack P raceway groove AlGaN/GaN HEMT, can't realize at present to similar circuit arrangement based on CMOS.Utilizing N raceway groove HEMT, is that direct coupled field effect transistor (" the FET ") logic (DCFL) of characteristics provides the simplest circuit arrangement shown in Figure 1A, with integrated enhancement/depletion-type (" E/D type ") HEMT.

Owing to lack the compatible integrated technique of D type and E type AlGaN/GaNHEMT so far, people such as Hussain trade off, and 31 grades of ring oscillators that use full D type HEMT technology and buffering FET logic (" BFL ") configuration to realize inverter and comprise 217 transistors and two negative voltage power supplies.

Damage based on Cl according to low ₂The ICP-RIE technology, people such as Micovic use the technology of two rank grid groove etchings, and using plasma strengthens chemical vapor deposition (" PECVD ") grown silicon nitride and makes E type GaN HEMT as the gate metal deposition mask, and they and D type GaN HEMT are integrated.For 31 grades of DCFL ring oscillators with 0.15-μ m grid technology, they show the propagation delay of 127ps/ level on the drain bias of 1.2V.

The monolithic of enhancement mode and depletion-mode AlGaN/GaN HFET is integrated

The application proposes to have single chip integrated device, circuit and the system of D type and E type HFET and the method that is used to make up them.In a class embodiment, the plasma treatment that forms pattern is used for fixed charge is introduced the only wide bandgap material of the grid below of a part of device.In this example, D type HFET be defined and the barrier layer of grid below without plasma treatment, and E type HFET be defined and the barrier layer of grid below through plasma treatment.

In various embodiments, disclosed innovation provides one or more in the following at least advantage:

Enhancement mode and the depletion-mode AlGaN/GaN of complete circuit that allows to be used for to realize DCFL or other logic family is integrated with the monolithic of EMT.

The Alignment Method of making the E/D type AlGaN/GaN HEMT with low on-resistance, low knee voltage and high extrinsic mutual conductance is provided.

The method that adopts the microelectronics manufacturing equipment that easily obtains to make autoregistration E/D type HFET is provided.

The method that is particularly suitable for renewable product that the high temperature digital circuit uses and stable E/D type HEMT device of allow producing is provided.

Large power supply voltage in the regulation permission DCFL circuit is to improve noise margin and to shorten gate delay.

Provide big input voltage swing to eliminate the needs of regulating for logic level between the adjacent level among the IC.

The plane that E/D type HEMT is provided is integrated and need not any mesa etch or grid groove etching.

Brief description

Describe disclosure innovation with reference to accompanying drawing, accompanying drawing illustrates the important example embodiment of the innovation, and is attached to by reference in its explanation, in the accompanying drawing:

Fig. 1 illustrates the E type HFET of prior art.

Figure 1A explanation is used for the DCFL circuit diagram of E/D inverter.

Figure 1B explanation is used for the DCFL circuit of ring oscillator.

The microphoto of Fig. 1 C explanation inverter is as an embodiment of the innovation.

The microphoto of Fig. 1 D explanation ring oscillator is as an embodiment of the innovation.

Fig. 2 explanation does not utilize the transfer characteristic of an embodiment of traditional D type HEMT, the E type HEMT of the innovation and the innovation.

An embodiment of the process of E type AlGaN/GaN HFET is made in Fig. 3 A to 3F explanation.

The I-V output characteristic of the embodiment of Fig. 4 A explanation E type AlGaN/GaN HFET.

The I of the embodiment of Fig. 4 B explanation E type AlGaN/GaN HFET _g-V _GsCharacteristic.

Fig. 5 illustrate E type AlGaN/GaN HFET an embodiment pass through " SIMS " measured fluorinion concentration distribution curve.

Fig. 6 illustrates and injects the fluorine ion cross section of an embodiment of the innovation before.

Fig. 7 illustrates that various embodiment's passes through " SIMS " measured fluorinion concentration distribution curve.

Fig. 7 A and Fig. 7 B illustrate that various embodiment's passes through " SIMS " measured fluorinion concentration distribution curve.

Fig. 8 A explanation is at different CF ₄The I of E type AlGaN/GaN HFET after the plasma process conditions _dTo V _GsTransfer characteristic.

Fig. 8 B explanation is at different CF ₄The g of E type AlGaN/GaN HFET after the plasma process conditions _mTo V _GsTransfer characteristic.

Fig. 9 illustrates and adopts different CF ₄The grid Schottky diode of plasma treatment the barrier height of extracting and desirable factor.

Figure 10 illustrates the V of various E type AlGaN/GaN HFET _ThCorrelation with plasma power and processing time.

Figure 11 illustrates afm image, and the CF on the AlGaN layer is described ₄The small etch effect of plasma treatment.

Figure 12 A illustrates the DCI of various E type AlGaN/GaN HFET embodiment _dTo V _GsTransfer characteristic.

Figure 12 B illustrates the DC g of various E type AlGaN/GaN HFET embodiment _mTo V _GsTransfer characteristic.

Figure 13 illustrates the DC output characteristic of an E type AlGaN/GaN HFET embodiment.

The various embodiment of Figure 14 A explanation E type AlGaN/GaN HFET have different CF ₄Reverse and the forward gate current of plasma treatment.

The various embodiment of Figure 14 B explanation E type AlGaN/GaNHFET have different CF ₄The amplification of plasma treatment and forward gate current.

Figure 15 illustrates f _tAnd f _MaxWith the correlation of gate bias, wherein V _DsStuck-at-2V.

Figure 16 illustrates and adopts different CF ₄Measured f on the wafer of plasma treatment _tAnd f _Max

E type Si is made in Figure 17 A to 17F explanation ₃N ₄The demonstration program of AlGaN/GaN MISHFET.

Figure 18 illustrates demonstration DC output characteristic.

Figure 19 A illustrates transfer characteristic.

Figure 19 B illustrates grid leakage current.

Figure 20 illustrates the impulsive measurement result.

Figure 21 illustrates small-signal RF characteristic.

Figure 22 explanation does not have CF ₄The simulation conduction band diagram of traditional D type AlGaN/GaN HEMT of plasma treatment.

Figure 23 explanation has CF ₄The simulation conduction band diagram of the E type AlGaN/GaN HEMT of plasma treatment.

Figure 24 explanation does not have CF ₄Traditional D type AlGaN/GaNHEMT of plasma treatment and have CF ₄The electron concentration of the E type AlGaN/GaN HEMT of plasma treatment.

Figure 25 illustrates an embodiment according to the single chip integrated technological process of the E type of the inverter of the innovation and D type HEMT.

The single chip integrated exemplary process flow process of Figure 26 A to 26F explanation E type and D type HFET.

Figure 27 illustrates single chip integrated planar technique flow process.

Figure 28 illustrates another exemplary process flow process of E/D type HEMT.

Figure 29 explanation is by the D-HEMT of planar technique making and the DC output characteristic of E-HEMT.

Figure 30 compares the transfer characteristic of the transfer characteristic of planar technique and traditional handicraft.

Figure 31 explanation is by the quiescent voltage transfer characteristic of the E/D HEMT inverter of plane manufacture craft made.

Figure 32 illustrates the epitaxial structure of the HEMT that uses in the example embodiment.

Figure 33 explanation is used for the E type of monolithic inverter and the single chip integrated integrated technique flow process of D type HEMT.

Figure 34 illustrates the demonstration geometric parameter of inverter and ring oscillator.

Figure 35 illustrates DC I-V transfer characteristic and the output characteristic of disclosed demonstration D type and E type AlGaN/GaN HEMT.

Figure 36 illustrates the performance of made E type and D type AlGaN/GaN HEMT.

Figure 37 illustrates the I of D type and E type HEMT _g-V _gCharacteristic and the simulation guide margin band figure under the gate electrode of D type HEMT and E type HEMT.

Figure 38 illustrates the quiescent voltage transfer characteristic of traditional E/D HEMT inverter.

Figure 39 explanation according to various disclosed embodiments, have the quiescent voltage transfer characteristic of β=6.7,10,25 and 50 E/D HEMT inverter.

Figure 40 explanation has the noise margin of the inverter of different beta value.

Figure 41 explanation has the quiescent voltage transfer characteristic of the E/D HEMT inverter of β measured on different electrical power voltage=10.

Figure 42 explanation is for the inverter with β=10, at different V _DDMeasured noise margin.

Figure 43 explanation is according to an example embodiment, at V _DD=2.5V has the load and the input current of the inverter of β=10.

Figure 44 explanation has at V _DDThe frequency spectrum of 17 grades of ring oscillators of β=10 of=3.5V biasing, and Figure 45 illustrates its time domain specification.

Figure 46 illustrates the propagation delay of a circuit embodiments and the correlation of power delay product and supply voltage.

DETAILED DESCRIPTION OF THE PREFERRED

A large amount of innovation theories of the application are specifically described with reference to currently preferred embodiment (as an example rather than restriction).

The process of enhancement mode III nitride HFET is made in Fig. 3 A to 3F explanation according to the first embodiment of the present invention.A preferred epitaxial structure of Fig. 3 A explanation the innovation, therein, reference number 110,120,130 and 140 is represented substrates (for example sapphire, silicon or SiC), coring layer (low-temperature epitaxy GaN coring layer, AlGaN or AlN), high growth temperature GaN resilient coating and the Al that comprises modulation doping charge carrier accommodating layer _xGa _1-xThe N barrier layer.The manufacture method of the enhancement mode III nitride HFET of an embodiment is described below.Mesa-isolated is utilized Cl ₂/ He plasma dry-etching, be to have source/drain ohmic contact with 850 ℃ of annealing 45 seconds Ti, Al, Ni and Au to form 160 and form then, shown in Fig. 3 B.Subsequently, photoresist 170 forms pattern and the gate window of exposing.Then, handle or the fluorine ion injection, fluorine ion is added Al by for example fluoro plasma _xGa _1-xThe N barrier layer is shown in Fig. 3 C.Gate electrode 180 is by deposit and peel off Ni and Au forms on barrier layer 140, shown in Fig. 3 D.After this, back grid RTA carried out 10 minutes at 400-450 ℃.Passivation layer 190 is in the wafer grown on top, shown in Fig. 3 E.At last, by the contact pad that partially opens of the passivation layer on the elimination contact pad, shown in Fig. 3 F.

Example 1

In Aixtron AIX 2000HT metallo-organic compound chemical vapor deposition (MOCVD) system on (0001) Sapphire Substrate growth AlGaN/GaN HEMT structure.The HEMT structure is made up of thick unconscious Doped GaN resilient coating of low temperature GaN coring layer, 2.5-m and AlGaN barrier layer with nominal 30%Al composition.Barrier layer by 3-nm do not mix spacer, with 2.5 * 10 ¹⁸Cm ^-315-nm charge carrier accommodating layer that mixes and 2-nm undoped cladding layer are formed.The room temperature hall measurement of structure obtains 1.3 * 10 ¹³Cm ^-2Electronics sheet density and 1000cm ²The electron mobility of/Vs.Part table utilizes the Cl in the STS ICP-RIE system ₂/ He plasma dry-etching, be to have with 45 seconds the source/drain ohmic contact of Ti/Al/Ni/Au of 850 ℃ of annealing to form then.Ohmic contact resistance is measured as 0.8ohm-mm usually.

After opening the gate window with 1nm length by contact lithograph, sample passes through CF in the RIE system ₄Plasma was handled 150 seconds with the RF plasma power of 150W.The pressure of handling is generally 50mTorr.Via this exemplary depth distribution curve of handling the fluorine ion that adds like this be Gauss, and the exemplary depth of fluorine concentration during from order of magnitude of peak value decline is 20nm.Notice that it is the another kind of method that adds fluorine ion that ion injects, and to need to estimate the energy of about 10KeV.

Carry out the Ni/Au electron beam evaporation subsequently and peel off to form gate electrode.The gate regions of plasma treatment and self-aligned with grid electrode.Back grid RTA carried out 10 minutes at 400 ℃.This RTA temperature is through selecting, because at the RTA that is higher than 500 ℃ temperature grid Schottky contacts and source/drain ohmic contact are all demoted.Device has L _SgSource-the gate spacer of=1 μ m and L _GdThe grid of=2 μ m-drain electrode at interval.D type HEMT also makes on identical sample, and gate regions is not carried out plasma treatment.

Fig. 2 illustrates the transfer characteristic of D type and E type (after reaching before the back grid annealing) AlGaN/GaNHEMT.V _ThThe linear extrapolation that is defined as drain current is at peak value mutual conductance (g _m) point the gate bias intercept, the V of E type device _ThBe defined as 0.9V, and the V of D type device _ThFor-4.0V.The V that is higher than 4V _ThDisplacement realizes by plasma treatment.At V _Gs=0 place, mutual conductance reaches zero, shows real E type operation.The drain current quilt is pinch off fully, and at V _DsShow the leakage of 28 μ A/mm during=6V, i.e. the minimum value of reporting recently for E type AlGaN/GaN HEMT.Peak value g _mBe 151mS/mm for D type HEMT respectively and be 148mS/mm for E type HEMT.Maximum drain current (I _Max) for the gate bias (V of E type HEMT at 3V _Gs) time reach 313mA/mm.Comparison shows that of current-voltage (I-V) characteristic of the E type device after reaching before RTA playing an important role aspect the damage that recovers to cause during the plasma treatment and realization high current density and the mutual conductance with 400 ℃ of RTA that carried out 10 minutes.Fig. 4 A illustrates before the RTA process and the curve of output of E type device afterwards.After RTA, do not observe the variation of threshold voltage.V at 2.5V _Gs, higher by 85% with the saturated drain current (247mA/mm) of the E type device after 400 ℃ of RTA that carry out than (133mA/mm) before the RTA, and the knee voltage with E type device of RTA is 2.2V, wherein drain current is 95% saturated drain current.At V _GsThe cut-off state drain breakdown voltage of=0V is greater than 80V, show with D type HEMT in the observed not degradation of not comparing.Fig. 4 B illustrates the I of these three devices _g/ V _GsCurve.Realize lower grid leakage current for E type HEMT, particularly after RTA.

Pass through CF in order to study ₄The V of plasma treatment _ThThe mechanism of displacement is carried out secondary ion mass spectroscopy (SIMS) to the sample of following and is measured, so that monitoring CF ₄The atom of the AlGaN/GaN material of plasma treatment is formed variation.Except Al, Ga and N, detect a large amount of fluorine atoms in the sample after plasma treatment.Fig. 5 explanation is with the CF of 150W ₄Plasma power is handled the fluorine atom concentration profile of 2.5 minutes sample.The concentration of fluorine atom is the highest at the AlGaN near surface, and the order of magnitude that descends in raceway groove.Can infer, pass through CF ₄The fluorine ion that plasma produced is added into sample surface, and immersing ion to the plasma of the technology of the super shallow junction that is used for realizing advanced silicon technology as exploitation, to inject the effect of (" PIII ") similar.Because the strong elecrtonegativity of fluorine ion, the fluorine ion of adding can provide fixing negative electrical charge and exhaust electronics in the raceway groove effectively in the AlGaN potential barrier.Along with enough fluorine ions are added into the AlGaN potential barrier, D type HEMT can be exchanged into E type HEMT.CF ₄Plasma treatment can produce big threshold voltage displacement to 4.9V.Carry out 10 minutes RTA with 400 ℃ after, the peak value fluorine atom concentration of AlGaN near surface does not change, and then runs into more obvious reduction around the AlGaN/GaN interface.But should be noted that the SIMS measurement result from different strokes does not provide accurate quantitative comparison owing to lack normative reference.Yet, before RTA and V afterwards _ThLittle variation show that the sum of fluorine ion that is added into the AlGaN potential barrier is before RTA and afterwards near constant, plasma damage then obtains bigger recovery by RTA.The low grid reverse leakage current of E type HEMT is attributable to add owing to fluorine ion the upwards band curvature of the AlGaN layer that causes.After the RTA process, CF ₄Defective on the interface of caused metal and AlGaN is resumed, thereby produces the further inhibition to grid leakage current.Observe from the atomic force microscopy (" AFM ") that carries out for the sample that forms pattern is measured, plasma treatment only produces the reducing of 0.8nm of whole AlGaN barrier layer (20nm is thick).

Measure small-signal RF characteristic on the wafer of D type and E type AlGaN/GaN HEMT from 0.1 to 39.1GHz.Have the current gain of two types device of 1 μ m long gate and maximum stable gain/maximum available gain (MSG/MAG) and from measured S parameter, draw, as shown in Figure 5 as the function of frequency.At V _Ds=12 and V _Gs=1.9V place is for the current gain cutoff frequencies (f of E type AlGaN/GaNHEMT acquisition 10.1GHz _T) and the power gain cutoff frequency (f of 34.3GHz _MAX), be slightly less than its D type homologue, the latter the drain bias of 12V and-be measured as 13.1 and 37.1GHz on the gate bias of 3V respectively.

An advantage of the innovation is, the E type HFET with the fluorine ion that is added into barrier layer can stand the bigger gate bias corresponding with bigger input voltage swing (＞3V).

The thermal reliability test shows that also it all is stable that the fluorine ion in the AlGaN potential barrier adds up to 700 ℃.But, the Schottky contacts of making by nickel only be only below 500 ℃ stable.Therefore, temperature limit is up to 500 ℃, unless adopt another kind of Schottky contacts technology.The tungsten grid is a kind of possible candidate.

In Fig. 7, the influence that the fluorine atom in the AlGaN/GaN heterostructure is distributed by grid RTA after the difference of SIMS measurement is described.Be untreated device with for referencial use.

Can find, pass through CF ₄The fluorine ion that plasma treatment is added into the AlGaN barrier layer can make the threshold voltage SF effectively.The adding of the fluorine ion in the AlGaN layer is measured by secondary ion mass spectroscopy (SIMS) and is confirmed, as shown in Figure 7.At CF ₄In the plasma treatment, fluorine ion is injected into the AlGaN/GaN heterostructure in the built-in field that RF power is simulated.

Also draw from result shown in Figure 7, the fluorine ion of injection all has good thermal stability at the AlGaN layer up to 700 ℃.Being confirmed as the reason of threshold voltage displacement though should be noted that the existence of fluorine ion, not knowing where fluorine ion occupies, is calking or displacement.For CF ₄The handled HEMT sample of plasma carries out deep-level transient spectroscopy (" DLTS ").The fluorine ion that is added into the AlGaN potential barrier it seems that introducing is lower than the conduction band minimum deep energy level state of 1.8eV at least.Therefore, fluorine ion is considered to introduce the similar electronegative deep energy level of being led in AlGaN.

Note, in the SIMS of for example Fig. 7 chart, be difficult to from SIMS measures, carry out the accurate Calculation of concentration, because do not know beam size.But, calculating according to band structure and threshold voltage, the peak value of F concentration may be high to about 1 * 20cm ^-3

In Fig. 7 A, the influence that the different plasma power stage without RTA measured by SIMS distributes for the fluorine atom in the AlGaN/GaN heterostructure is described.

Notice that 200W and 400W lines show " projection (bump) " on the interface between the AlGaN/GaN interface.In adition process, fluorine ion may be filled surface or interface state (or " trap "), produces " abnormality stops ".Therefore, this shows the more traps of existence on the interface.In addition, 600W and 800W lines do not show projection, are likely because bigger penetration depth and overall density.

Untreated device is with for referencial use.In Fig. 7 B, the influence of adopting the different backs grid treatment temperature of the constant power of 600W that the fluorine atom in the AlGaN/GaN heterostructure is distributed for RTA of measuring by SIMS is described.Untreated device is with for referencial use.Notice that the distribution among 700 ℃ and the following AlGaN shows the conventional effect of root Dt, but the very different diffusivity (certain activation energy effect of perhaps possible other) of reflection as if of the distribution in the AlGaN layer.Therefore, data show that fluorine ion is more stable in AlGaN than in GaN.In addition, binding energy may be higher, and the relevant energy state of fluorine to be lower than the degree of conduction band in AlGaN than in GaN bigger.

Also studied susceptibility for plasma process parameters.By using different CF ₄Plasma power and processing time are with different V _ThValue is made device.Adopt five kinds of different combinations: 100W, 60 seconds, 150W, 20 seconds, 150W, 60 seconds, 150W, 150 seconds and 200W, 60 seconds.In order to compare, without CF ₄The HEMT that handles is also making on the identical sample and in the identical course of processing.All device unpassivated, so that any confusion of avoiding passivation layer to cause, it may change the stress of AlGaN layer and change piezoelectric polarization.All HEMT devices have grid length, the L of 1 μ m _SgSource-the gate spacer of=1 μ m and L _GdThe grid of=2 μ m-drain electrode at interval.DC current-voltage (I-V) characteristic of the device of making adopts the HP4156A parameter analyzer to measure.Transfer characteristic and mutual conductance (g _m) characteristic is respectively shown in Fig. 8 A and Fig. 8 B.Take traditional HEMT (promptly without CF ₄Plasma treatment) as the baseline device, all other CF ₄The threshold voltage of the HEMT of plasma treatment is shifted to positive direction.V _ThBe defined as at peak value mutual conductance (g _m) the gate bias intercept of linear extrapolation of drain current of point, the V of all devices _ThIn Fig. 9, extract and list.For traditional HEMT, V _ThFor-4V.For passing through CF ₄Plasma is handled 150 seconds HEMT, V with 150W _ThBe 0.9V, it is corresponding to E type HEMT.Realize the maximum V of 4.9V _ThDisplacement.In order further to disclose CF ₄The effect of plasma treatment, V _ThWith CF ₄The correlation of plasma treatment time and RF power is run a curve in Figure 10.Along with the processing time that plasma power increases and employing is longer, realize V _ThBigger displacement.Along with the increase of plasma treatment time, more the polyfluoro ion is injected into the AlGaN layer.The fluorinion concentration that increases causes the electron density that reduces in the raceway groove, and causes V _ThJust displacement.When plasma power increased, fluorine ion obtained more high-energy, and the fluorine ion flow is because of CF ₄The enhancing ionization rate and increase.Adopt higher energy, fluorine ion can reach the darker degree of depth near raceway groove.Fluorine ion is more near raceway groove, and then they are more effective when exhausting 2DEG, and realizes V _ThBigger displacement.The fluorine ion flow that increases is to V _ThHas the identical effect of increase with plasma treatment time by improving the fluorine atom concentration in the AlGaN layer.Should be noted that almost V _ThTo time and V _ThThe V that power relation is shown AlGaN/GaN HEMT _ThThe possibility of accurate control.Though V _ThPass through CF ₄Plasma treatment is shifted, but g _mDo not demote.Shown in Fig. 8 B, the maximum g of all devices _mBe in the scope of 149-166mS/mm, except handle 60 seconds device with 150W, it has the more peak value g of 186mS/mm _mGuess that this singular point is caused by the nonuniformity in the epitaxial growth.By to CF ₄The AFM that the sample of the formation pattern of handling (wherein, the part of sample is processed, and prevents that other parts are through plasma treatment) carries out measures to determine CF ₄The AlGaN thickness that plasma treatment only produces less than 1nm reduces, as shown in figure 11.Therefore, show,, in element manufacturing, keep the 2DEG mobility in the raceway groove according to the innovation near constant mutual conductance.A committed step that keeps mutual conductance is a back grid annealing process.

Recover the damage that plasma causes by back grid annealing

As previously described, plasma causes damage usually, and produces the defective in the semi-conducting material, thereby makes mobility of charge carrier rate degradation.RTA is a kind of effective ways of repairing these damages and recovering mobility.At CF ₄Among the AlGaN/GaN HEMT of plasma treatment, drain current and mutual conductance degradation just take place after plasma treatment.In Figure 12 A and Figure 12 B, drawn RTA (400 ℃, 10 minutes) before and afterwards be untreated device and processing apparatus (200W, 60 seconds) go up the drain current measured and the curve of mutual conductance.Figure 13 compares before the RTA and the output characteristic of processing apparatus afterwards.After the RTA, drain current is high by 76%, and mutual conductance is high by 51% in processing apparatus.The RTA process can be recovered the major part of the mobility degradation of the device after the plasma treatment, and traditional device that is untreated is shown not obvious influence.Therefore, CF ₄I in the device of plasma treatment _dAnd g _mRecovery be the result that efficient recovery is arranged of the 2DEG mobility on this RTA condition.With recovery is by comparing based on 700 ℃ required higher anneal temperature of the damage that ICP-RIE produced of fluorine in the situation of groove grids, this lower RTA temperature shows CF ₄Plasma treatment produces ratio based on the lower damage of the ICP-RIE of chlorine.It also makes the RTA process carry out after the grid deposit, thereby realizes the target of self-registered technology.If adopt V _ThPrevious definition, CF then ₄The V of the device of plasma treatment _ThAfter RTA, as if be displaced to-0.29V from 0.03V.As the g shown in Figure 12 B _mStarting point or the I on the logarithmic scale shown in the insertion figure of Figure 12 A _dStarting point as the assessment V _ThStandard the time, CF ₄The V of the device after the plasma treatment _ThAfter RTA, do not change.V _ThGood thermal stability and previous described AlGaN layer in the good thermal stability of fluorine atom consistent.

The inhibition of conductivity gate leakage current

AlGaN/GaN HEMT presents the reverse grid leakage current of the theoretical prediction value that is higher than thermionic emission (" TE ") model far away all the time.Higher grid current makes the noiseproof feature degradation of device, and improves stand-by power consumption.Specifically, the swing of forward gate current restriction gate input voltage, thereby restriction maximum drain current.Attempted the grid current that alternate manner suppresses AlGaN/GaNHEMT.These effort comprise to be adopted gate metal, employing copper, the modification HEMT structure (for example adding the GaN cover layer) with higher work-functions or turns to metal-insulator semiconductor's hetero-structure field effect transistor (MISHFET).CF in the innovation ₄Among the AlGaN/GaN HEMT of plasma treatment, can realize oppositely and the inhibition of the grid current in the forward bias district.Grid current suppresses to show and CF ₄The correlation of plasma process conditions.

Figure 14 A and the different CF of Figure 14 B explanation employing ₄The grid current of the AlGaN/GaNHEMT of plasma treatment.Figure 14 B is the amplified curve in forward gate bias district.In the reverse bias district, and without CF ₄Traditional HEMT of plasma treatment compares, all CF ₄The grid leakage current of the AlGaN/GaN HEMT of plasma treatment reduces.At V _g=-20V, grid leakage current is from 1.2 * 10 of traditional HEMT ^-2A/mm arrives with 7 * 10 of 60 seconds AlGaN/GaN HEMT of 200W plasma treatment ^-7A/mm descends and surpasses four orders of magnitude.In the forward region, all CF ₄The grid current of the AlGaN/GaN HEMT of plasma treatment also reduces.Therefore, the expansion of the conducting voltage of grid Schottky diode, and the gate input voltage swing increases.Adopt 1mA/mm as standard, the conducting voltage of grid Schottky diode is increased to the CF through 60 seconds with 200W from the 1V of traditional HEMT ₄The 1.75V of the AlGaN/GaN HEMT of plasma treatment.

CF ₄The inhibition of the grid leakage current among the AlGaN/GaN HEMT of plasma treatment can be described as follows.At CF ₄In the plasma treatment, fluorine ion is added into the AlGaN layer.Have strong electronegative these ions as fixed negative charge, they cause upwards conduction band bending in the AlGaN barrier layer because of the electrostatic induction effect.Therefore, formation additional barrier height Ф as shown in figure 23 _F, and effective metal barrier potential of a semiconductor height is from Ф _BBe increased to Φ _B+ Ф _FThe barrier height of this increase can suppress oppositely and the grid Schottky diode electric current in the forward bias district effectively.Adopt higher plasma power and longer processing time, fluorinion concentration in the AlGaN layer increases, and effective barrier height further improves, and suppresses thereby produce more significant grid current.In Fig. 9, describe in detail by utilizing the effective barrier height and the desirable factor of TE model from the forward region extraction of the grid current of measurement.The effective barrier height of tradition HEMT is 0.4eV, and for the CF that carries out 60 seconds with 200W ₄The HEMT of plasma treatment, effective barrier height is increased to 0.9eV.CF ₄The effective barrier height of the HEMT of plasma treatment also shows the trend that increases with plasma power and processing time, and except handle 20 seconds HEMT with 150W, it has the higher effective barrier height.This exception is considered to because process variations causes.The effective barrier height that extracts show that well below the fact of theoretical prediction value and very big desirable factor (＞2.4) grid current of the AlGaN/GaNHEMT of making is not by TE mechanism but by other mechanism, control as the auxiliary tunnelling of vertical tunnelling, surface potential barrier refinement and trap.Therefore, inaccurate by barrier height and the desirable factor that utilizes the TE model to extract.Yet they are provided for illustrating CF ₄The abundant qualitative information of the mechanism that the grid current among the AlGaN/GaN HEMT of plasma treatment suppresses.

Dynamic I-V characteristic is by utilizing Accent DIVA D265 system research CF ₄Plasma treatment is carried out the drain current diffusion influence.Pulse duration is 0.2 μ s, and the pulse spacing is 1ms.Dead point be in slightly (～0.5V) be lower than the V of pinch off _GS, and V _DS=15V.Compare with static I-V characteristic, the maximum drain current of traditional D type HEMT reduces by 63%, and 150 seconds CF is carried out in employing with 150W ₄The maximum drain current of the E type HEMT of plasma treatment reduces by 6%.

The drain current of E type HEMT descends alleviate may be gate bias by the raising of dead point cause (for E type HEMT, V _GS=0V is for D type HEMT, V _GS=-4.5V).

The RF small-signal behaviour

Small-signal RF characteristic description utilizes Cascade microwave probe and Agilent 8722ES network analyzer to carry out on the frequency range of 0.1-39.1GHz on the wafer of the AlGaN/GaN HEMT that makes.Adopt the S parameter of dry joint dish to carry out open pad de-embedding, so that eliminate the parasitic capacitance of surveying pad.Having the current gain of all devices of the long grid of 1 μ m and maximum stable gain/maximum available gain (MSG/MAG) draws from de-embedding S parameter as the function of frequency.Current cut-off frequency (f _t) and maximum oscillation frequency (f _Max) extract from current gain and MSG/MAG with unit gain.Observe intrinsic f _tAnd f _MaxWhen not having the de-embedding process generally than extrinsic high 10-15%.For E type HEMT, f _tAnd f _MaxWith the correlation of gate bias as shown in figure 15.f _tAnd f _MaxAll more constant on low and high gate bias, show good linearity.Figure 16 lists the f of all samples _tAnd f _MaxFor traditional HEMT, f _tAnd f _MaxBe 13.1 and 37.1GHz, and for CF ₄The HEMT of plasma treatment, f _tAnd f _MaxBe approximately 10 and 34GHz,, but handle divided by 150W outside 60 seconds the HEMT a little less than traditional HEMT.This higher f in the device of 150W/60 second _tAnd f _MaxThe higher g of prerequisite confession with it _mUnanimity, and owing to material inconsistency and process variations.CF ₄Lower slightly f among the HEMT of plasma treatment _tAnd f _MaxShow, can recover the 2DEG mobility of demoting effectively, but recover less than 100% by plasma treatment with 400 ℃ of back grid RTA that carry out.We advise, need the optimization of RTA temperature and time further to improve the 2DEG mobility, do not make grid Schottky contacts degradation simultaneously.

MISHFET

In another embodiment, E type Si ₃N ₄/ AlGaN/GaN MISHFET adopts two-stage Si ₃N ₄Process makes up, and it is with the Si under the grid ₃N ₄Si in thin layer (15nm) and the access district ₃N ₄Thick-layer (approximately 125nm) is a characteristic.Plasma treatment based on fluorine is used for device is transformed into the E type from the D type.E type MISHFET with 1-μ m long gate area coverage presents the threshold voltage of 2V, the forward conduction gate bias of 6.8V (comparing with the about 3V that realizes among the E type AlGaN/GaN HEMT) and the maximum current density of 420mA/mm.Grow on the AlGaN/GaN HFET structure of using in this example (0001) Sapphire Substrate in Aixtron AlX 2000HT MOCVD system.The HFET structure is made up of thick unconscious Doped GaN resilient coating of 50-nm thick low temperature GaN coring layer, 2.5-μ m and AlGaN barrier layer with nominal 30%Al composition.Barrier layer by 3-nm do not mix spacer, with 2 * 10 ¹⁸Cm ^-316-nm charge carrier accommodating layer that mixes and 2-nm undoped cladding layer are formed.The capacitance-voltage that the mercury probe carries out (" C-V ") is measured the initial threshold voltage of sample generation-4V hereto.Work flow is shown in Figure 17 A to 17F.Part table utilizes the Cl in the STS ICP-RIE system ₂/ He plasma dry-etching, be to have with 30 seconds the source/drain ohmic contact of Ti/Al/Ni/Au (20nm/150nm/50nm/80nm) of 850 ℃ of annealing to form then, shown in Figure 17 A.Then, a Si ₃N ₄Layer (approximately 125nm) is deposited on the sample by plasma reinforced chemical vapor deposition (PECVD), shown in Figure 17 B.Open the gate window with 1-μ m length by photoetching after, sample is placed in the RIE system through CF ₄Plasma treatment, it eliminates Si in AlGaN ₃N ₄With the adding fluorine ion.The RF power of plasma is 150W, shown in Figure 17 C.Air-flow is controlled as 150sccm, and total etching and processing time are 190 seconds.After eliminating photoresist, the 2nd Si ₃N ₄Film (approximately 15nm) is deposited by PECVD so that form insulating barrier between gate metal and the AlGaN, shown in Figure 17 D.Subsequently, Si ₃N ₄Layer is formed pattern and etching, so that open window in source electrode and drain electrode ohmic contact zone, shown in Figure 17 E.Then, the long gate electrode of 2-μ m by photoetching, be that (～50nm/300nm) electron beam evaporation and peeling off defines Ni/Au, shown in Figure 17 F then.Cover whole plasma treatment zone in order to ensure gate electrode, metal gates length (2 μ m) is selected as greater than handling gate regions (1 μ m), thereby produces the T gate configuration.The grid that is suspended from source/drain electrode access zone passes through thick Si ₃N ₄Layer and the insulation of AlGaN layer, it is low-level that grid capacitance is remained on.At last, whole sample is with 400 ℃ of annealing 10 minutes, so that repair the damage that the plasma in AlGaN potential barrier and the raceway groove causes.Measure from the bottom of grid, gate-to-source and gate-to-drain are 1.5 μ m at interval.Test is adopted the grid width of 10 μ m and is adopted the grid width of 100 μ m to design E type MISHFET for the RF feature description for dc.

Constructed device is then characterized.In Figure 18, drawn the DC output characteristic of E type MISHFET.At V _GS=7V, device present the conducting resistance of the peak current density of about 420mA/mm, about 5.67 Ω mm and the knee voltage of about 3.3V.Figure 19 A explanation has the transfer characteristic of the identity unit of 1 * 10-μ m grid size.Can see V _ThBe approximately 2V, show by inserting Si ₃N ₄The V that insulator and plasma treatment realize _Th6-V displacement (comparing) with traditional D type HFET.Peak value mutual conductance gm is approximately 125mS/mm.Grid leakage current when Figure 19 B explanation negative bias and forward bias.The forward bias conducting voltage of grid is approximately 6.8V, and the gate bias swing more much bigger than E type HFET is provided.Adopt the pulse length of 0.2 μ s and the pulse spacing of 1ms that the E type MISHFET with 1 * 100-μ m grid size is carried out impulsive measurement.Quiescent bias point is chosen in V _GS=0V (is lower than V _Th) and V _DS=20V.Figure 20 shows that pulse peak current is higher than static, and showing does not have current collapse in the device.Static maximum current density with big device of 100-μ m grid width is approximately 330mA/mm, less than the device with 10-μ m grid width (approximately 420mA/mm).Lower peak current density in the big device is because the self-heating effect of reduction current density causes.Because occur minimum automatic heating during impulsive measurement, therefore, the maximum current of the device that 100-μ m is wide can reach the device identical level wide with 10-μ m.On the wafer small-signal RF characteristic from 0.1 to 39.1GHz at V _DS=10V carries out the wide E type MISHFET of 100-μ m.As shown in figure 21, maximum current gain cut-off frequency (f _T) and power gain cutoff frequency (f _Max) be respectively 13.3 and 23.3GHz.When gate bias was 7V, small-signal RF performance was not obviously demoted, and wherein had the f of 13.1GHz _TF with 20.7GHz _Max, show Si ₃N ₄Insulator provides the good insulation between gate metal and the semiconductor.

Model

For the part of the innovation has been developed the theoretical characterization model.For traditional AlGaN/GaN HEMT, as shown in Figure 7, when calculating the HEMT threshold voltage, need consider polarization charge with silicon modulate-doped layer.Make amendment from the formula of general use by the effect of considering charge polarization, surface and buffering trap, the threshold voltage of AlGaN/GaN HEMT can be expressed as:

$V_{\mathrm{th}}={\mathrm{\&phi;}}_B/e-\mathrm{d\&sigma;}/\mathrm{\&epsiv;}-\mathrm{\&Delta;}{E}_C/e+{\mathrm{<figure-callout\; id="0"\; label="E\; f"\; filenames="A20068005199000481.png,A20068005199000531.png"\; state="\{\{state\}\}">E</figure-callout>}}_f/e$

$-\frac{e}{\mathrm{\&epsiv;}}\underset{0}{\overset{d}{\&Integral;}}\mathrm{dx}\underset{0}{\overset{x}{\&Integral;}}{N}_{\mathrm{si}}\left(x\right)\mathrm{dx}-\mathrm{ed}{N}_{\mathrm{\&epsiv;k}}/\mathrm{\&epsiv;}-e{N}_b/C_b.---\left(1\right)$

Wherein parameter-definition is as follows:

It is the metal semiconductor schottky barrier height.

σ is total clean (the spontaneous and piezoelectricity) polarization charge on potential barrier-AlGaN/GaN interface.

D is the AlGaN barrier layer thickness.

N _Si(x) be silicon doping concentration.

Δ E _CIt is the conduction band offset on the AlGaN/GaN heterostructure.

E _F0Be poor between the intrinsic Fermi level of GaN raceway groove and the conduction band edge.

ε is the dielectric constant of AlGaN.

N _StIt is the net charge surface wells of each unit are.

N _bIt is effective net charge buffering trap of each unit are.

C _bIt is effective buffering-channel capacitance of each unit are.

Last two effects of describing surface wells and buffering trap respectively in the equation (1).The AlGaN surface is in x=0, and the direction of sensing raceway groove is integrated positive direction.In order to represent above-described device, fixed negative charge is introduced into the AlGaN barrier layer under the grid.Because electrostatic induction, these fixed negative charges can exhaust the 2DEG in the raceway groove, improve and can be with, thereby modulation V _ThThe effect that comprises the negative electrical charge that limits in the AlGaN potential barrier, the threshold voltage of revising from equation (1) is expressed as:

$V_{\mathrm{th}}={\mathrm{\&phi;}}_B/e-\mathrm{d\&sigma;}/\mathrm{\&epsiv;}-\mathrm{\&Delta;}{E}_C/e+{\mathrm{<figure-callout\; id="0"\; label="E\; f"\; filenames="A20068005199000481.png,A20068005199000531.png"\; state="\{\{state\}\}">E</figure-callout>}}_f/e$

$-\frac{e}{\mathrm{\&epsiv;}}\underset{0}{\overset{d}{\&Integral;}}\mathrm{dx}\underset{0}{\overset{x}{\&Integral;}}(N_{\mathrm{si}}\left(x\right)-N_F\left(x\right))\mathrm{dx}-\mathrm{ed}{N}_{\mathrm{st}}^{\&prime;}/\mathrm{\&epsiv;}-e{N}_b/C_b.---\left(2\right)$

Positive charge distribution curve N _Si(x) by net charge distribution N _Si(x)-N _F(x) replace, wherein N _F(x) be the concentration of electronegative fluorine ion.Surface wells density (N _St) can revise by plasma treatment.

By using Poisson's equation and Fermi-Di Lake statistics, simulation is made up of the conduction band distribution curve and the electron distributions of AlGaN/GaN HEMT structure that has and be not added into the fluorine ion of AlGaN layer.Two kinds of structures all have identical epitaxial structure, as shown in Figure 7.For the HEMT structure that adds fluorine ion, the distribution curve of electronegative fluorine ion is from passing through CF ₄Plasma was handled 150 seconds and was converted to 150W in the SIMS measurement result that the fluorine atom of the AlGaN/GaNHEMT structure of E type HEMT distributes and extracts.Simulation conduction band diagram when in Figure 22 and Figure 23, having drawn zero gate bias.For the simulation conduction band of E type HEMT, as shown in figure 22, fluorine concentration is 3 * 10 by utilizing peak value fluorine concentration on the AlGaN surface ¹⁹Cm ^-3Linear distribution come approximate calculation, and fluorine concentration to be assumed on the AlGaN/GaN interface be insignificant.About 3 * 10 ¹³Cm ^-2Total fluorine ion sheet concentration be enough to not only compensate silicon doping (about 3.7 * 10 in the AlGaN potential barrier ¹³Cm ^-2), but also compensation piezoelectricity and spontaneous polarization charge inducing (about 1 * 10 ¹³Cm ^-2).Can be observed two notable features.At first, compare with the AlGaN/GaN HEMT structure that is untreated, the conduction band minimum of the 2DEG raceway groove of the structure of plasma treatment is higher than Fermi level, shows the raceway groove and the E type HEMT that exhaust fully.Shown in the electron distribution curve among Figure 24, in the structure of plasma treatment, there is not electronics in the raceway groove under zero gate bias, show E type HEMT operation.Secondly, fixed band negative electrical charge fluorine ion causes being bent upwards of conduction band especially in the AlGaN potential barrier, thereby produces additional barrier height Φ F, as shown in figure 23.The potential barrier of this enhancing can obviously suppress oppositely and the grid Schottky diode electric current of the AlGaN/GaN HEMT in the forward bias district.

The epitaxial structure of the integrated E/D type of monolithic HFET is made up of the following: (a) Semiconductor substrate (sapphire, SiC, silicon, AlN or GaN etc.); The resilient coating of (b) on substrate, growing; (c) channel layer; (d) barrier layer comprises the wall that do not mix, modulation doping charge carrier accommodating layer and undoped cladding layer.Manufacturing process comprises: (f) active area isolation; (g) ohmic contact on source electrode and the drain terminal forms; (h) photoetching of the area of grid of E type HFET; (i) to the plasma treatment based on fluoride of the exposure barrier layer of E type HFET; (j) the gate metal deposit of E type HFET; (k) photoetching of the gate regions of D type HFET; (l) the gate metal deposit of D type HFET; Ml) surface passivation of D type and E type HFET; (n) the grid annealing of carrying out with the temperature that raises.This single chip integrated signal work flow as shown in figure 25.

Active device in the above-mentioned monolithic integrating process is isolated the employing mesa etch, and it is a characteristic to eliminate by the active region of etching technique in not having the zone of HFET.This method applies restriction to integration density, photoetching resolution.For high-frequency circuit, the additional interruption also introduced to wave propagation in the edge of table top, and this makes circuit design and Analysis of Complexization again.Owing to can exhaust electronics in the raceway groove (provide raceway groove electric by) based on the plasma treatment of fluoride, therefore can be used for device isolation.Adopt the plasma power and the processing time that increase, do not need the zone of active device on electric, to end fully, thereby the electrical isolation between the device is provided.This method does not relate to any material eliminates, thereby realizes the smooth wafer surface of planar technique.

Example

Figure 26 A to 26F illustrates the process of the E/D type HFET of monolithic integration integrated circuits according to one embodiment of present invention.Figure 26 A illustrates a preferred epitaxial structure of the present invention, and wherein reference number 110,120,130 and 140 is represented substrates, low-temperature epitaxy GaN coring layer, high growth temperature GaN resilient coating and the Al that comprises modulation doping charge carrier accommodating layer _xGa _1-xThe N barrier layer.The single chip integrated manufacture method of the E/D type HFET of integrated circuit is as described below.For D type and E type HFET, mesa-isolated is utilized Cl simultaneously ₂/ He plasma dry-etching, be to have source/drain ohmic contact with 850 ℃ of annealing 45 seconds Ti, Al, Ni and Au to form 160 and form then, shown in Figure 26 B.The gate-to-source interconnection of grid and D type HFET forms pattern by photoresist 170 shown in Figure 26 C, follow deposit afterwards and peel off Ni and Au 178.After this, the grid of E type HFET, pad and second interconnection adopt photoresist 175 to form pattern, shown in Figure 26 D.Then, for example inject, the Al under the grid of fluoride ion adding E type HFET by fluoride plasma treatment or fluoride ion _xGa _1-xThe N barrier layer is shown in Figure 26 D.Gate electrode 180 is by deposit and peel off Ni and Au forms on barrier layer 140.After this, back grid rapid thermal annealing (RTA) carried out 10 minutes at 400-450 ℃.Passivation layer 190 is in the wafer grown on top, shown in Figure 26 E.Then, by the part of eliminating the passivation layer on contact pad and the through hole they are opened, shown in Figure 26 F.At last, form the 3rd interconnection.

At the typical CF that carries out 150 seconds for E type HFET with 150W ₄Plasma process conditions and with 450 ℃ of 20nm Al that carry out on 10 minutes the 2 μ m GaN resilient coatings of typical case back grid RTA condition _0.25Ga _0.75Set up E/D HFET inverter and 17 grades of ring oscillators that directly are coupled on the N barrier layer.Inverter has the NM of 0.21V on the supply voltage of 1.5V _LNM with 0.51V _HWhen applying the supply voltage of 3.5V, 17 grades of ring oscillators present the maximum oscillation frequency of the 225MHz corresponding with the minimum propagation delay of 130ps.

Example

This embodiment describes the single chip integrated method in plane of E type and D type AlGaN/GaN HFET.As described in first embodiment, the isolation between the active device can obtain by setting up active part table via the etching of setting up the non-flat forms wafer surface.In production of integrated circuits, planar technique suits the requirements all the time.Abide by the same principle that the raceway groove by the electronegative fluorine ion among the AlGaN exhausts, can realize by exhausting based on expection passive (by the isolating) zone of the plasma treatment of fluoride.Plasma power and processing time all can increase, so that strengthen carrier depletion.Work flow as shown in figure 27, wherein: (a) the source/drain ohmic contact forms; (b) the D type HFET grid definition of being undertaken by photoetching; (c) part of D type HFET gate metalized and interconnection formation; (d) by following the E type HFET grid definition that plasma treatment is carried out after the photoetching; (e) part of E type HFET gate metalized and interconnection formation; (f) define by following second area of isolation that carries out based on the plasma treatment of fluoride after the photoetching; (g) follow the final chip of passivation afterwards.

Example

Grow on AlGaN/GaN HEMT structure in this example (0001) Sapphire Substrate in Aixtron AIX 2000HTMOCVD system.The HEMT structure is made up of thick unconscious Doped GaN resilient coating of low temperature GaN coring layer, 2.5-μ m and AlGaN barrier layer with nominal 30%Al composition.Barrier layer by 3-nm do not mix spacer, with 2 * 1018cm ^-321-nm charge carrier accommodating layer that mixes and 2-nm undoped cladding layer are formed.The room temperature hall measurement of structure produces 1.3 * 1013cm ^-2Electronics sheet density and 950cm ²The electron mobility of/Vs.

The integrated technique flow process as shown in figure 28.At first, the source/drain ohmic contact of E/D type device simultaneously the Ti/Al/Ni/Au (20nm/150nm/50nm/80nm) by electron beam evaporation deposit and form with 850 ℃ of rapid thermal annealings that carry out 30 seconds, shown in Figure 28 (a).Secondly, the active region of two kinds of devices of E/D type forms pattern by photoetching, follows the CF in the reactive ion etching system thereafter ₄Plasma treatment.Plasma power is 300W, and the processing time is 100 seconds.Air-flow is controlled as 150sccm, and plasma bias installs and is changed to 0V.Area of isolation is that wherein a large amount of fluorine ions are added into the AlGaN of near surface and GaN layer, exhaust the position of the two-dimensional electron gas in the raceway groove then, shown in Figure 28 (b).Then, the gate electrode of D type HEMT by contact lithograph, follow the electron beam evaporation of Ni/Au (50nm/300nm) and peel off and form pattern afterwards, shown in Figure 28 (c).Subsequently, gate electrode and the interconnection of definition E type HEMT.Before the electron beam evaporation of Ni/Au, the area of grid of E type HEMT passes through CF ₄Plasma is handled 150 seconds (it has the insignificant etching to AlGaN) with 170W, shown in Figure 28 (d).This plasma treatment is carried out the function that the device of handling is converted to E type HEMT from the D type.The silicon nitride passivation that 200nm is thick passes through the PECVD deposit, and opens the detection pad.Then, sample is with 400 ℃ of annealing 10 minutes, so that repair the AlGaN potential barrier of E type HEMT and the damage that the plasma in the raceway groove causes, shown in Figure 28 (e).As a comparison, D type device is made by standard technology on another sample from same substrate, and in standard technology, the inductively coupled plasma reactive ion etching is used for table top is defined as active region.For the directly coupling FET logic inverter shown in Figure 1A, E type HEMT design of Driver becomes grid length, gate-to-source interval, gate-to-drain interval and grid width to be respectively 1.5,1.5,1.5 and 50 μ m; It is 4,3,3 and 8 μ m that D type HEMT load is designed to grid length, gate-to-source interval, gate-to-drain interval and grid width, produces ratio β=(W of 16.7 _E/ L _E)/(W _D/ L _D).For characterizing discrete E type and the D type HEMT that makes grid size with 1.5 * 100 μ m.

Device and circuit characteristic

E/D type HEMT for making by planar technique has drawn output characteristic in Figure 29.The peak current density of D type and E type HEMT is approximately 730 and 190mA/mm.DC transfer characteristic between Figure 30 illustrated planar and the standard technology relatively.Can see that the drain leakage of planar technique is approximately 0.3mA/mm, reach and the identical level of device of making by the standard unit facet etch.D type HEMT by planar technique has and the suitable drain current and the transconductance characteristic that pass through standard technology, shown in Figure 30 (b).In addition, (400 * 100 μ m between two pads ²) leakage current adopt the interval of 150 μ m to measure.In the DC of 10V biasing, the same level (about 30 μ A) at standard unit facet etch sample is approximately 38 μ A by the leakage current of planar technique.Compare with the standard mesa technique, can realize the same levels of active device isolation based on the plasma treatment of fluoride, thereby realize complete plane integrated technique.Compare with D type device, E type HEMT presents littler mutual conductance (" g _m"), this is that the incomplete recovery of the damage introduced by plasma causes.Sample also shows by the fact of the thermal annealing that carries out with 400 ℃, at least one pre-in respect of good thermal stability on 400 ℃ temperature.Should be noted that also developing ion implantation technique is used for injecting so that isolating between the generation device that serious crystal lattice damage realized on the whole thickness of GaN resilient coating by a plurality of energy N+.Compare CF with ion implantation technique ₄The plasma treatment technology has the low-cost and low advantage of damaging.

The E/D type HEMT DCFL inverter of making by the plane integrated technique is characterized.Figure 31 explanation is at supply voltage V _DDThe measurement quiescent voltage transfer curve of the inverter of=3.3V.High and low output logic level (V _OHAnd V _OL) be respectively 3.3 and 0.45V, wherein have the output swing (V of 2.85V _OH-V _OL).Dc voltage gain in the range of linearity is 2.9.By the V on the definition unit gain point _ILAnd V _IHValue, low and strong noise tolerance limit is 0.34 and 1.47V.Inverter DC electric current also is shown in Figure 31.Leakage current with E type device pinch off is approximately 3 μ A, and it is consistent with the discrete device result.

Example

Figure 32 illustrates according to the AlGaN/GaN epitaxial heterostructures during the making of the HEMT of the innovation.They comprise the following: 2.5 μ m GaN resilient coating and raceway grooves, 2nm is doped with Al not _0.25Ga _0.75The N distance piece has with 1 * 1018cm ^-3The 15nmAl of the Si that mixes _0.25Ga _0.75N charge carrier accommodating layer, and 3nm doped with Al not _0.25Ga _0.75The N cover layer.Structure is grown on Sapphire Substrate in Aixtron 2000HT MOCVD system.Technological process as Figure 33 (a) to shown in 33 (f).

Table top and source/drain ohmic contact are that E type and D type HEMT form simultaneously, as Figure 33 (a) with (b).Then, the gate electrode of D type HEMT is by photoetching, metal deposit and peel off and form, as Figure 33 (c) with (d).After the pattern of grid that defines E type HEMT and interconnection, sample passes through CF in STS RIE system ₄Plasma was handled 150 seconds with the source power of 150W, shown in Figure 33 (e), was for the gate metalized of E type HEMT then and peeled off.Check that by atomic force micrology (" AFM ") measurement the AlGaN potential barrier thickness reduces 0.8nm after plasma treatment.Subsequently, back grid thermal annealing carried out 10 minutes with 450 ℃, shown in Figure 33 (f).CF ₄Plasma treatment is converted to the E type to the GaN HEMT that handles from the D type.The threshold voltage shift amount depends on treatment conditions, for example plasma power and processing time, as previously described.The annealing of back grid is used for recovering the damage that the plasma of AlGaN potential barrier and raceway groove is introduced.In principle, annealing temperature is high more, and it is effective more to damage reparation.But in fact, back grid annealing temperature should not surpass the maximum temperature (in our situation ,～500 ℃) that the grid Schottky contacts can stand, as previously described.We find that the characteristic of D type HEMT remains unchanged after annealing, the drain current densities of E type HEMT then significantly increases.Find that back grid annealing does not have influence for the threshold voltage displacement that plasma treatment produced.

For E/D inverter and ring oscillator, most important physical design parameters is driving/duty ratio β=(W _g/ L _g) E type/(W _g/ L _g) the D type.Some E/D inverters and ring oscillator with from 6.7 to 50 β that change design and make at same sample.In Figure 34, list the geometric parameter of each design.Discrete E type and D type GaN HEMT with grid size of 1 * 100 μ m make on same sample simultaneously for dc and RF test.

The characteristic of E/D type HEMT

DC current-voltage (I-V) characteristic of discrete device adopts the HP4156A parameter analyzer to measure.In Figure 35 (a), drawn the transfer characteristic of E/D type HEMT.Small-signal RF characterizes and utilizes Cascade microwave probe and Agilent 8722ES network analyzer to carry out in the frequency range of 0.1-39.1GHz on the wafer of discrete device.In Figure 36, list the measurement parameter of E/D type HEMT.Threshold voltage and peak value mutual conductance (g _{M, max}) be 0.75V and 132mS/mm for E type HEMT, and for D type HEMT be-2.6V and 142mS/mm.The lower peak current density of the 480mA/mm of D type HEMT is because 25% low Al composition and 1 * 1018cm in the AlGaN barrier layer ^-3More low-doped density cause.Different with the AlGaN/GaN HEMT that is used for the RF/ microwave power amplifier, digital IC to current density require less.Shown in Figure 35 (b), obtain the low knee voltage of 2.5V for E type HEMT.On the gate bias of 2.5V, realize the conducting resistance of 7.1 Ω mm for E type HEMT, it is identical with the conducting resistance of D type HEMT on the identical saturated current level.A kind of observed result is, HEMT compares with the D type, oppositely and the grid current in the forward biased condition in E type HEMT, significantly reduce, shown in Figure 37 (a).The mechanism that this grid current suppresses is by the electromotive force in the electronegative fluorine ion modulation AlGaN potential barrier of being introduced by plasma treatment.By finding the solution Poisson's equation and Fermi-Di Lake statistics, for D and E type HEMT simulation guide margin band figure.For the simulation conduction band of E type HEMT, the distribution curve that fluorine distributes comes approximate calculation by linear function, and the characteristics of this function are at the lip-deep 3 * 1019cm of AlGaN ^-3Maximum fluorinion concentration and on the AlGaN/GaN interface, reached for zero (can ignore).About 3 * 1013cm ^-2Total fluorine ion sheet concentration be enough to not only compensate about 3.7 * 1012cm ^-2Si+ alms giver's concentration, but also compensation piezoelectricity and spontaneous polarization charge inducing (about 1 * 1013cm ^-2).Should be noted that schottky barrier height that grid/AlGaN ties is assumed in this example remains unchanged.From Figure 37 (b) and the simulation conduction band (c) see that the electromotive force of AlGaN potential barrier can significantly improve by the adding of fluorine ion, thereby Schottky barrier that produce to strengthen and follow-up grid current suppress.Grid current in the forward bias suppresses to use useful especially for digital IC.The grid current that suppresses allows the gate bias of E type device to be increased to 2.5V.This increase produces bigger grid swing, the more great dynamic range of input and higher fan-out.The input voltage swing that increases allows higher supply voltage, and it is in the higher service speed that realizes digital IC and be a key factor during strong noise tolerance limit more.The grid input that does not have to increase is swung, and bigger supply voltage will produce the output voltage (at logic " height ") of the conducting voltage of the input grid that surpasses next stage.The more wide dynamic range of input realizes the direct loic level match between input and the output, thereby eliminates the needs to the level adjustment between the adjacent level.

Should be noted that as the silicon nitride passivation that generally is used for based on the important technology of the stable operation of the HEMT of GaN and also can on than low degree, influence threshold voltage.In general, the deposit of silicon nitride passivation on active region can change the stress in AlGaN and the GaN layer.Subsequently, the piezoelectric polarization charge density of device and threshold voltage can pass through minor modifications.In general, in the AlGaN layer, introduce additional tensile stress, thereby produce the negative displacement of the threshold voltage in the scope of a few tenths of volt by the widely used silicon nitride layer of high frequency PECVD deposit.In fact, this influence should take in technological design.Plasma treatment dosage can correspondingly increase, thereby compensation is by the negative displacement in the threshold voltage of SiN passivation layer generation.The stress of SiN passivation layer also can reduce by the technological parameter of revising the PECVD deposit, makes that the negative displacement in the threshold voltage is minimum.

Example: DCFL inverter

The circuit diagram of E/D HEMT inverter is shown in Fig. 1 (a), and therein, D type HEMT is as load, and its grid is connected to its source electrode, and E type HEMT is as driver.Figure 1B explanation is according to the making microphoto of the inverter of the innovation.The inverter of making adopts the HP4156A parameter analyzer to characterize.Figure 38 illustrates the quiescent voltage transfer characteristic (block curve) of typical E/D HEMT inverter.(rising of＞2.1V) output voltage is the result of grid Schottky diode conducting at big input voltage.Dashed curve is the identical transfer curve with exchanger axis, and represents the input-output characteristic of next inverter stage.Parameter-definition is abideed by for described based on the HEMT of GaAs and InP.Static output level (V _OHAnd V _OL) given by two joinings of the curve of stable equilibrium point, and the difference between two level is defined as the output logic voltage swing.Inverter threshold voltage (V _TH) be defined as V _In, V wherein _InEqual V _OutStatic noise margin adopts logic low noise margin (NM _L) and logic high noise margin (NM _H) the method for Breadth Maximum measure.In Figure 39, drawn at supply voltage V _DD=1.5V has the measurement quiescent voltage transfer curve of the E/D inverter of from 6.7 to 50 β that change.High output logic level (V _OH) remain 1.5V, show that E type HEMT disconnects fully, and low output logic level (V _OL) because β is increased to 50 and be improved to 0.09V from 0.34 from 6.7.Therefore, be defined as V _OH-V _OLOutput logic swing be increased to 1.41V from 1.16.When β when 6.7 are increased to 50, V _THBe reduced to 0.61V from 0.88, the dc voltage gain (G) in the range of linearity is increased to 4.1 from 2.Figure 40 lists static noise margin and V _OH, V _OL, output logic swing, V _THMeasured value with G.NM _LAnd NM _HAll increase and improve with β.

The quiescent voltage transfer curve of inverter with β=10 is measured on different supply voltages, and in Figure 41 curve plotting.Circuit performance parameters is listed in Figure 42.When supply voltage increases, the corresponding increase of all parameters of E/D inverter.This means that the increase of supply voltage improves the static properties of E/D inverter.As everybody knows, for HEMT and MESFETE/D inverter, input voltage is subjected to the conducting voltage restriction of grid Schottky diode all the time.When big input voltage, the grid conduction causes the voltage drop that increases on the parasitic source resistance as the E type device of driver, thereby improves the voltage of logic low.When supply voltage and the increase of required input voltage, can in static transfer curve, observe the rising of output voltage, as shown in figure 41.Grid current may make the ability of a plurality of grades of inverter drive obviously demote when increasing by big input voltage, thereby reduces fan-out.Usually, the conducting voltage of grid Schottky diode is approximately 1V for conventional AlGaN/GaN HEMT.For grid groove E type GaNHEMT, the AlGaN potential barrier of attenuation further reduces conducting voltage because of the tunnelling current that improves.Therefore, for the inverter based on grid groove E type GaN HEMT, output voltage raises when input voltage surpasses 0.8V.As previously described, pass through CF ₄The E type GaN HEMT that plasma treatment is made has repressed grid current because of the Schottky barrier that strengthens in the AlGaN layer, and it is caused by the negative electricity fluorine ion.A kind of like this grid current suppresses to realize the big input voltage swing of E/D inverter.Can see that in Figure 41 the rising of output voltage did not take place before input voltage surpasses 2V, show about 1V expansion of input voltage swing.Figure 43 illustrates the correlation of load current and input current and input voltage.Lower input current (grid current of E type HEMT) shows bigger fan-out amount.At " conducting " state, when input voltage during greater than 2V, input current surpasses 10% load current.

Example: DCFL ring oscillator

Figure 1B illustrates the schematic circuit diagram of DCFL ring oscillator, and it adopts odd number E/D chain of inverters to form.17 grades of ring oscillators adopt β=6.7,10 and 25 of inverter to make.For each ring oscillator, adopt 36 transistors, comprise output buffer.Fig. 1 D explanation is according to the microphoto of the made ring oscillator of the innovation.Ring oscillator utilizes Agilent E4404B spectrum analyzer and HP 54522A oscilloscope to characterize on wafer.Operating period at ring oscillator is also measured the DC power consumption.Figure 44 and 45 explanations are at V _DDThe frequency domain and the time domain specification of 17 grades of ring oscillators with β=10 of=3.5V biasing.The fundamental oscillation frequency is 225MHz.Formula τ pd=(2nf) according to every grade propagation delay ^-1, wherein progression is 17, and τ _PdBe calculated as the 130ps/ level.In Figure 46, drawn τ _PaWith power delay product to V _DDCorrelation.Along with the increase of supply voltage, propagation delay is reduced, and power delay product then increases.With at the measured τ of 1V _PdCompare (234ps/ level), at the measured τ of 3.5V _PdReduce 45%.Ring oscillator can be at this high V _DDThe fact of last work is owing to employed CF in the integrating process ₄The bigger input voltage swing that the plasma treatment technology is realized.V at 1V _DDThe minimum power of last discovery 0.113pJ/ level postpones product.Figure 46 also illustrates the τ of the ring oscillator with β=6.7 and 25 _PdAnd power delay product characteristic.For ring oscillator with β=6.7, bigger τ _PdWith power delay product is because the determined bigger input capacitance of bigger grid length (1.5 μ m) of E type HEMT causes.For ring oscillator with β=25, bigger τ _PdBe because the determined lower charging current of bigger grid length (4 μ m) of D type HEMT causes that power delay product then is in the grade identical with the ring oscillator with β=10.When this integrated technology is realized, estimate that the gate delay time can further reduce in the sub-micron system.

Recently, discrete E type HEMT and DCFL ring oscillator are tested with the elevated temperature up to 375C.In the threshold voltage of E type HEMT, do not observe obvious displacement, and ring oscillator presents the frequency of oscillation of 70MHz at 375C.

Creative embodiment according to disclosed classification, provide: a kind of method that is used to make the semiconductor active device, comprise following action: a) vertically not homogeneity III-N semiconductor layer form pattern so that the channel region of exposure the first transistor rather than the channel region of transistor seconds; B) fluorine is added the described channel region of described the first transistor, but do not add the described channel region of described transistor seconds in fact, thereby provide different threshold voltages for described first and second transistors; And c) forms source electrode, drain and gate, so that finish described transistorized formation; Wherein said action (b) makes described the first transistor rather than described transistor seconds have positive threshold voltage.

Creative embodiment according to disclosed classification provides: a kind of method that is used to make III-N semiconductor active device comprises following action: have (Al _xM _(1-x)) vertically not in the homogeneity semiconductor layer of general composition of Y, on expection depletion mode transistor raceway groove position, form first grid electrode pattern, wherein M mainly is that Ga and Y mainly are N, and the Al share is higher at the near surface of described layer; Introduce fluorine and formation second gate electrode pattern in the self-aligning action combination, on expection enhancement transistor raceway groove position; And form source electrode, drain electrode and interconnection, so that finish the formation of circuit.

Creative embodiment according to disclosed classification provides: a kind of integrated circuit comprises: enhancement mode and depletion mode transistor reciprocally interconnect to form circuit; Wherein, described transistor all has the raceway groove that forms in the common layer of the vertical not homogeneity III hi-nitride semiconductor material of the higher Al share of the near surface that is included in described layer; And wherein said enhancement transistor has fluorine concentration at least one horizontal plane of described layer, and it is higher than 1,000 times of fluorine concentration in the appropriate section of the described layer on the described depletion mode transistor.

Modifications and changes

Person of skill in the art will appreciate that the described creative notion of the application can make amendment and change in the application of very big scope, and the scope of patented subject matter the concrete exemplary teachings that provided correspondingly is not provided any limit.

Disclosed technology also can be used for setting up the merging device, and therein, enhancing and depleted transistor are combined in the single isolated area.

For another example, the minor change of semiconductor composition, for example phosphorous nitride replace the use of pure nitride or for basic HEMT structure at Al _yGa _(1-y)Al on the N heterostructure _xGa _(1-x)The use of N is considered to alternative.

The innovation provides the ability of making univoltage power supply RFIC and MMIC for the user.It also is provided for realizing the single slice integration technique based on the digital integrated circuit of GaN that the high-temperature electronic circuit is required for the user.

For another example, shown in various device architectures in, various materials can be used for gate electrode any difference that produces of work function (consider) alternatively.

In a class embodiment who is considered, grid material with different work functions can be used in combination with the sheet charge layer of capturing that above-described various embodiment is provided, so that increase the difference (for given fluorine dosage) between two types the transistorized threshold voltage.Perhaps, this can be used for realizing as required four kinds of different threshold voltages on single III-N chip.

Similarly, can in mixing, epitaxial loayer carry out various variations or alternative.

Similarly, as mentioned above, various materials can be used for substrate alternatively.

Above-described method and structure is not only applicable to HEMT or MISHFET device, and is applicable to III-N MESFET (metal semiconductor FET) and MOSFET device.(the MESFET device does not adopt gate insulator, but provides Schottky barrier between grid and raceway groove.)

The additional general background that helps the explanation change and realize is found in following publication, by reference it all is incorporated into this:

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" the non-groove grids enhanced AlGaN/GaN High Electron Mobility Transistor " of Endoh, Y.Yamashita, K.Ikeda, M.Higashiwaki, K.Hikosaka, T.Matsui, S.Hiyamizu and T.Mimura with high RF performance, Jpn.J.Appl.Phys., vol.43, no.4B, the 2255-2258 page or leaf, 2004;

" the AlGaN/GaN metal-oxide semiconductor (MOS) hetero-structure field effect transistor " of M.A.Khan, X.Hu, G.Sumin, A.Lunev, J.Yang, R.Gaska and M.S.Shur, IEEEElectron Device Lett., vol.21, no.2, the 63-65 page or leaf, in February, 2000;

" the Si of X.Hu, A.Koudymov, G.Simin, J.Yang and M.A.Khan ₃N ₄/ AlGaN/GaN-metal-insulator semiconductor (MIS) hetero-structure field effect transistor ", Appl.Phys.Lett., vol.79, no.17,2832-2834 page or leaf, October calendar year 2001;

" power of the GaN MISFET on the Sapphire Substrate and the linearity characteristic " of Chini, J.Wittich, S.Heikman, S.Keller, S.P.DenBaars and U.K.Mishra, IEEEElectron Device Lett., Vol.25, No.2, the 55-57 page or leaf, in February, 2004;

" be used for wireless base station applications surpass 100W n-GaN/n-AlGaN/GaN MIS-HEMT power amplifier " of M.Kanamura, T.Kikkawa, T.Iwai, K.Imanishi, T.Kubo and K.Joshin, IEDM Tech.Dig., in December, 2005, the 572-575 page or leaf intactly is incorporated into this with it by reference;

The application US20030218183 that announces, " high-power low-noise microwave GaN hetero-structure field effect transistor ";

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" the planar GaAs IC technology: the application of digital LSI " of R.C.Eden, B.M.Welch and R.Zucca, IEEE J.Solid-State Circuits, vol.13, no.4,419-426 page or leaf, in August, 1978;

" manufacturing of high density GaAs integrated circuit " of J.M.Mikkelson and L.R.Tomasetta, IEEE Trans.Semicond.Manuf., vol.16, no.3,384-389 page or leaf, in August, 2003;

R.Kirschman Ed., high-temperature electronic circuit, New York:IEEE Press, 1999;

S.Long and S.E.Butner, the GaAs Design of Digital Integrated Circuit.New York:McGraw-Hill, nineteen ninety;

" the GaN HFET digital circuit technique that is used for adverse circumstances " of T.Hussain, M.Micovic, T.Tsen, M.Delaney, D.Chow, A.Schmitz, P.Hashimoto, D.Wong, J.S.Moon, M.Hu, J.Duvall and D.McLaughlin, Electron.Lett., vol.39, no.24, the 1708-1709 page or leaf, in November, 2003;

" monolithic that is used for the enhancing of GaN digital integrated circuit and depletion-mode AlGaN/GaN HEMT is integrated " of Y.Cai, Z.Cheng, C.W.Tang, K.J.Chen and K.M.Lau, 2005International Electron Device Meeting (IEDM05), Washington D.C., USA, 4-7 day in December, 2005;

" adopting the monolithic-integrated enhancement/depletion-type AlGaN/GaN HEMT inverter and the ring oscillator of CF4 plasma treatment " of Y.Cai, Z.Cheng, W.C.K.Tang, K.M.Lau and K.J.Chen, IEEE Trans.Electron Devices, vol.53, No.9, the 2223-2230 page or leaf, in September, 2006;

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Any description not should be understood to hint that any concrete element, step or function are the essential elementss that must be included in the claim scope among the application.The scope of patented subject matter is only defined by the claim that allows.In addition, neither one is intended to quote the 6th section of 35USC the 112nd joint in these claims, unless definite word " be used for ... parts " follow participle afterwards.

The claim of being submitted to is intended to comprehensive as far as possible, and do not have theme abandoned intentionally, special-purpose or abandon.

Claims (26)

1. method that is used to make the semiconductor active device comprises following action:

A) vertically not homogeneity III-N semiconductor layer form pattern so that make the channel region exposure of the channel region rather than the transistor seconds of the first transistor;

B) fluorine is introduced the described channel region of described the first transistor, but do not introduced the described channel region of described transistor seconds basically, so that provide different threshold voltages for described first and second transistors; And

C) form source electrode, drain and gate, thereby finish described transistorized formation;

Wherein, described action (b) makes described the first transistor rather than described transistor seconds have positive threshold voltage.

2. the method for claim 1, wherein described semiconductor layer is the AlGaN/GaN hierarchy.

3. the method for claim 1, wherein described step (b) is also introduced device isolation region to fluorine.

4. the method for claim 1, wherein fluorine is introduced the position of the described grid of described action autoregistration of the described channel region of described the first transistor.

5. the method for claim 1, wherein described semiconductor layer is the epitaxial loayer by the substrate supports of sapphire, silicon, SiC, AlN or GaN.

6. the method for claim 1, wherein described semiconductor layer is the epitaxial structure of the resilient coating, GaN raceway groove and the AlGaN potential barrier that comprise coring layer, GaN or the AlGaN of GaN or AlN.

7. the method for claim 1, wherein described transistorized described source electrode and described drain electrode form by a plurality of metal levels of deposit and rapid thermal annealing, and wherein, described metal is chosen from the group that is made of Ti, Al, Ni and Au.

8. the method for claim 1, wherein described channel region is through the plasma treatment based on fluorine, and this is handled and adopts from by CF ₄, SF ₆, BF ₃And composition thereof the unstripped gas chosen in the group that constitutes.

The method of claim 1, wherein gate electrode by the deposit gate metal, peel off then or metal etch forms, adopt at least a metal of from the group that constitutes by Ti, Al, Ni and Au, choosing.

10. the method for claim 1 also is included in the subsequent step of the passivating material that deposit is chosen on the described transistor from the group that is made of silicon nitride, silica, polyimides and benzocyclobutene.

11. the method for claim 1, wherein described first and described transistor seconds all through roughly at the final thermal annealing of the maximum temperature that can not change the Schottky barrier under the grid.

12. the method for claim 1, wherein Fu Jia dielectric material film is inserted between described grid and the semi-conductive surface of III-N, thus, described the first transistor and described transistor seconds all are integrated among the HFET of metal-insulator semiconductor (MIS) by monolithic.

13. the method for claim 1, wherein the plasma treatment based on fluorine is used for realizing device isolation.

14. method as claimed in claim 13 wherein, is enabled plane monolithic integrated technique.

15. method as claimed in claim 14, wherein, additional dielectric material film is inserted between described grid and the semi-conductive surface of III-N, and thus, described the first transistor and described transistor seconds all are integrated among the HFET of metal-insulator semiconductor (MIS) by monolithic.

16. a method that is used to make III-N semiconductor active device comprises following action:

Has (Al _xM _(1-x)) vertically not in the homogeneity semiconductor layer of general composition of Y, on expection depletion mode transistor raceway groove position, form first grid electrode pattern, wherein, M mainly is that Ga and Y mainly are N, and the Al share is higher at the near surface of described layer;

In self aligned combination of actions, on expection enhancement transistor raceway groove position, introduce fluorine and form second gate electrode pattern; And

Form source electrode, drain electrode and interconnection, so that finish the formation of circuit.

17. method as claimed in claim 16, wherein, described semiconductor layer is the epitaxial loayer that substrate supported by sapphire, silicon, SiC, AlN or GaN.

18. method as claimed in claim 16, wherein, described semiconductor layer is the epitaxial structure of the resilient coating, GaN raceway groove and the AlGaN potential barrier that comprise coring layer, GaN or the AlGaN of GaN or AlN.

19. method as claimed in claim 16, wherein, described source electrode and described drain electrode form by a plurality of metal levels of deposit and rapid thermal annealing, and wherein, described metal is chosen from the group that is made of Ti, Al, Ni and Au.

20. method as claimed in claim 16, wherein, described expection enhancement transistor raceway groove position is through based on the plasma treatment of fluorine, and this is handled and adopts from by CF ₄, SF ₆, BF ₃And composition thereof the unstripped gas chosen in the group that constitutes.

21. method as claimed in claim 16, wherein, gate electrode by the deposit gate metal, peel off then or metal etch forms, adopt at least a metal of from the group that constitutes by Ti, Al, Ni and Au, choosing.

22. method as claimed in claim 16 also comprises the subsequent step of the passivating material that deposit is chosen from the group that is made of silicon nitride, silica, polyimides and benzocyclobutene.

23. an integrated circuit comprises:

Enhancement mode and depletion mode transistor reciprocally interconnect to form circuit;

Wherein, described transistor all has the raceway groove that forms in the common layer of vertical not homogeneity III hi-nitride semiconductor material, has higher Al share at described layer near surface; And

Wherein, described enhancement transistor has fluorine concentration at least one horizontal plane of described layer, and it is higher than 1,000 times of fluorine concentration in the counterpart of described layer at described depletion mode transistor place.

24. circuit as claimed in claim 23, wherein, described semi-conducting material is the epitaxial loayer that substrate supported by sapphire, silicon, SiC, AlN or GaN.

25. circuit as claimed in claim 23, wherein, described semi-conducting material is the epitaxial structure of the resilient coating, GaN raceway groove and the AlGaN potential barrier that comprise coring layer, GaN or the AlGaN of GaN or AlN.

26. circuit as claimed in claim 23 also comprises the subsequent step of the passivating material that deposit is chosen from the group that is made of silicon nitride, silica, polyimides and benzocyclobutene.

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