CN101399086B - Displacement register and grid drive device thereof - Google Patents
Displacement register and grid drive device thereof Download PDFInfo
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- CN101399086B CN101399086B CN200710122584XA CN200710122584A CN101399086B CN 101399086 B CN101399086 B CN 101399086B CN 200710122584X A CN200710122584X A CN 200710122584XA CN 200710122584 A CN200710122584 A CN 200710122584A CN 101399086 B CN101399086 B CN 101399086B
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Abstract
The invention relates to a shift register and a gate driving device thereof. The shift register comprises a first film transistor which is directly deposited on an array substrate, a ninth film transistor, an eleventh film transistor and a plurality of control modules. The gate driving device comprises a displacement initial signal output end, a gate off-state voltage output end, a first clock signal output end, a second clock signal output end, a first shift register and a second shift register. The shift register and the gate driving device lower the gate bias stress of the film transistor, avoid the rise of the gate threshold voltage to the maximum, prolong the service life of the film transistor and avoid the misoperation that the film transistor is closed during the invalid state. Compared with the prior art, no additional power supplying circuit is required, the circuit is simple, the stable working can be ensured, and the cost is low.
Description
Technical field
The present invention relates to a kind of shift register and gate drive apparatus thereof, shift register and gate drive apparatus thereof in particularly a kind of liquid crystal display drive circuit.
Background technology
Characteristics such as that Thin Film Transistor-LCD (TFT-LCD) has is in light weight, thin thickness and use power are low are widely used in the devices such as mobile phone, display, televisor.
For display image, the matrix of lining by line scan that TFT-LCD arranges with m * n point shows.The TFT-LCD driver mainly comprises gate drivers and data driver, data driver latchs the video data and the clock signal timing of input in proper order, convert the data line that is input to liquid crystal panel after the simulating signal to, gate drivers is changed the clock signal of input by shift register, switch to unlatching/shutoff voltage, be applied on the liquid crystal panel in turn.In active matrix thin film transistor liquid crystal display (TFT-LCD) (AM TFT-LCD), the shift register in the gate drivers is used to produce the sweep signal of scanning grid line, and the shift register in the data driver is used to select the data line module.
In the prior art shift register, in order to keep shift register disarmed state at different levels, all importing on each field effect transistor has constant voltage, and at this moment, field effect transistor can produce gate bias stress (gate biasstress).This gate bias stress makes the threshold voltage of the grid (gate thresholdvoltage) of field effect transistor raise, and the rising of threshold voltage of the grid can cause might occurring under the disarmed state field effect transistor generation drop-down (pull-down) pent maloperation in long-term the use.
The maloperation of prior art in order to prevent that threshold voltage of the grid from rising and causing, all the rising direct ratio according to threshold voltage of the grid increases supply voltage, and the increase of supply voltage need increase extra feed circuit, causes cost to rise.
Summary of the invention
The purpose of this invention is to provide a kind of shift register and gate drive apparatus thereof, effectively solve existing shift register and cause technological deficiencies such as threshold voltage of the grid rising because of gate bias stress.
To achieve these goals, the invention provides a kind of shift register, comprise the first film transistor, the 9th thin film transistor (TFT), the 11 thin film transistor (TFT) and several control modules that directly are deposited on the array base palte, wherein:
The first film transistor, its grid is connected with the output terminal of upper level shift register, and its drain electrode is connected with its grid, and its source electrode is connected with the grid of the 11 thin film transistor (TFT);
The 9th thin film transistor (TFT), its drain electrode is connected with output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal;
The 11 thin film transistor (TFT), its grid is connected with the transistorized source electrode of the first film, and its drain electrode is connected with first clock signal output terminal, and its source electrode is connected with output terminal at the corresponding levels;
First control module is connected with power supply negative terminal with the second clock signal output part respectively, is used to receive the second clock signal; Described first control module comprises: second thin film transistor (TFT), and its grid is connected with the second clock signal output part, and its drain electrode is connected with the first film transistor drain, and its source electrode is connected with the transistorized source electrode of the first film; The 3rd thin film transistor (TFT), its drain electrode is connected with the source electrode of second thin film transistor (TFT); The 4th thin film transistor (TFT), its grid is connected with the second clock signal output part, and its drain electrode is connected with the source electrode of the 3rd thin film transistor (TFT) and is connected to output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal;
Second control module is connected the rising that is used to receive first clock signal and slows down the threshold voltage of the grid of the 9th thin film transistor (TFT) respectively with first clock signal output terminal, first control module and the grid of the 9th thin film transistor (TFT); Described second control module comprises: the 5th thin film transistor (TFT), and its grid is connected with the grid of the 3rd thin film transistor (TFT), and its drain electrode connects its grid and is connected with first clock signal output terminal; The 7th thin film transistor (TFT), its grid is connected with the source electrode of the 5th thin film transistor (TFT), and its drain electrode is connected with the drain electrode of the 5th thin film transistor (TFT), and its source electrode is connected with the grid of the 9th thin film transistor (TFT);
The 3rd control module is connected with first control module, power supply negative terminal and the grid of the 9th thin film transistor (TFT) respectively, is used to keep the disarmed state of the 9th thin film transistor (TFT); Described the 3rd control module comprises: the 6th thin film transistor (TFT), and its grid is connected with output terminal at the corresponding levels, and its drain electrode is connected with the source electrode of the 5th thin film transistor (TFT), and its source electrode is connected with power supply negative terminal; The 8th thin film transistor (TFT), its grid is connected with output terminal at the corresponding levels, and its drain electrode is connected with grid with the 9th thin film transistor (TFT), and its source electrode is connected with power supply negative terminal;
The 4th control module, the output terminal with output terminal at the corresponding levels, next stage shift register is connected with power supply negative terminal respectively, is used to keep the no-output state of output terminal at the corresponding levels.
Wherein, described the 4th control module comprises:
The tenth thin film transistor (TFT), its grid is connected with the output terminal of next stage shift register, and its drain electrode is connected with the grid of the 11 thin film transistor (TFT), and its source electrode is connected with power supply negative terminal;
The 12 thin film transistor (TFT), its grid and the grid of the tenth thin film transistor (TFT) are connected and are connected to the output terminal of next stage shift register, and its drain electrode is connected with the source electrode of the 11 thin film transistor (TFT) and is connected to output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal.
To achieve these goals, the present invention also provides a kind of gate drive apparatus that comprises above-mentioned shift register, comprise displacement start signal output terminal, gate off voltage output terminal, first clock signal output terminal, second clock signal output part, first shift register and second shift register, wherein:
First shift register is connected with the gate off voltage output terminal with displacement start signal output terminal, first clock signal output terminal, second clock signal output part respectively, has first control signal output ends of output first control signal;
Second shift register, be connected with first control signal output ends, second clock signal output part, first clock signal output terminal and gate off voltage output terminal respectively, have second control signal output ends of output second control signal, described second control signal output ends is connected with first shift register.
The present invention proposes a kind of shift register that directly is deposited on the array base palte, the high level of exporting successively by first clock signal output terminal and second clock signal output part has effectively kept the OFF state of output terminal at the corresponding levels, have only when first clock signal output terminal output high level, the grid of thin film transistor (TFT) just is applied in voltage, and when second clock signal output part output high level, the grid of thin film transistor (TFT) does not have voltage, make shift register of the present invention guarantee that output terminal at the corresponding levels keeps under the OFF state, the grid of thin film transistor (TFT) is under the back-lash voltage effect, effectively reduce gate bias stress, reduced the threshold voltage of the grid trend of rising.Further; shift register of the present invention is by being provided with two thin film transistor (TFT)s that shield between the grid of thin film transistor (TFT) and first clock signal output terminal; further reduced the gate bias stress of thin film transistor (TFT); avoided the rising of threshold voltage of the grid to greatest extent; prolonged the life-span of thin film transistor (TFT), and prevented that thin film transistor (TFT) from pent maloperation may occur when disarmed state.Compare for the technical scheme that prevents threshold voltage of the grid rising increase supply voltage with prior art, the present invention need not increase extra feed circuit, and not only circuit is simple, can guarantee steady operation, and cost is low.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is the structural representation of shift register of the present invention;
Fig. 2 is the structural representation of shift register one embodiment of the present invention;
Fig. 3 is a shift register working timing figure of the present invention;
Fig. 4 is the structural representation of gate drive apparatus of the present invention.
Embodiment
Fig. 1 is the structural representation of shift register of the present invention.As shown in Figure 1, the agent structure of shift register of the present invention comprises three thin film transistor (TFT)s, four control modules and corresponding output terminal, three thin film transistor (TFT)s are the first film transistor T 1, the 9th thin film transistor (TFT) T9 and the 11 thin film transistor (TFT) T11, four control modules are the first control module C1, the second control module C2, the 3rd control module C3 and the 4th control module C4, output terminal is the output terminal OUTn-1 of upper level shift register, the output terminal OUTn of shift register at the corresponding levels, the output terminal OUTn+1 of next stage shift register, power supply negative terminal VSS, the first clock signal output terminal CKV1 and second clock signal output part CKV2, wherein the output terminal OUTn of shift register at the corresponding levels is connected with output terminal INPUTn+1 to the next stage shift register, when shift register of the present invention is used for gate drive apparatus, for output terminal OUTn-1, first shift register correspondence be displacement start signal output terminal STV, other shift register correspondences be the output terminal of upper level shift register.Particularly, the grid of the first film transistor T 1 is connected with the output terminal OUTn-1 of upper level shift register, and its drain electrode is connected with its grid, and its source electrode is connected with the grid of the 11 thin film transistor (TFT) T11; The grid of the 9th thin film transistor (TFT) T9 is connected with the 3rd control module C3 with the second control module C2, and its drain electrode is connected with the output terminal OUTn of shift register at the corresponding levels, and its source electrode is connected with power supply negative terminal VSS; Its grid of the 11 thin film transistor (TFT) T11 is connected with the source electrode of the first film transistor T 1, and its drain electrode is connected with the first clock signal output terminal CKV1, and its source electrode is connected with the output terminal OUTn of shift register at the corresponding levels; The first control module C1 is connected with power supply negative terminal VSS with second clock signal output part CKV2 respectively, is used to receive the second clock signal; The second control module C2 is connected the rising that is used to receive first clock signal and slows down the threshold voltage of the grid of the 9th thin film transistor (TFT) T9 with the grid of the first clock signal output terminal CKV1, the first control module C1 and the 9th thin film transistor (TFT) T9 respectively; The 3rd control module C3 is connected with the grid of the 9th thin film transistor (TFT) T9 with the first control module C1, power supply negative terminal VSS respectively, is used to keep the disarmed state of the 9th thin film transistor (TFT) T9; The 4th control module C4 is connected with power supply negative terminal VSS with the output terminal OUTn of shift register at the corresponding levels, the output terminal OUTn+1 of next stage shift register respectively, is used to keep the no-output state of output terminal OUTn at the corresponding levels.
Fig. 2 is the structural representation of shift register one embodiment of the present invention.As shown in Figure 2, the first control module C1 comprises the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4, the second control module C2 comprises the 5th thin film transistor (TFT) T5 and the 7th thin film transistor (TFT) T7, the 3rd control module C 3 comprises the 6th thin film transistor (TFT) T6 and the 8th thin film transistor (TFT) T8, the 4th control module C4 comprises the tenth thin film transistor (TFT) T10 and the 12 thin film transistor (TFT) T12, and final formation directly is deposited on 12 thin film transistor (TFT)s (TFT) and corresponding input end and the output terminal on the array base palte.Particularly, the grid of the first film transistor T 1 is connected with the output terminal OUTn-1 of upper level shift register, and its drain electrode is connected with its grid, and its source electrode is connected with the source electrode of the second thin film transistor (TFT) T2; The grid of the second thin film transistor (TFT) T2 is connected with second clock signal output part CKV2, and its drain electrode is connected with the drain electrode of the first film transistor T 1, and its source electrode is connected with the source electrode of the first film transistor T 1; The grid of the 3rd thin film transistor (TFT) T3 is connected with the grid of the 5th thin film transistor (TFT) T5, its drain electrode is connected with the source electrode of the first film transistor T 1 and the source electrode of the second thin film transistor (TFT) T2 respectively, and being connected to the grid of the 11 thin film transistor (TFT) T11, its source electrode is connected with the drain electrode of the 4th thin film transistor (TFT) T4; The grid of the 4th thin film transistor (TFT) T4 is connected with second clock signal output part CKV2, its drain electrode is connected with the source electrode of the 3rd thin film transistor (TFT) T3 and is connected to output terminal OUTn at the corresponding levels (to the output terminal INPUTn+1 of next stage shift register), and its source electrode is connected with power supply negative terminal VSS; The grid of the 5th thin film transistor (TFT) T5 is connected with the grid of the 3rd thin film transistor (TFT) T3, and its drain electrode connects its grid and is connected with the first clock signal output terminal CKV1, and its source electrode is connected with the drain electrode of the 6th thin film transistor (TFT) T6; The grid of the 6th thin film transistor (TFT) T6 is connected with output terminal OUTn at the corresponding levels (to the output terminal INPUTn+1 of next stage shift register), and its drain electrode is connected with the source electrode of the 5th thin film transistor (TFT) T5, and its source electrode is connected with power supply negative terminal VSS; The grid of the 7th thin film transistor (TFT) T7 is connected with the source electrode of the 5th thin film transistor (TFT) T5 and the drain electrode of the 6th thin film transistor (TFT) T6 respectively, its drain electrode is connected with the drain electrode of the 5th thin film transistor (TFT) T5, and being connected to the first clock signal output terminal CKV1, its source electrode is connected with the drain electrode of the 8th thin film transistor (TFT) T8; The grid of the 8th thin film transistor (TFT) T8 is connected with output terminal OUTn at the corresponding levels (to the output terminal INPUTn+1 of next stage shift register), and its drain electrode is connected with the source electrode of the 7th thin film transistor (TFT) T7, and its source electrode is connected with power supply negative terminal VSS; The grid of the 9th thin film transistor (TFT) T9 is connected with the source electrode of the 7th thin film transistor (TFT) T7 and the drain electrode of the 8th thin film transistor (TFT) T8 respectively, and its drain electrode is connected with output terminal OUTn at the corresponding levels, and its source electrode is connected with power supply negative terminal VSS; The grid of the tenth thin film transistor (TFT) T10 is connected with the grid of the 12 thin film transistor (TFT) T12, and be connected to the output terminal OUTn+1 of next stage shift register, its drain electrode is connected with the grid of the 11 thin film transistor (TFT) T11, and being connected to the source electrode of the first film transistor T 1, the source electrode of the second thin film transistor (TFT) T2 and the drain electrode of the 3rd thin film transistor (TFT) T3, its source electrode is connected with power supply negative terminal VSS; The grid of the 11 thin film transistor (TFT) T11 is connected with the source electrode of the first film transistor T 1, the source electrode of the second thin film transistor (TFT) T2, the drain electrode of the 3rd thin film transistor (TFT) T3 and the drain electrode of the tenth thin film transistor (TFT) T10 respectively, its drain electrode is connected with the first clock signal output terminal CKV1, its source electrode is connected with the drain electrode of the 12 thin film transistor (TFT) T12, and is connected to output terminal OUTn at the corresponding levels; The grid of the 12 thin film transistor (TFT) T12 is connected with the grid of the tenth thin film transistor (TFT) T10, and be connected to the output terminal OUTn+1 of next stage shift register, its drain electrode is connected with the drain electrode of the 9th thin film transistor (TFT) T9 and the source electrode of the 11 thin film transistor (TFT) T11 respectively, and being connected to output terminal OUTn at the corresponding levels, its source electrode is connected with power supply negative terminal VSS.
Fig. 3 is a shift register working timing figure of the present invention.As shown in Figure 3, at first by displacement start signal output terminal STV output high level.When displacement start signal output terminal STV output high level,, then start the first film transistor T 1 because the grid of the first film transistor T 1 is connected with displacement start signal output terminal STV; Because the drain electrode of the first film transistor T 1 is connected with grid, the source electrode of the first film transistor T 1 is connected with the grid of the 11 thin film transistor (TFT) T1, and high level is applied on the grid of the 11 thin film transistor (TFT) T11 from the drain electrode of the first film transistor T 1 source electrode by the first film transistor T 1; Because this moment, the first clock signal output terminal CKV1 did not have signal, therefore the electric charge of the 11 thin film transistor (TFT) T11 grid was added up gradually (shown in T11 gate switch signal among Fig. 3).The high level of first clock signal output terminal CKV1 output afterwards.Because the grid of the 11 thin film transistor (TFT) T11 is in high level state always, so during first clock signal output terminal CKV1 output high level, the 11 thin film transistor (TFT) T11 starts, and the high level of first clock signal output terminal CKV1 output adds that electric charge that the 11 thin film transistor (TFT) T11 grid added up is together to output terminal OUTn output at the corresponding levels (shown in output terminal OUTn at the corresponding levels among Fig. 3).The high level of second clock signal output part CKV2 output afterwards.Because the grid of the 4th thin film transistor (TFT) T4 is connected with second clock signal output part CKV2, then starts the 4th thin film transistor (TFT) T4; Because the source electrode of the 4th thin film transistor (TFT) T4 is connected with power supply negative terminal VSS, the drain electrode of the 4th thin film transistor (TFT) T4 is connected with output terminal OUTn at the corresponding levels, therefore after the 4th thin film transistor (TFT) T4 opens the drain electrode of the 4th thin film transistor (TFT) T4 is connected with output terminal OUTn at the corresponding levels with power supply negative terminal VSS, makes output terminal OUTn at the corresponding levels be in the OFF state.
Said process makes output terminal OUTn at the corresponding levels realize once output, therefore in the time subsequently, the high level that shift register of the present invention is exported successively by the first clock signal output terminal CKV1 and second clock signal output part CKV2 keeps the OFF state of output terminal OUTn at the corresponding levels.Particularly, when first clock signal output terminal CKV1 output high level subsequently,, then start the 5th thin film transistor (TFT) T5 because the grid of the 5th thin film transistor (TFT) T5 is connected with the first clock signal output terminal CKV1; Because the grid of the 5th thin film transistor (TFT) T5 is connected with drain electrode, it is high level that the 5th thin film transistor (TFT) T5 opens the source electrode that then makes the 5th thin film transistor (TFT) T5; Because the grid of the 7th thin film transistor (TFT) T7 is connected with the source electrode of the 5th thin film transistor (TFT) T5, then starts the 7th thin film transistor (TFT) T7; Because the drain electrode of the 7th thin film transistor (TFT) T7 is connected with the drain electrode of the 5th thin film transistor (TFT) T5, the 7th thin film transistor (TFT) T7 opens the source electrode that then makes the 7th thin film transistor (TFT) T7 and also is high level; Because the grid of the 9th thin film transistor (TFT) T9 is connected with the source electrode of the 7th thin film transistor (TFT) T7, then starts the 9th thin film transistor (TFT) T9; Because the source electrode of the 9th thin film transistor (TFT) T9 is connected with power supply negative terminal VSS, it is low level that the 9th thin film transistor (TFT) T9 opens the drain electrode that then makes the 9th thin film transistor (TFT) T9, finally makes output terminal OUTn at the corresponding levels keep OFF state (shown in T9 gate switch signal among Fig. 3).Subsequently when second clock signal output part CKV2 is high level because the grid of the 4th thin film transistor (TFT) T4 is connected with second clock signal output part CKV2, then start the 4th thin film transistor (TFT) T4; Because the source electrode of the 4th thin film transistor (TFT) T4 is connected with power supply negative terminal VSS, the 4th thin film transistor (TFT) T4 opens and makes the drain electrode of the 4th thin film transistor (TFT) T4 is low level; Because the drain electrode of the 4th thin film transistor (TFT) T4 is connected with output terminal OUTn at the corresponding levels, finally make output terminal OUTn at the corresponding levels keep the OFF state.
From technique scheme of the present invention as can be seen, the high level that shift register of the present invention is exported successively by the first clock signal output terminal CKV1 and second clock signal output part CKV2 has effectively kept the OFF state of output terminal OUTn at the corresponding levels, have only when first clock signal output terminal CKV1 output high level, the grid of the 9th thin film transistor (TFT) T9 just is applied in voltage, and when second clock signal output part CKV2 output high level, the grid of the 9th thin film transistor (TFT) T9 does not have voltage, therefore shift register of the present invention is guaranteeing that output terminal OUTn at the corresponding levels keeps under the OFF state, the grid of the 9th thin film transistor (TFT) T9 is under the back-lash voltage effect, effectively reduce gate bias stress, reduced the threshold voltage of the grid trend of rising.Further; shift register of the present invention is by being provided with the 5th thin film transistor (TFT) T5 and the 7th thin film transistor (TFT) T7 (second control module) that shields between the grid of the 9th thin film transistor (TFT) T9 and the first clock signal output terminal CKV1; further reduced the gate bias stress of the 9th thin film transistor (TFT) T9; avoided the rising of threshold voltage of the grid to greatest extent; prolonged the life-span of the 9th thin film transistor (TFT) T9, and prevented that thin film transistor (TFT) from pent maloperation may occur when disarmed state.
Shift register of the present invention can be realized by 5 masking process or 4 masking process in the LCD (Liquid Crystal Display) array technology, by vacant part outside the substrate active region or substrate edges place alignment film transistor, then it directly is deposited on the array base palte.
Fig. 4 is the structural representation of gate drive apparatus of the present invention.As shown in Figure 4, gate drive apparatus comprises the first shift register SFT12 and the second shift register SFT21, output terminal comprises displacement start signal output terminal STV, gate off voltage output end vo ff, the first clock signal output terminal CKV1 and second clock signal output part CKV2, comprises that also the first shift register SFT12 exports first output terminal OUT1 of first control signal and the second output terminal OUT2 that the second shift register SFT21 exports second control signal.Particularly,
The first shift register SFT12 is connected with displacement start signal output terminal STV, be used for receiving the displacement start signal, ff is connected with the gate off voltage output end vo, be used to receive gate off voltage (power supply negative terminal VSS), be connected with second clock signal output part CKV2 with the first clock signal output terminal CKV1 respectively, be used to receive first clock signal and second clock signal, be connected with the second output terminal OUT2 of the second shift register SFT21, be used to receive second control signal of the second shift register SFT21, export first control signal from the first output terminal OUT1 simultaneously.The second shift register SFT21 is connected with the first output terminal OUT1 of the first shift register SFT12, be used to receive first control signal, ff is connected with the gate off voltage output end vo, be used to receive gate off voltage, be connected with the first clock signal output terminal CKV1 with second clock signal output part CKV2 respectively, be used to receive the second clock signal and first clock signal, be connected with the output terminal of next stage shift register, be used to receive the next stage control signal, export second control signal from the second output terminal OUT2 simultaneously, and this second control signal is sent into the first shift register SFT12.
Displacement start signal output terminal STV at first exports initial pulse, the first shift register SFT12 receives first clock signal and second clock signal from the first clock signal output terminal CKV1 and second clock signal output part CKV2 respectively afterwards, first clock signal is a high level pulse, the second clock signal is a high level pulse of first clock signal and then, have the present invention first shift register SFT12 work of Fig. 1～structure shown in Figure 3, the course of work repeats no more; The first output terminal OUT1 of the first shift register SFT12 is after the second shift register SFT21 exports first control signal, the second shift register SFT21 receives the second clock signal and first clock signal from the second clock signal output part CKV2 and the first clock signal output terminal CKV1 respectively, the second clock signal is a high level pulse, first clock signal is a high level pulse of second clock signal and then, the present invention second shift register SFT21 work, repeat above-mentioned flow process, just realized lining by line scan of LCD.
It should be noted that at last: above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and scope of technical solution of the present invention.
Claims (3)
1. a shift register is characterized in that, comprises the first film transistor, the 9th thin film transistor (TFT), the 11 thin film transistor (TFT) and several control modules that directly are deposited on the array base palte, wherein:
The first film transistor, its grid is connected with the output terminal of upper level shift register, and its drain electrode is connected with its grid, and its source electrode is connected with the grid of the 11 thin film transistor (TFT);
The 9th thin film transistor (TFT), its drain electrode is connected with output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal;
The 11 thin film transistor (TFT), its grid is connected with the transistorized source electrode of the first film, and its drain electrode is connected with first clock signal output terminal, and its source electrode is connected with output terminal at the corresponding levels;
First control module is connected with power supply negative terminal with the second clock signal output part respectively, is used to receive the second clock signal; Described first control module comprises: second thin film transistor (TFT), and its grid is connected with the second clock signal output part, and its drain electrode is connected with the first film transistor drain, and its source electrode is connected with the transistorized source electrode of the first film; The 3rd thin film transistor (TFT), its drain electrode is connected with the source electrode of second thin film transistor (TFT); The 4th thin film transistor (TFT), its grid is connected with the second clock signal output part, and its drain electrode is connected with the source electrode of the 3rd thin film transistor (TFT) and is connected to output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal;
Second control module is connected the rising that is used to receive first clock signal and slows down the threshold voltage of the grid of the 9th thin film transistor (TFT) respectively with first clock signal output terminal, first control module and the grid of the 9th thin film transistor (TFT); Described second control module comprises: the 5th thin film transistor (TFT), and its grid is connected with the grid of the 3rd thin film transistor (TFT), and its drain electrode connects its grid and is connected with first clock signal output terminal; The 7th thin film transistor (TFT), its grid is connected with the source electrode of the 5th thin film transistor (TFT), and its drain electrode is connected with the drain electrode of the 5th thin film transistor (TFT), and its source electrode is connected with the grid of the 9th thin film transistor (TFT);
The 3rd control module is connected with first control module, power supply negative terminal and the grid of the 9th thin film transistor (TFT) respectively, is used to keep the disarmed state of the 9th thin film transistor (TFT); Described the 3rd control module comprises: the 6th thin film transistor (TFT), and its grid is connected with output terminal at the corresponding levels, and its drain electrode is connected with the source electrode of the 5th thin film transistor (TFT), and its source electrode is connected with power supply negative terminal; The 8th thin film transistor (TFT), its grid is connected with output terminal at the corresponding levels, and its drain electrode is connected with grid with the 9th thin film transistor (TFT), and its source electrode is connected with power supply negative terminal;
The 4th control module, the output terminal with output terminal at the corresponding levels, next stage shift register is connected with power supply negative terminal respectively, is used to keep the no-output state of output terminal at the corresponding levels.
2. shift register according to claim 1 is characterized in that, described the 4th control module comprises:
The tenth thin film transistor (TFT), its grid is connected with the output terminal of next stage shift register, and its drain electrode is connected with the grid of the 11 thin film transistor (TFT), and its source electrode is connected with power supply negative terminal;
The 12 thin film transistor (TFT), its grid and the grid of the tenth thin film transistor (TFT) are connected and are connected to the output terminal of next stage shift register, and its drain electrode is connected with the source electrode of the 11 thin film transistor (TFT) and is connected to output terminal at the corresponding levels, and its source electrode is connected with power supply negative terminal.
3. gate drive apparatus that comprises claim 1 or 2 described shift registers, it is characterized in that, comprise displacement start signal output terminal, gate off voltage output terminal, first clock signal output terminal, second clock signal output part, first shift register and second shift register, wherein:
First shift register is connected with the gate off voltage output terminal with displacement start signal output terminal, first clock signal output terminal, second clock signal output part respectively, has first control signal output ends of output first control signal;
Second shift register, be connected with first control signal output ends, second clock signal output part, first clock signal output terminal and gate off voltage output terminal respectively, have second control signal output ends of output second control signal, described second control signal output ends is connected with first shift register.
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| CN200710122584XA CN101399086B (en) | 2007-09-27 | 2007-09-27 | Displacement register and grid drive device thereof |
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| CN200710122584XA CN101399086B (en) | 2007-09-27 | 2007-09-27 | Displacement register and grid drive device thereof |
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| CN101399086A CN101399086A (en) | 2009-04-01 |
| CN101399086B true CN101399086B (en) | 2010-09-15 |
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| CN101615431B (en) * | 2009-07-29 | 2012-06-27 | 友达光电股份有限公司 | Shift register |
| KR101992158B1 (en) * | 2013-04-30 | 2019-09-30 | 엘지디스플레이 주식회사 | Gate shift register and display device using the same |
| CN106486084B (en) * | 2017-01-04 | 2019-01-18 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and its driving method, display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1397956A (en) * | 2001-07-16 | 2003-02-19 | 株式会社半导体能源研究所 | Shift register and its driving method |
| CN101000417A (en) * | 2006-01-10 | 2007-07-18 | 三星电子株式会社 | Gate driver, and thin film transistor substrate and liquid crystal display having the same |
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| US7327169B2 (en) * | 2002-09-25 | 2008-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Clocked inverter, NAND, NOR and shift register |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1397956A (en) * | 2001-07-16 | 2003-02-19 | 株式会社半导体能源研究所 | Shift register and its driving method |
| CN101000417A (en) * | 2006-01-10 | 2007-07-18 | 三星电子株式会社 | Gate driver, and thin film transistor substrate and liquid crystal display having the same |
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