CN101388381B - Multi-chip stacking construction having metal spacer - Google Patents

Multi-chip stacking construction having metal spacer Download PDF

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CN101388381B
CN101388381B CN 200710145488 CN200710145488A CN101388381B CN 101388381 B CN101388381 B CN 101388381B CN 200710145488 CN200710145488 CN 200710145488 CN 200710145488 A CN200710145488 A CN 200710145488A CN 101388381 B CN101388381 B CN 101388381B
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metal
chip
plurality
pads
surface
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CN 200710145488
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CN101388381A (en )
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吴政庭
林鸿村
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南茂科技股份有限公司;百慕达南茂科技股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/4813Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83136Aligning involving guiding structures, e.g. spacers or supporting members
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

A package structure stacked with a plurality of chips comprises a base plate, a first chip and a second chip, wherein the base plate is provided with a plurality of metal contacts which are mutually connected, the first surface of the first chip is fixed on the base plate through an adhesion coating, and the second surface thereof is provided with a plurality of first metal bonding pads and a plurality of second metal bonding pads, and a plurality of metal protrusions are formed on the second metal bonding pads of the first chip. The first surface of the second chip is fixed with the metal protrusions through an adhesive coating, and a plurality of metal pads are arranged on the second surface thereof, and a plurality of metal wires are used to electrically connect the first metal bondingpads on the first chip and the first metal pads on the second chip with the metal contacts on the base plate, wherein the height of the metal protrusions is larger than the largest height of the bankof the metal wires.

Description

具有金属间隔物的多芯片堆叠结构 Multichip stack structure having a metal spacer

技术领域 FIELD

[0001] 本发明涉及集成电路的封装结构及其封装的方法,特别涉及一种在芯片上使用金属凸出物来作为多芯片堆叠结构中的支撑与散热的封装结构。 [0001] The present invention relates to a packaging structure and a method of packaging an integrated circuit, particularly relates to a metal projection on the chip package structure as a stacked structure in a multi-chip support and heat dissipation.

背景技术 Background technique

[0002] 近年来,半导体的后段制造工艺都在进行三维空间(Three Dimension ;3D)的封装,以期利用最少的面积来达到较高的密度或是存储器的容量等。 [0002] In recent years, the rear section of the semiconductor manufacturing process are performed three-dimensional space (Three Dimension; 3D) packaging, with a minimum area in order to achieve a high density memory capacity or the like. 为了能达到此目的,现阶段已发展出使用芯片堆叠(chip stacked)的方式来达成三维空间(Three Dimension ;3D) 的封装。 In order to achieve this object, the present stage has been developed using the chip stack embodiment (chip stacked) to achieve a three-dimensional space (Three Dimension; 3D) packaging.

[0003] 在公知技术中,例如第6333562号美国专利,即披露一种使用金属架350与树脂层340来形成多芯片堆叠的结构300,如图1所示。 [0003] In the prior art, for example U.S. Pat. No. 6,333,562, which discloses a 340 to 300, a multi-chip structure 1 is formed using a stacked layer of metal and a resin frame 350 shown in FIG. 很明显地,在图1的封装结构中,为避免下层芯片310的金属导线360与上层堆叠芯片320的背面接触,故将金属架350制造出并使用树脂层340所形成的高度差来保护下层芯片310的金属导线360。 Obviously, the package structure of Figure 1, to avoid the underlying metal wiring chip 310 360 in contact with the back surface of the upper stacked chips 320, so that the metal frame 350 manufactured using the difference in height of the resin layer 340 is formed to protect the underlying chip 310 metal wires 360. 然而,经过制造出的金属架350容易变形,造成后续芯片不易对准。 However, after the manufacture of the metal frame 350 is easily deformed, resulting in difficult alignment of subsequent chip. 另外,树脂层340涂布不均会使多芯片结构高低不平且松散,并且增加制造成本致使无法缩小封装体积。 Further, the resin layer 340 coating unevenness causes uneven and loose multi-chip structure, and makes it impossible to reduce the manufacturing cost is increased package size. 此外,由于金属导线360作了大幅度的弯折,因此每个芯片与金属焊垫320a,350a的粘着面积不足,容易在注膜过程中,造成芯片脱离。 Further, since the metal wires 360 made significant bending, thus each chip and the metal pad 320a, 350a is less than the area of ​​the adhesive, the film easily injection process, resulting from the chip.

[0004] 又如在公知技术中,例如第1255020号中国台湾专利专利中,即披露一种堆叠式多芯片封装100,如图2所示,其具有包括顶侧108与底侧的承载基座102,底部集成电路晶粒104,其具有附着至该承载基座的顶侧108的底面112,及相对的顶面114。 [0004] Another example is well-known in the art, e.g. China Taiwan Patent No. 1,255,020 patent, i.e., discloses a stacked multi-chip package 100, as shown, having a bottom side 108 of the carrier base comprises a top side 2 102, a bottom integrated circuit die 104 having a top side attached to the bottom surface 108 of the carrier base 112, top surface 114 and an opposite. 顶面114具有包括多个第一焊垫与中央区域的周边区域。 Top surface 114 having a first peripheral region comprises a plurality of pads and the central region. 在该周边区域与该中央区域间,珠粒124形成于底部晶粒104的顶面114上。 In the peripheral region and the central region between the beads 124 is formed on the top surface 114 of the bottom die 104. 该珠粒124可维持介于该底部晶粒104与顶部晶粒106间的预定空隙,以致在附着该顶部晶粒106至该底部晶粒104时,连接该底部晶粒104至该底部晶粒104时,连接该底部晶粒104至该承载基座102的第一导线122的丝焊点不会损坏。 When the beads 124 may be maintained between a predetermined gap between the bottom die 104 and top die 106, such that the attachment of the top to the bottom die 106 die 104, die 104 is connected to the bottom of the bottom die when 104, 104 connected to the bottom of the die to the carrier 122 of the first lead wire 102 of the base pad will not be damaged. 该珠粒124下并无提供焊垫的功能,使得整体晶粒面积无法加以缩小。 It does not provide the function of this pad bead 124, such that the overall particle area can not be reduced.

[0005] 上述的先前技术在实际使用时仍有不理想之处,因此尚具有改善的空间。 [0005] The prior art is still unsatisfactory place in actual use, and therefore still have room for improvement.

发明内容 SUMMARY

[0006] 有鉴于背景技术中所述的芯片堆叠方式的缺点及问题,本发明提供一种使用通过在焊垫上的金属凸出物取代树脂近似球状物(ball spacer)的结构,并将多个尺寸相近似的芯片堆叠成一种三维空间的多芯片堆叠封装结构。 [0006] In view of the chip stacking embodiment according to the background art problems and shortcomings, the present invention provides a substantially spherical object using a substituted resin (ball spacer) by protrusions in the metal structure of the bonding pad, and a plurality of approximating the size of the chip stack into a three-dimensional multi-chip stack package.

[0007] 本发明的主要目的在提供一种具有散热功能的多芯片堆叠封装结构,可增加产品的可靠度。 [0007] The main object of the present invention to provide a multi-chip stack package having a heat radiation function, can increase the reliability of the product.

[0008] 据此,本发明首先提供一种多芯片堆叠的封装结构,包括基板、第一芯片与第二芯片。 [0008] Accordingly, the present invention first provides a stacked multi-chip package structure includes a substrate, a first chip and second chip. 基板,其上表面及下表面上设置有多个相互连接的金属接点供金属导线连接使用。 A substrate provided with a plurality of metal interconnect metal contacts for connection wires upper and lower surfaces. 第一芯片的第一面通过第一粘着层固接于该基板的上表面,且该第一芯片第二面上设置有多个第一金属焊垫以及多个第二金属焊垫;第二芯片的第一面通过第二粘着层与该多个金属凸出物固接,而该第二芯片的第二面上设置有多个第一金属焊垫。 A first surface of the first chip through a first adhesive layer fixed to the upper surface of the substrate, and the chip is first provided with a first plurality of metal pads and a second plurality of metal pads on the second face; second the first surface of the chip by the adhesive layer and the plurality of second projections fixed to the metal, which is provided with a first plurality of metal pads on the second face of the second chip. 多个金属凸出物,形成于该第一芯片的该多个第二金属焊垫上;多条金属导线,用以将该第一芯片上的该多个第一金属焊垫以及该第二芯片上的该多个第一金属焊垫与该基板上表面的多个金属接点电连接。 A plurality of metal projections formed on the second plurality of metal pads of the first chip; a plurality of metal wires, to the first of the plurality of metal pads on the first chip and the second chip the first plurality of metal pads on the plurality of metal contact electrically connected to the upper surface of the substrate. 此封装体,用以包覆该第一芯片、该第二芯片及该基板的上表面,其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 This line package body for encapsulating the first chip, the second chip and the upper surface of the substrate, wherein the height of the plurality of metal projections is greater than the plurality of metal wires of the maximum height of the arc.

[0009] 本发明接着提供一种多芯片堆叠的封装结构,包括基板、第一芯片与第二芯片。 [0009] Next the present invention provides a stacked multi-chip package structure includes a substrate, a first chip and second chip. 基板,其上表面及下表面上设置有多个相互连接的金属接点供金属导线连接使用。 A substrate provided with a plurality of metal interconnect metal contacts for connection wires upper and lower surfaces. 第一芯片的第一面通过第一粘着层固接于该基板的上表面,且该第一芯片第二面上设置有多个第一金属焊垫以及多个第二金属焊垫;第二芯片的第一面通过第二粘着层与该多个金属凸出物固接,而该第二芯片的第二面上设置有多个第一金属焊垫。 A first surface of the first chip through a first adhesive layer fixed to the upper surface of the substrate, and the chip is first provided with a first plurality of metal pads and a second plurality of metal pads on the second face; second the first surface of the chip by the adhesive layer and the plurality of second projections fixed to the metal, which is provided with a first plurality of metal pads on the second face of the second chip. 多个金属凸出物,形成于该第一芯片的该多个第二金属焊垫上;多条金属导线,用以将该第一芯片上的该多个第一金属焊垫以及该第二芯片上的该多个第一金属焊垫与该基板上表面的多个金属接点电连接,并且至少一条第二金属导线,用以将该第一芯片上的该多个第二金属焊垫与该基板上表面的多个金属接点电连接。 A plurality of metal projections formed on the second plurality of metal pads of the first chip; a plurality of metal wires, to the first of the plurality of metal pads on the first chip and the second chip the first plurality of metal pads connected electrically to the plurality of metal contacts on the substrate surface, and at least one second metal wire for the second of the plurality of metal pads on the first chip a plurality of metal contact electrically connected to the surface of the substrate. 此封装体,用以包覆该第一芯片、该第二芯片及该基板的上表面,其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 This line package body for encapsulating the first chip, the second chip and the upper surface of the substrate, wherein the height of the plurality of metal projections is greater than the plurality of metal wires of the maximum height of the arc.

[0010] 本发明接着再提供一种多芯片堆叠的封装结构,包括导线架、第一芯片与第二芯片。 [0010] The present invention provides a multi followed by a chip stack package, the lead frame comprising, a first chip and second chip. 导线架,由多个成相对排列的内引脚以及芯片承座所组成,该芯片承座位于该多个相对排列的内引脚之间。 A lead frame die pad and inner lead into a plurality of oppositely disposed composed, between the inner pin of the chip to the plurality of supporting seats arranged opposite. 第一芯片的第一面通过第一粘着层固接于该基板的上表面,且该第一芯片的第二面上设置有多个第一金属焊垫以及多个第二金属焊垫。 A first surface of the first chip through a first adhesive layer fixed to the upper surface of the substrate, and the metal is provided with a plurality of first pads and a second plurality of metal pads on the second face of the first chip. 多个金属凸出物,形成于该第一芯片的该多个第二金属焊垫上。 A plurality of metal projections formed on the plurality of second metallic bonding pad of the first chip. 第二芯片的第一面通过第二粘着层与该多个金属凸出物固接,而该第二芯片的第二面上设置有多个第一金属焊垫。 A first surface of the second chip by a second adhesive metal layer and the plurality of projections fastened, which is provided with a first plurality of metal pads on the second face of the second chip. 多条金属导线,用以将该第一芯片上的该多个第一金属焊垫以及该第二芯片上的该多个第一金属焊垫与该导线架的多个成相对排列的内引脚电连接。 A plurality of metal wires to a plurality of the metal into the plurality of first pads and a first plurality of metal pads and the lead frame on the second chip to the first chip oppositely arranged inner leads pin electrical connection. 封装体,用以包覆该第一芯片、该第二芯片及该导线架,且其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 Line package body for encapsulating the first chip, the second chip and the lead frame, and wherein a height of the plurality of metal projections is greater than the plurality of metal wires of the maximum height of the arc.

[0011] 本发明继续提供一种多芯片堆叠的封装结构,包括导线架、第一芯片与第二芯片。 [0011] The present invention continued to provide a multi-chip stack package structure, comprising a lead frame, the first chip and the second chip. 导线架,由多个成相对排列的内引脚以及芯片承座所组成,该芯片承座位于该多个相对排列的内引脚之间,且该芯片承座具有上表面及相对于该上表面的下表面。 A lead frame die pad and inner lead into a plurality of oppositely disposed composed, between the inner pin of the chip to the plurality of bearing seats are arranged opposite, and the die pad having an upper surface and a relative to the upper surface of the lower surface. 第一多芯片堆叠结构及第二多芯片堆叠结构分别固接于该芯片承座的上表面及下表面。 A first stacked structure and the second multi-chip multichip stack structure are fixed to the die pad upper and lower surfaces. 多条金属导线,用以将该第一多芯片堆叠结构及该第二多芯片堆叠结构与该导线架的多个成相对排列的内引脚电连接。 A plurality of metal wires, to the first multi-chip stack structure and the inner pin of the second multi-stacked structure of the chip lead frame is arranged opposite to the plurality of connection. 封装体,用以包覆该第一多芯片堆叠结构、该第二多芯片堆叠结构及该导线架的多个内引脚,其中该第一多芯片堆叠结构及该第二多芯片堆叠结构,包括至少一个下层芯片、多个金属凸出物及上层芯片。 A package body encapsulating the first multi-chip stack structure, a plurality of the second multi-chip stack structure and the lead frame pins, wherein the first multi-chip structure and the second multi-stacked chip stack structure, a lower layer comprising at least one chip, a plurality of metal projections and the upper chip. 至少一个下层芯片,每一该下层芯片的主动面上设置有多个第一金属焊垫以及多个第二金属焊垫。 At least one lower die, the active surface of each chip is provided with a plurality of lower layer a first metal and a second plurality of metal pads pads. 多个金属凸出物,形成于该下层芯片的该多个第二金属焊垫上。 A plurality of metal projections formed on the metal bonding pad of the second plurality of lower layer chip. 上层芯片,该上层芯片的相对于主动面的背面通过第二粘着层与该多个金属凸出物固接,且其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 Upper chip, the chip with respect to the back surface of the upper active surface of the second adhesive layer by the plurality of metal wire loop secured to projections, and wherein the plurality of projections is greater than the height of the metal of the metal interconnects maximum height.

附图说明 BRIEF DESCRIPTION

[0012] 图1为公知多芯片堆叠封装的剖视图;[0013] [0012] FIG. 1 is a cross-sectional view of a known multi-chip stack package; [0013]

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[0044] [0044]

[0045] [0045]

图2为另一公知多芯片堆叠封装的剖视图; 图3A为依据本发明的第一芯片第一实施例的俯视图; 图3B为依据本发明的第一芯片的侧视图; 图4A为依据本发明的第一芯片第二实施例的俯视图; 图4B为依据本发明的第一芯片的侧视图; 图5为依据本发明的多芯片堆叠封装结构的剖视图; 图6为依据本发明的基板与第一芯片第一实施例粘合与打线后的俯视图图7为依据本发明的基板与第一芯片第二实施例粘合与打线后的俯视图图8为依据本发明的另一多芯片堆叠封装结构的剖视图; FIG 2 is a cross-sectional view of another known multi-chip stack package; FIG. 3A is a plan view of a chip according to the first embodiment of the present invention in a first embodiment; FIG. 3B is a side view of a first chip of the present invention; FIG. 4A is according to the invention a first chip plan view of a second embodiment; FIG. 4B is a side view of a first chip of the present invention; FIG. 5 is a cross-sectional view of the multi-chip stack package according to the present invention; FIG. 6 is a substrate of the invention according to the first a top view of the embodiment of FIG wire bonding a chip with a first embodiment of the present invention, the substrate 7 according to the first embodiment of the chip and the bonding wire of the second embodiment of FIG. 8 is a plan view according to another multi-chip stacked invention cross-sectional view of the package;

多芯片堆叠封装结构的剖视图; -多芯片堆叠封装结构的剖视图;以及-多芯片堆叠封装结构的剖视图。 The multi-chip stack package in a sectional view; - cross-sectional view of a stacked multi-chip package structure; and - a cross-sectional view of a stacked multi-chip package.

图9为依据本发明的再-图10为依据本发明的另图11为依据本发明的再主要元件标记说明100堆叠式多芯片封装104底部集成电路晶粒108承载基座的顶侧112底面120 中央区域124 珠粒200a第一芯片200c第三芯片210 主动面230第一粘着层250第二金属焊垫270第二粘着层32,34金属接点310下层芯片320a金属焊垫350金属架360金属导线600导线架620 芯片承座642第二金属导线 9 is further based on the present invention - FIG. 10 is a top side view of the invention according to another based on another main element 11 of the present invention Numerals 100 stacked multi-chip package 104 integrated circuit die 108 at the bottom 112 of the bottom surface of the carrier base a first chip 124 beads 200a 200c third die 210 active surface of the first adhesive layer 250 230 120 central region of the second metal pad 270 second adhesive layer 32, metal contact 310 metal pad 320a of the lower chip 350 metal frame 360 ​​metal 620 lead 600 lead frame die pad 642 of the second metal wire

102底侧106顶部晶粒110底侧114顶面122第一导线200 芯片200b第二芯片200d第四芯片220芯片的背面240第一金属焊垫252第三金属焊垫30 基板 The top surface of die 114 106 110 102 bottom side of the bottom side 122 of the first conductor chip 200 200b 240 200d of the first metal back of the second chip 220 of the fourth chip of the chip pads 252 of the third metal pad 30 of the substrate

300多芯片堆叠的结构320上层堆叠芯片340树脂层350a金属焊垫400金属凸出物610内引脚640第一金属导线70 封装体 300 320 chip stack structure an upper resin layer 340 stacked chips 350a metal pad 400 projecting metal pins 640 of the first metal wire 70 within the package body 610

具体实施方式 detailed description

[0046] 由于本发明所利用到的一些集成电路封装制造原理,已于先前技术中详细披露, 故在下述说明中,对于封装制造原理,不作完整描述。 [0046] As some integrated circuit package manufacturing principles of the present invention to use, has disclosed in detail in the prior art, so in the following description, package manufacturing principle, is not a complete description. 而且下述内文中的附图,也并未依据实际的相关尺寸完整绘制,其作用仅在表达与本发明特征有关的示意图。 And within the following drawings herein, also not according to the actual relative dimensions completely drawn, its role is only schematic and features of the present invention is related to expression.

[0047] 本发明在此所探讨的方向为一种三维空间的封装结构。 [0047] The present invention is discussed herein in the direction of the package structure of a three-dimensional space. 为了能彻底地了解本发明,将在下列的描述中提出详尽的封装结构设计。 In order to thoroughly understand the present invention, it will be set forth in the detailed design of the packaging structure in the following description. 显然地,本发明的施行并未限定芯片堆叠的方式的技术人员所熟习的特殊细节。 Obviously, the application of the present invention is not limited to the specific details of the chip stack art are familiar with the way. 另一方面,众所周知的芯片形成方式以及芯片薄化等后段制造工艺的详细步骤并未描述于细节中,以避免造成本发明不必要的限制。 On the other hand, the detailed steps known latter stage of the manufacturing process a thin chip and chip forming manner and so are not described in details to avoid unnecessary limits of the invention. 然而,对于本发明的较佳实施例,则会详细描述如下,然而除了这些详细描述之外,本发明还可以广泛地施行在其他的实施例中,且本发明的范围不受限定,其以权利要求为准。 However, for the preferred embodiment of the present invention will be described in detail below, however, in addition to the detailed description, the present invention can be widely implemented in other embodiments, and the scope of the present invention is not limited, to whichever claims.

[0048] 首先,请参照图3A、图3B,为本发明形成多芯片堆叠结构中的芯片的俯视图及侧视图。 [0048] First, referring to FIGS. 3A, 3B, the present invention forms a top view and a side view of a multi-chip stacked chip structure. 如图3A所示,芯片200的主动面210上已设置有多个第一金属焊垫240,同时在较接近芯片200中央区域的附近,再设置多个第二金属焊垫250,其中第二金属焊垫250的面积可以选择大于第一金属焊垫240的面积。 3A, the active surface 210 of chip 200 is provided with a first plurality of metal pads 240, 200 while in the vicinity of the chip closer to the central region, and then a second plurality of metal pads 250, wherein the second the area of ​​the metal pad 250 may be selected larger than the first area of ​​the metal pad 240. 此外,在芯片结构的另一实施例中,芯片200主动面210上设置有多个第一金属焊垫240,同时在较接近芯片200中央区域的附近,再设置多个第二金属焊垫250及多个第三金属焊垫252,其中第二金属焊垫250及第三金属焊垫252之间的距离非常小,例如:1〜20mil,如图4A所示。 Further, in another embodiment of the structure of the chip is provided with a first plurality of metal pads 240 on die 200 active surface 210, while in the vicinity of the chip closer to the central region 200, then a second plurality of metal pads 250 and a third plurality of metal pads 252, wherein the second metal pad 250, and a third distance between the metal pad 252 is very small, for example: 1~20mil, shown in Figure 4A. 在此要强调,第二金属焊垫250及第三金属焊垫252可以是在完成芯片的前段制造工艺后,再另外成长在芯片200的主动面上,如图3B所示。 To emphasize this, the second and third metal pad 250 may be a metal pad 252 after completion of the pre-stage of the chip manufacturing process, and then further grown in the active surface of the chip 200, shown in Figure 3B. 另外,第二金属焊垫250及第三金属焊垫252也可以是在芯片200完成前段制造工艺的过程中就已经设置在主动面上,如图4A及图4B所示。 Further, the second metal pad 250 and the third metal pad 252 may be completed in a manufacturing process preceding the process of the chip 200 has been provided on the active surface, as shown in FIG 4A and 4B. 对此,本发明并不加以限制,其均为本发明的实施方式。 In this regard, the present invention is not limited by which are embodiments of the present invention. 此外,在本实施例中,还可以在芯片200的相对于主动面210的背面220上,再选择性地加上粘着层230 (此粘着层也可作为一种绝缘层230)。 Further, in the present embodiment, the chip 200 may also be in phase with respect to the active surface on the back side 220 210, and then the adhesive layer 230 is selectively coupled (This adhesive layer can also be used as an insulating layer 230).

[0049] 接着,请参照图5,为本发明多芯片堆叠的具体实施例的剖视图。 [0049] Next, referring to FIG. 5, a cross-sectional view of a particular embodiment of the present invention, a multi-chip stack. 如图5所示, 多芯片堆叠结构由基板30、第一芯片(或称为下层芯片)200a、第二芯片(或称为上层芯片)200b与多条金属导线(640 ;642)所组成,其中基板30上设置有多个金属接点(32 ;34)。 As shown, a stacked structure of a multi-chip substrate 30, the first chip 5 (or lower chip) 200a, a second chip (or upper chip) 200b and a plurality of metal wires (640; 642) consisting of, wherein a plurality of metal contacts 30 on a substrate (32; 34).

[0050] 第一芯片200a通过粘着层230固接于基板30之上,且第一芯片200a的主动面上设置有多个第一金属焊垫240以及多个第二金属焊垫250,其中粘着层230可以预先贴附于基板30之上或是先将粘着层230贴附于第一芯片200a的背面上,本发明并不加以限制。 [0050] 200a of the first chip 230 via the adhesive layer 30 fixed on the substrate, and the active surface 200a of the first chip is provided with a first plurality of metal pads 240 and a second plurality of metal pads 250, wherein the adhesive layer 230 may be previously attached on the substrate 30 is attached or adhered to the first back surface 200a of the first chip, the present invention is not limited by the layer 230. 此外,本发明的粘着层230的目的在与基板30或是第一芯片200a形成接合,因此,只要是具有此功能的粘着材料,均为本发明的实施方式,例如:粘着胶带(tape)或B-Stage材料等;同时本发明的基板30的目的在于提供承载,因此,只要是具有此功能的材料,均为本发明的实施方式,例如:电路板或BGA电路板材料等。 Further, the object of the present invention, the adhesive layer 230 in the chip 30 or the first substrate 200a into engagement, so long as it is an adhesive material having this feature, embodiments of the present invention are, for example: adhesive tape (Tape) or B-Stage material; object 30 while the substrate of the present invention to provide a carrier, so long as it has this feature, embodiments of the present invention are, for example: a circuit board or a BGA circuit board material and the like.

[0051] 接着,在多个第二金属焊垫250上分别形成金属凸出物400,其中金属凸出物400 可以使用锡球(solder bump)堆叠而成,其也可以是使用打线制造工艺以金属凸块(stump bump)来形成,因此金属凸出物400也可以是一种金或铜材料,同时,金属凸出物400可以由多个锡球堆叠或是多个金属凸块堆叠所形成,本发明并不加以限制。 [0051] Next, a second plurality of metal pads 250 on the projections 400 are formed of metal, wherein the metal projections 400 may use solder balls (solder bump) stacking, which may be manufactured using a wire bonding process a metal bump (stump bump) formed, the metal projection 400 may be a gold or copper material, while the metal projections 400 may be formed by stacking a plurality of the plurality of solder balls or metal bumps are stacked form, the present invention is not limited thereto. 再接着,使用打线制造工艺以多条第二金属导线642将第一芯片200a上的第二金属焊垫250与基板30上的金属接点34连接;然后,再以另一打线制造工艺以多条第一金属导线640将芯片200a的第一金属焊垫240与基板30上的金属接点32连接。 Subsequently, using wire manufacturing process to a second plurality of metallic wires 642 of the second metal on the first die pad 200a connected to the metal contacts 25 034 on the substrate 30; Then, in another manufacturing process to wire a first plurality of metal wires 640 of the first metallic pad 200a, the chip 240 and the metal contacts on the substrate 30, 32 is connected.

[0052] 接着,进行芯片200b的堆叠,以第二粘着层270将第一芯片200a与第二芯片200b 固接。 [0052] Next, the stacked chip 200b, the second adhesive layer 270 to the first chip and the second chip 200a 200b fixed. 在堆叠过程中,可以将第二粘着层270形成于第一芯片200a的主动面上或是第二芯片200b的背面上,同时,此第二粘着层270可以是B-Stage材料,因此第二粘着层270也可以作为一种绝缘材料,对此,本发明也不加以限制。 During stacking, the second adhesive layer 270 may be formed on the back surface of the first die active surface 200a or 200b of the second chip, while this second adhesive layer 270 may be a B-Stage material, a second The adhesive layer 270 may be used as an insulating material, to which the present invention is not limited thereto. 此外,在第二芯片200b的背面上,也可以选择先选择性地贴附绝缘层230。 Further, on the back surface 200b of the second chip, you may be selected to be selectively attached to the insulating layer 230. 当第二芯片200b固接于第一芯片200a之上后,可以选择性地进行烘烤制造工艺,以固化第二粘着层270。 When the second chip 200b over the first fixed die 200a, may be selectively produced by baking process to cure the second adhesive layer 270. 然后,再以打线制造工艺以多条第一金属导线640将第二芯片200b的第一金属焊垫240与基板30上的金属接点32连接。 Then, to the wire manufacturing process to a first plurality of conductors 640 of the first metal of the second metal 200b of the chip pad 240 and the metal substrate 30 on the contact 32 engages. 最后, 再以封胶制造工艺将基板30、第一芯片200a、第二芯片200b与多条金属导线(640 ;642)包覆,以完成封装结构。 Finally, the manufacturing process of the sealant to the substrate 30, the first chip 200a, 200b and the second chip metal interconnects (640; 642) coated to complete the package.

[0053] 在此要强调的是,在本实施例中,第二金属焊垫250的面积比第一芯片200a上的第一金属焊垫240大,所以,除了可以在第二金属焊垫250上形成金属凸出物400外,还可以再提供第二金属导线642形成连接时所需的面积,如图6所示,其中,第二金属导线642 的线径可以比第一金属导线640粗,以便能作为第一芯片200a及第二芯片200b的散热导线。 [0053] It is emphasized that this, in the present embodiment, the second metal pad area 250 than the first metal on a first die pad 200a 240 large, so that, in addition to the second metal pad 250 projections 400 formed on the metal, but also may further provide a second metal wire 642 form the desired connection area, shown in Figure 6, wherein the second metal wire diameter 642 may be thicker than the first metal wire 640 in order to heat the wire as the first chip and the second chip 200a 200b.

[0054] 此外,若第二金属焊垫250的面积只能形成金属凸出物400时,也可以选择在第二金属焊垫250的旁边再形成一个第三金属焊垫252,其中第二金属焊垫250及第三金属焊垫252之间的距离非常小,例如:1〜20mil,如图7所示。 [0054] Further, when the bonding area of ​​the second metal pad 250 can be formed of metal projections 400, 250 may be selected in the next second metal pad is further formed a third metal pad 252, wherein the second metal pad 250, and a third distance between the metal pad 252 is very small, for example: 1~20mil, as shown in FIG. 由于第二金属焊垫250及第三金属焊垫252非常接近,因此当第三金属焊垫252以另一条金属导线642与基板30上的金属接点34连接后,也可以作为芯片间的散热导线。 Since the second metal pad 250 and the third metal pad 252 is very close, so when the third metal pad 252 to the other metal contacts on the metal wire 642 connected to the substrate 3034, the heat can also be used as a wire between the chips . 在此要强调的,基板30上的金属接点32及金属接点34,可以如图6及图7所示的分成两列;但也可以是一列的排列,对此本发明并不加以限制。 It is emphasized here, the metal contact 32 on the substrate 30 and metal contact 34 may be divided into two as shown in FIG. 6 and FIG. 7; it may be arranged in a row, to which the present invention is not limited thereto. 同时,基板30上的金属接点32及金属接点34间的面积大小可以相同,但也可以选择将金属接点34做的大一些,以使较粗的第二金属导线642能够有效地连接,以便能作为第一芯片200a及第二芯片200b的散热导线。 Meanwhile, the metal contact 32 on the substrate 30 and metal contact 34 may be the same size of the area, it is also possible to select metal contacts 34 made larger, so that the thick second metal wire 642 can be operatively connected, so as to as the first heat dissipating wires 200a and the chip 200b of the second chip.

[0055] 接着,请再参照图8,为本发明的多芯片堆叠结构的另一具体实施例的剖视图。 [0055] Next, Referring again to FIG. 8, a cross-sectional view of another configuration of a multi-chip stacked specific embodiment of the present invention. 本实施例仅在图5的实施例中,在第二芯片200b上再多堆叠另一芯片200c。 In the present embodiment, only the embodiment of FIG. 5, in the second chip 200b more stacked another chip 200c. 此时,第二芯片200b之上就必须设置有第二金属焊垫250或是第三金属焊垫252,并且在第二金属焊垫250 上形成金属凸出物400以及第二金属导线642。 At this time, on the second chip 200b must be provided with the second metal pad 250 or pad 252 of the third metal, and forming a metal protrusion 400 and a second metal wire 642 on the second metal pad 250. 很明显地,在本发明的实施例中,凡在下层的芯片均需设置成与图5中第一芯片200a相同的结构,故在图8中的第一芯片200a及第二芯片200b则必须与图5中第一芯片200a有相同的结构。 Obviously, in the embodiment of the present invention, where the lower layer is required in the chip set to the same configuration as the first chip 200a in FIG. 5, so that the first chip 200a in FIG. 8 and the second chip 200b must and FIG. 5 of the first chip 200a has the same structure. 由于第三芯片200c与第二芯片200b间也是由第二粘着层270来固接,其余连接过程均与图5的连接过程相同,因此详细的过程在此不再赘述。 Since the third chip 200c and the second inter-chip 200b by a second adhesive layer 270 is affixed to, the rest are the same as the connection process the connection process of Figure 5, detailed process is not repeated herein.

[0056] 请继续参照图9,为本发明的多芯片堆叠封装结构的再一实施例的剖视图。 [0056] Please continue to refer to FIG. 9, and then the multi-chip stack package of the present invention is a cross-sectional view of an embodiment. 很明显地,图9与图5之间的差异在于基板30的结构置换成导线架600,而导线架600是由多个成相对排列的内引脚610以及芯片承座620所组成,其中芯片承座620位于多个相对排列的内引脚610之间。 Obviously, the difference between FIG. 9 and FIG. 5 in that the structure of the substrate 30 is replaced with the lead frame 600, and the lead frame 600 is arranged opposite the plurality of inner leads 610 and die pad 620, where the chip seat 620 is positioned between the plurality of inner pins 610 arranged opposite. 第一芯片200a通过粘着层230固接于芯片承座620之上,且第一芯片200a的主动面上设置有多个第一金属焊垫240以及多个第二金属焊垫250,其中粘着层230 可以预先贴附于芯片承座620之上或是先将粘着层230贴附于第一芯片200a的背面上, 本发明并不加以限制。 The first chip 200a disposed through a first chip 230 fixed to the adhesive layer on the die pad 620, and the active surface 200a of the first plurality of metal pads 240 and a second plurality of metal pads 250, wherein the adhesive layer 230 may be pre-attached to or on the die pad 620 is attached to the first adhesive layer 230 on the rear surface 200a of the first chip, the present invention is not limited thereto. 接着,在多个第二金属焊垫250上分别形成金属凸出物400,其中金属凸出物400可以使用锡球(solder bump)堆叠而成,其也可以是使用打线制造工艺以金属凸块(stump bump)来形成其中,金属凸出物400可以由多个金属凸块堆叠所形成。 Subsequently, in a second plurality of metal pads 400 are formed of metal on the projections 250, which projections 400 may use the metal solder ball (solder bump) stacking, which may be used in a manufacturing process of the metal wire projecting block (stump bump) formed wherein the metal projections 400 may be formed by stacking a plurality of metal bumps is formed. 再接着,使用打线制造工艺以多条第二金属导线642将第一芯片200a上的第二金属焊垫250与内引脚610连接;然后,再以另一打线制造工艺以多条第一金属导线640将第一芯片200a 的第一金属焊垫240与内引脚610连接。 Subsequently, using wire manufacturing process to a second plurality of metal wires 642 on the second metal 200a of the first die pads 250 and the inner lead 610 is connected; Then, in another manufacturing process of a multi-wire article a metal wire 640 of the first metal pad 200a of the first chip 240 and the inner lead 610 is connected. 接着,将第二芯片200b堆叠于第一芯片200a之上。 Next, the second chip stacked on the first chip 200b 200a. 由于第二芯片200b的堆叠过程,与图5的实施例相同,故其详细过程不再赘述,最后,再使用封胶制造工艺以封胶材料700将导线架600中的内引脚610、芯片承座620、第一芯片200a、第二芯片200b与多条金属导线(640 ;642)包覆,以完成封装结构。 Since the second chip 200b of the stacking process, the embodiment of Figure 5 is the same, so the process will not be repeated in detail, and finally, reused at the manufacturing process sealant sealant material 700 to the inner leads 610 of the lead frame 600, the chip seat 620, a first chip 200a, 200b and the second chip metal interconnects (640; 642) coated to complete the package.

[0057] 在此要强调的是,在本实施例中,同样地,第二金属焊垫250的面积比第一芯片200a上的金属焊垫240大,所以,除了可以在第二金属焊垫250上形成金属凸出物400夕卜, 还可以再提供第二金属导线642形成连接时所需的面积,如图6所示,其中,第二金属导线642的线径可以比第一金属导线640粗,以便能作为第一芯片200a及第二芯片200b的散热导线。 [0057] It is emphasized that this, in the present embodiment, in the same manner, a second metal pad 250 on the area ratio of the metal pad 200a of the first die 240 large, so that, in addition to the second metal pad metal projections 400 formed on the Xi Bu 250, can then provide a second metal wire 642 is formed to connect the desired area, as shown in FIG 6, wherein the second metal wire diameter than the first wire 642 may be metal 640 thick, as the first chip in order to heat the wires 200a and 200b of the second chip. 此外,若第二金属焊垫250的面积只能形成凸出物400时,也可以选择在第二金属焊垫250的旁边再形成一个第三金属焊垫252,其中第二金属焊垫250及第三金属焊垫252 之间的距离非常小,例如:1〜20mil,如图7所示。 Further, if the second area of ​​the metal pad 250 can be formed when the projections 400, 250 may be selected in the next second metal pad is further formed a third metal pad 252, where metal pads 250 and the second between the third metal pad 252 is very small distance, for example: 1~20mil, as shown in FIG. 由于第二金属焊垫250及第三金属焊垫252非常接近,因此当第三金属焊垫252以另一条金属导线642与基板30上的金属接点34 连接后,也可以作为第一芯片200a及第二芯片200b间的散热导线。 Since the second metal pad 250 and the third metal pad 252 is very close, so when the third metal pad 252 to the other metal contacts on the substrate 30 and the metal wire 34 is connected 642, the chip may be used as the first and 200a the second heat conductor between chip 200b.

[0058] 接着,请继续参照图10,为依据本发明的另一多芯片堆叠封装结构的剖视图。 [0058] Next, please continue to refer to FIG. 10, it is a cross-sectional view of another configuration of a multi-chip stack package according to the present invention. 很明显地,图10与图9的差异在于导线架600中的芯片承座620与内引脚610之间形成高度差,而在第一芯片200a及第二芯片200b在导线架600上的堆叠过程以及封胶过程,则均与图9相同,故详细过程不再赘述。 Obviously, the difference in FIG. 9 and FIG. 10 is to form a height difference between the chip seat 620 and the pin 600 of the lead frame 610, and stacked on the first chip 200a and 200b on the second chip 600 of the lead frame sealant and process procedure, are the same as in FIG. 9, and therefore the process will not be repeated in detail.

[0059] 接着,请继续参照图11,为在导线架600上形成多芯片堆叠封装结构的剖视图,其中导线架600由多个成相对排列的内引脚610以及芯片承座620所组成,而芯片承座620 位于多个相对排列的内引脚610之间。 [0059] Next, proceed to 11, is a cross-sectional view of a multi-chip stack package 600 is formed on the lead frame, wherein a plurality of lead frame 600 opposite the pin 610 arranged in a seat 620 and a chip composed, and die pad 620 is positioned between the plurality of inner pins 610 arranged opposite. 如图11所示,将第一芯片200a、第二芯片200b所形成的第一多芯片堆叠结构以及第三芯片200c、第四芯片200d所形成的第二多芯片堆叠结构分别固接于芯片承座620的上表面及下表面,其中位于下层的第一芯片200a以及第二芯片200c的主动面上设置有多个第一金属焊垫240以及多个第二金属焊垫250。 11, the first chip 200a, 200b of the first multi-chip second chip stack structure is formed and a third chip 200c, a second multi-chip stack structure formed by the fourth chip 200d are respectively fixed to the chip support upper and lower surfaces of the base 620, wherein a first chip located on the lower surface 200a and a second active chip 200c is provided with a first plurality of metal pads 240 and a second plurality of metal pads 250. 如前所述, 由第一芯片200a、第二芯片200b所形成的第一多芯片堆叠结构以及第三芯片200c、第四芯片200d所形成的第二多芯片堆叠结构与图9及图10中的芯片堆叠结构完全相同,故其详细的芯片堆叠过程、第一芯片200a、第二芯片200b、第三芯片200c及第四芯片200d与第一金属导线640、第二金属导线642的连接过程不再赘述。 As described above, the first multi-chip stack structure and a third chip 200c from the first chip 200a, 200b formed in the second chip, the second chip stacked structure of a multi-fourth chip 200d in FIG. 9 and FIG formed 10 the chip stacking structure is identical, so the detailed chip stacking process, a first chip 200a, a second chip 200b, 200c and the third chip to the fourth chip 200d first metal wire 640, a second metal wire 642 is not connected to the process then repeat.

[0060] 要强调的是,在本实施例中的第一多芯片堆叠结构及第二多芯片堆叠结构,其下层的第一芯片200a及第三芯片200c的主动面上的多个第二金属焊垫250可进一步设置多个金属凸出物400,用以接触及支撑上层的第二芯片200b及第四芯片200d。 [0060] It is emphasized that the first and second multi-chip multi-chip stacked structure stacked structure in the present embodiment, a plurality of the active surface of the first chip and the third lower layer 200a of a second metal chip 200c pad 250 may be further provided a plurality of metal protrusions 400 for contacting and supporting the second upper die 200b and the fourth chip 200d.

[0061] 显然地,依照上面实施例中的描述,本发明可能有许多的修正与差异。 [0061] Clearly, in the embodiment in accordance with the embodiment described above, the present invention may have many differences and correction. 因此需要在其附加的权利要求项的范围内加以理解,除了上述详细的描述外,本发明还可以广泛地在其他的实施例中施行。 Therefore needs to be understood in terms of its appended claims, in addition to the foregoing detailed description, the present invention can be widely implemented in other embodiments. 上述仅为本发明的较佳实施例而已,并非用以限定本发明的权利要求;例如,本发明不限于具有两个堆叠式晶粒的封装,而是可以应用至多个堆叠式晶粒的封装,即本发明可应用于所有导线焊接的封装型式。 The above-described embodiments are merely exemplary embodiments of the present invention only, not intended to limit the claims of the present invention; for example, the present invention is not limited to having two stacked die package, but may be applied to the plurality of stacked die package , i.e., the present invention is applicable to all types of wire bonding packaging. 此外,晶粒大小与步骤中的尺寸可加以变化以符合封装设计的要求。 Further, the grain size of the step size of the package may be varied to meet the design requirements. 因此,应了解本发明不限于特定具体实施例,凡其它未脱离本发明所揭示的精神下所完成的等效变更或改进,均应包含在权利要求中。 Thus, it should be understood that the invention is not limited to the particular embodiment, any other equivalent alterations or modifications without departing from the spirit of the invention disclosed completed, it should be included in the appended claims.

Claims (9)

  1. 一种多芯片堆叠的封装结构,包括:基板,其上表面及下表面上设置有多个相互连接的金属接点;第一芯片,该第一芯片的第一面通过第一粘着层固接于该基板的上表面,且该第一芯片的第二面上设置有多个第一金属焊垫以及多个第二金属焊垫;多个金属凸出物,形成于该第一芯片的该多个第二金属焊垫上;第二芯片,该第二芯片的第一面通过第二粘着层与该多个金属凸出物固接,而该第二芯片的第二面上设置有多个第一金属焊垫;多条第一金属导线,用以将该第一芯片上的该多个第一金属焊垫及该多个第二金属焊垫以及该第二芯片上的该多个第一金属焊垫与该基板上表面的多个金属接点电连接;至少一条第二金属导线,用以将该第一芯片上的该多个第二金属焊垫与该基板上表面的多个金属接点电连接,其中,上述第二金属导线线径较第一金属导 A multi-chip package stacked structure, comprising: a substrate, which metal contacts are connected to each other is provided with a plurality of upper and lower surfaces; a first chip, the first chip through a first face fixed to the first adhesive layer upper surface of the substrate, and the second surface of the first chip is provided with a first plurality of metal pads and a plurality of second metal pad; a plurality of metal projections formed on the plurality of the first chip a second metallic bonding pad; a second chip, a first surface of the second adhesive layer and the plurality of the plurality of metal projections fastened, and the second face of the second chip are disposed through the second chip a metal pad; a first plurality of metal wires to the plurality of first metal on the pads and said second plurality of metal pads on the second chip and the first chip of the first plurality metal pad electrically connected to the plurality of metal contacts on the substrate surface; and at least one second metal wire for the second of the plurality of metal pads and a plurality of metal contacts on the substrate surface on a first chip electrically connecting the second metal wire diameter than the first metal guide 为粗;以及封装体,用以包覆该第一芯片、该第二芯片及该基板的上表面;其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 Crude; and a package body for encapsulating the first chip, the second chip and the upper surface of the substrate; wherein the height of the line of the plurality of metal projections is greater than the plurality of metal wires of the maximum height of the arc.
  2. 2.根据权利要求1所述的封装结构,其特征是该基板可为BGA的电路板。 2. The package structure according to claim 1, characterized in that the BGA substrate may be a circuit board.
  3. 3.根据权利要求1所述的封装结构,其特征是该第一芯片的该第二面上的每一个第一金属焊垫的面积均小于每一个第二金属焊垫的面积。 3. The package structure according to claim 1, characterized in that the metal of the second face of each of the first pad of the first chip area is less than a second area of ​​each metal pad.
  4. 4.根据权利要求1所述的封装结构,其特征是每一该金属凸出物可以由多个锡球堆叠所形成。 4. The package structure according to claim 1, wherein each of the metallic projections may be formed of a plurality of solder balls are stacked.
  5. 5.根据权利要求1所述的封装结构,其特征是每一该金属凸出物可以由多个金属凸块堆叠所形成。 5. The package structure according to claim 1, wherein each of the metallic projections may be formed by stacking a plurality of metal bumps is formed.
  6. 6. 一种多芯片堆叠的封装结构,包括:导线架,由多个成相对排列的内引脚以及芯片承座所组成,该芯片承座位于该多个相对排列的内引脚之间;第一芯片,该第一芯片的第一面通过第一粘着层固接于该芯片承座的上表面,且该第一芯片的第二面上设置有多个第一金属焊垫以及多个第二金属焊垫; 多个金属凸出物,形成于该第一芯片的该多个第二金属焊垫上; 第二芯片,该第二芯片的第一面通过第二粘着层与该多个金属凸出物固接,而该第二芯片的第二面上设置有多个第一金属焊垫;多条金属导线,用以将该第一芯片上的该多个第一金属焊垫及该多个第二金属焊垫以及该第二芯片上的该多个第一金属焊垫与该导线架的多个成相对排列的内引脚电连接,其中上述多条金属导线中用以将该下层芯片上该多个第二金属焊垫与该导线架的多个成相对排列 A stacked multi-chip package, comprising: a lead frame into a plurality of oppositely arranged inner leads and the die pad is composed, between the inner pin of the chip to the plurality of opposing bearing seats arranged; a first chip, a first surface of the first adhesive layer fixed to the upper surface of the die pad of the first chip, the first chip and a second surface provided with a plurality of first pads and a plurality of metal a second metal pad; a plurality of metal projections formed on the second plurality of metal pads of the first chip; a second chip, the second chip to the first surface of the adhesive layer by a second plurality metal projections fastened, which is provided with a first plurality of metal pads on the second face of the second chip; a plurality of metal wires, to the first of the plurality of metal pads on the first chip and the second plurality of metal pads on the second chip and the first plurality of metal pads and the lead frame into a plurality of oppositely arranged inner leads electrically connected, wherein the plurality of metal wires for the on the lower die of the second plurality of metal pads and the lead frame are arranged into a plurality of relatively 内引脚电连接之金属导线线径较粗;以及封装体,用以包覆该第一芯片、该第二芯片及该导线架;其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 Thick metal wire diameter of the inner leads are electrically connected; and an encapsulation member for encapsulating the first chip, the second chip and the lead frame; wherein the plurality of projections is greater than the height of the metal of the plurality of metal the maximum height of the arc line conductor.
  7. 7. —种多芯片堆叠的封装结构,包括:导线架,由多个成相对排列的内引脚以及芯片承座所组成,该芯片承座位于该多个相对排列的内引脚之间,且该芯片承座具有上表面及相对于该上表面的下表面;第一多芯片堆叠结构及第二多芯片堆叠结构分别固接于该芯片承座的上表面及下表多条金属导线,用以将该第一多芯片堆叠结构及该第二多芯片堆叠结构与该导线架的多个成相对排列的内引脚电连接;以及封装体,用以包覆该第一多芯片堆叠结构、该第二多芯片堆叠结构及该导线架的多个内引脚;其中该第一多芯片堆叠结构及该第二多芯片堆叠结构,包括: 至少一个下层芯片,每一该下层芯片的有源面上设置有多个第一金属焊垫以及多个第二金属焊垫;多个金属凸出物,形成于该下层芯片的该多个第二金属焊垫上; 上层芯片,该上层芯片的相对于有 7. - Species stacked multi-chip package, comprising: between the lead frame into a plurality of inner leads and the die pad composed of oppositely arranged, the chip bearing seat arranged opposite to the plurality of inner leads, and the die pad having an upper surface and a lower surface with respect to the upper surface; a first stacked structure and the second multi-chip multichip stack structure are fixed to the upper surface of the die pad and a plurality of metal wires in the table, the first inner lead for electrically multichip stack structure and the second multi-stacked structure of a plurality of chip into the lead frame is arranged opposite; and a package body for encapsulating the multi-chip first stacked structure , a plurality of the second multi-chip stack structure and the lead frame pin; wherein the plurality of the first structure and the second chip stacked multi-chip stack structure, comprising: at least one lower die, each of the lower chip are source metal surface provided with a plurality of first pads and a second plurality of metal pads; a plurality of metal projections formed on the lower layer of the plurality of second metal pads of the chip; upper chip, the chip upper layer there is relative 面的背面通过第二粘着层与该多个金属凸出物固接;及多条金属导线,用以将该下层芯片上的该多个第一金属焊垫及该多个第二金属焊垫以及该上层芯片上的该多个第一金属焊垫与该导线架的多个成相对排列的内引脚电连接;且上述多条金属导线中用以将该下层芯片上该多个第二金属焊垫与该导线架的多个成相对排列的内引脚电连接之金属导线线径较粗;其中该多个金属凸出物的高度大于该多条金属导线的线弧最大高度。 The back surface of the second adhesive layer through the plurality of metal protrusions fixed; and a plurality of metal wires to the metal pads of the first plurality and said second plurality of metal pads on the lower chip and an inner pin of the first plurality of metal pads and the lead frame into a plurality of oppositely arranged on the upper chip is connected; and said plurality of metallic wires on the lower chip to the plurality of second metal pad thick metal wire diameter of the inner lead electrically connected to the lead frame with a plurality of oppositely arranged; wherein the height of the plurality of metal projections is greater than the plurality of metal wiring lines maximum height of the arc.
  8. 8.根据权利要求6或7所述的封装结构,其特征是每一该金属凸出物可以由多个锡球堆叠所形成。 8.6 packaging structure according to claim 7, wherein each of the metallic projections may be formed of a plurality of solder balls are stacked.
  9. 9.根据权利要求6或7所述的封装结构,其特征是每一该金属凸出物可以由多个金属凸块堆叠所形成。 9.6 packaging structure according to claim 7, wherein each of the metallic projections may be formed by stacking a plurality of metal bumps is formed.
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CN1561545A (en) 2001-09-28 2005-01-05 摩托罗拉公司 Semiconductor with multiple rows of bond pads

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US6593662B1 (en) 2000-06-16 2003-07-15 Siliconware Precision Industries Co., Ltd. Stacked-die package structure
US6706557B2 (en) 2001-09-21 2004-03-16 Micron Technology, Inc. Method of fabricating stacked die configurations utilizing redistribution bond pads
CN1561545A (en) 2001-09-28 2005-01-05 摩托罗拉公司 Semiconductor with multiple rows of bond pads

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