CN101378075B - LDMOS, and semicondutor device integrating with LDMOS and CMOS - Google Patents

LDMOS, and semicondutor device integrating with LDMOS and CMOS Download PDF

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CN101378075B
CN101378075B CN2007101488347A CN200710148834A CN101378075B CN 101378075 B CN101378075 B CN 101378075B CN 2007101488347 A CN2007101488347 A CN 2007101488347A CN 200710148834 A CN200710148834 A CN 200710148834A CN 101378075 B CN101378075 B CN 101378075B
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CN101378075A (en
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谭健
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Suzhou Saixin Electronic Technology Co ltd
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Abstract

The invention provides an LDMOS and a semiconductor device integrating the LDMOS and a CMOS. And the semiconductor device comprises the CMOS and the LDMOS arranged on a semiconductor substrate. The invention is characterized in that the LDMOS comprises a channel on the surface of the substrate, a grid on the channel, a source/drain electrode, which comprises a lightly doped region beside and close to the channel and a heavily doped region next to the lightly doped region, a counter-doping well which has the doping type opposite to that of the source/drain electrode and is below the groove, completely containing the groove, and a counter-doping region which has the doping type opposite to that of the source/drain electrode and is between the heavily doped region of the source/drain electrode and the counter-doping well. The LDMOS makes full use of the art of the CMOS already available, greatly reduces the number of layers of masks, and has the advantages of fast switching speed, small on resistance, low parasitic capacitance and low cost, and the like.

Description

The semiconductor device of LDMOS and integrating with LDMOS and CMOS
Technical field
The present invention relates to the semiconductor device of LDMOS and integrating with LDMOS and CMOS.Be horizontal proliferation type metal oxide semiconductor transistor (LDMOS) and integrated with CMOS technology thereof specifically.
Background technology
CMOS transistor (CMOS, Complementary Metal Oxide Semiconductor) device is widely used in microelectronic.Be generally used for logical device, memory etc.Except that CMOS, horizontal proliferation type metal oxide semiconductor transistor (LDMOS, Laterally Diffused Metal Oxide Semiconductor) also is widely used in the microelectronics industry field.LDMOS is generally used for the power management in the microelectronic.Power management is meant that some combination of circuits are used to control the conversion of electric energy and are transported to corresponding load.This load can be any chip, system or subsystem, like microprocessor chip, floating point processor, optics, microelectromechanical-systems etc.
CMOS technology is under the promotion of digital technology, and the minimum gate polar curve is wide to become more and more littler, and oxidated layer thickness is also corresponding more and more thinner, does like this to make that the CMOS integrated level is increasingly high on the unit are, makes that also corresponding C MOS speed is more and more faster simultaneously.LDMOS adopts relative CMOS to fall behind the technology of several generations usually because puncture voltage is higher than CMOS far away usually.And oxidated layer thickness also is different from the CMOS technology of standard.There was a kind of trend that CMOS and LDMOS are integrated on the same block semiconductor substrate in recent years.Because CMOS and LDMOS have different processes separately, be integrated together them and be not easy.Usually CMOS that is integrated together and LDMOS have different oxidation layer thickness separately, and different minimum feature is also arranged.And wide big several times than CMOS of the minimum gate polar curve of LDMOS often.
The technology that some LDMOS and CMOS have identical oxidated layer thickness has appearred recently, but normally integrated with some older CMOS technologies, as 0.5 micron even older.And however, the minimum gate polar curve of LDMOS is wide or bigger several times than CMOS.Wide when bigger when LDMOS minimum gate polar curve than CMOS, explain that this LDMOS does not utilize advanced CMOS technology to optimize the index of LDMOS fully.And just accomplished the simple merging of one two cover technology.Such LDMOS drives the energy of palpus labor, and the speed that conducting is closed is also very slow, thereby switching frequency is very low, like 300 kilo hertzs of tastes.And because the raceway groove of LDMOS is long; Channel resistance is also big; Adding many design rules is old threads; The area that makes LDMOS account for is very big, because much more many technology mask number after integrated is than the mask number of independent LDMOS with CMOS, the LDMOS cost after integrated is often than independently non-integrated LDMOS device is high.
Summary of the invention
The objective of the invention is to, a kind of new LDMOS and the semiconductor device of integrating with LDMOS and CMOS are provided.This device can make full use of the advanced technologies of CMOS and optimize the LDMOS index.
The present invention provides a kind of LDMOS; Comprise semi-conductive substrate; One is positioned at the raceway groove of this substrate surface; And be positioned at the grid on this raceway groove, it is characterized in that also comprising: a source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section; The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully; One with counter dopant regions that said source/the drain electrode doping type is opposite, this counter dopant regions is between the heavily doped region and said counter-doping trap of said source/drain electrode.
The present invention also provides another kind of LDMOS; Comprise semi-conductive substrate; One is positioned at the raceway groove of this substrate surface; And be positioned at the grid on this raceway groove, it is characterized in that also comprising: a source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section; The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully; One another doped region identical with said source/drain electrode doping type, this another doped region surrounds heavily doped region and the light doping section and the said counter-doping trap of said source/drain electrode.
The present invention also provides the semiconductor device of a kind of integrating with LDMOS and CMOS; Comprise and be located at a CMOS and a LDMOS on the semi-conductive substrate; Said CMOS comprises a NMOS and a PMOS, and said LDMOS comprises a N-LDMOS and a P-LDMOS, and it is characterized in that said N-LDMOS and said P-LDMOS comprise respectively: one is positioned at the raceway groove of this substrate surface; Be positioned at the grid on this raceway groove
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section;
The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully;
One with counter dopant regions that said source/the drain electrode doping type is opposite, this counter dopant regions is between the heavily doped region and said counter-doping trap of said source/drain electrode.
The present invention also provides the semiconductor device of a kind of integrating with LDMOS and CMOS; Comprise and be located at a CMOS and a LDMOS on the semi-conductive substrate; Said CMOS comprises a NMOS and a PMOS, and said LDMOS comprises a N-LDMOS and a P-LDMOS, and it is characterized in that said N-LDMOS and said P-LDMOS comprise respectively: one is positioned at the raceway groove of this substrate surface; Be positioned at the grid on this raceway groove
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section;
The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully;
One another doped region identical with said source/drain electrode doping type, this another doped region surrounds heavily doped region and the said light doping section and the said counter-doping trap of said source/drain electrode.
How that this LDMOS is integrated with CMOS technology the present invention has also described simultaneously.Can find out that from technological process this LDMOS makes full use of the existing technology of CMOS (BiCMOS), simplifies the mask number of plies greatly.
It is fast that LDMOS provided by the invention has switching speed, and conducting resistance is little, and parasitic capacitance is low, low cost and other advantages.
Description of drawings
Fig. 1 is the semiconductor device main technique flow process profile of processing semiconductor LDMOS of the present invention and integrating with LDMOS and CMOS to Figure 13;
Figure 14 is the P-LDMOS and the N-LDMOS of monolateral high pressure to Figure 17;
Figure 18 can both bear the symmetrical device structural representation of high pressure for device shown in Figure 14 becomes source electrode with draining.
Embodiment
Embodiment one
Shown in a kind of LDMOS such as Figure 14, Figure 15; Comprise a P-LDMOS and a N-LDMOS; Be positioned at jointly on the semi-conductive substrate 211, said P-LDMOS and N-LDMOS comprise that separately one is positioned at the raceway groove on these substrate 211 surfaces, and are positioned at the grid 270 on this raceway groove; One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region 266,267 that the other and light doping section 256,257 and that be close to this raceway groove of said raceway groove is close to this light doping section 256,257; The one counter-doping trap 241,242 opposite with said source/drain electrode doping type, this counter-doping trap 241,242 are positioned at this raceway groove below and comprise this raceway groove fully; One counter dopant regions 235,236 opposite with said source/drain electrode doping type, this counter dopant regions 235,236 is at the heavily doped region 266,267 of said source/drain electrode and said counter-doping trap 241, between 242.
Figure 14 illustrates said LDMOS and on P type epitaxial loayer, realizes.On said substrate 211, also be provided with a P type epitaxial loayer 222; The raceway groove of P-LDMOS and N-LDMOS is positioned at this epitaxial loayer 222 surfaces; Source/drain electrode of said N-LDMOS is N type light doping section 257 and N type heavily doped region 267; The counter-doping trap 242 of said N-LDMOS is P type traps, and the counter dopant regions 236 of said N-LDMOS forms by P type doped region or by P type epitaxial loayer 222, and its doping content is lower than said counter-doping trap 242.Source/drain electrode of said P-LDMOS is P type light doping section 256 and P type heavily doped region 266; The counter-doping trap 241 of said P-LDMOS is N type traps; The counter dopant regions 235 of said P-LDMOS is by N type doped region, and its doping content is lower than said counter-doping trap 241.
Like Figure 14, when epitaxial loayer was the P type, said P-LDMOS isolated through N type counter dopant regions 235 and other components and parts on the homepitaxy layer 222, and N-LDMOS both can be non-isolation, also can isolate.The structure of isolating is shown in figure 14, comprises that also surrounding said source/drain electrode, said counter-doping trap 242 and said counter dopant regions 236 3 parts constitutes the degree of depth N type dopant well 231 on holistic both sides and following N type embedding layer 221 or N type substrate 211.Not surrounded with following N type embedding layer 221 or N type substrate 211 by said degree of depth N type dopant well 231 like N-LDMOS, then is non-isolation N-LDMOS.
In addition, N-LDMOS and P-LDMOS promptly can be asymmetric in the present embodiment, also can be symmetrical.Shown in Figure 14 is asymmetric N-LDMOS and asymmetrical P-LDMOS.Asymmetrical P-LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to another P type heavily doped region 266 of this raceway groove.Asymmetrical N-LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to another N type heavily doped region 267 of this raceway groove.Symmetrical structure is shown in figure 18. and the P-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another P type light doping section 256 and one of being close to this raceway groove is close to another P type heavily doped region 266 of this another P type light doping section 256.The N-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another N type light doping section 257 and one of being close to this raceway groove is close to another N type heavily doped region 267 of this another N type light doping section 257.
Shown in figure 18, the P-LDMOS of symmetry isolates through N type counter-doping trap 241 and other components and parts on the homepitaxy layer 222, and the N-LDMOS of symmetry both can be non-isolation, also can isolate.The structure of isolating is shown in figure 18, comprises that also surrounding said source/drain electrode, said counter-doping trap 242 and said counter dopant regions 236, said another source/drain electrode four parts constitutes the degree of depth N type dopant well 231 on holistic both sides and following N type embedding layer or N type substrate 211.N-LDMOS like symmetry is not surrounded with following N type embedding layer 221 or N type substrate 211 by said degree of depth N type dopant well 231, then is the non-isolation N-LDMOS of symmetry.
Above-mentioned LDMOS also can realize on N type epitaxial loayer; Shown in figure 15, on said substrate 211, also be provided with a N type epitaxial loayer 223, the raceway groove of P-LDMOS and N-LDMOS is positioned at this epitaxial loayer 223 surfaces; Source/drain electrode of said N-LDMOS is N type light doping section 257 and N type heavily doped region 267; The counter-doping trap 242 of said N-LDMOS is P type traps, and the counter dopant regions 236 of said N-LDMOS is P type doped regions, and its doping content is lower than said counter-doping trap 242.Source/drain electrode of said P-LDMOS is P type light doping section 256 and P type heavily doped region 266; The counter-doping trap 241 of said P-LDMOS is N type traps; The counter dopant regions 235 of said P-LDMOS forms by N type doped region or by N type epitaxial loayer 223, and its doping content is lower than said counter-doping trap 241.
Like Figure 15, when epitaxial loayer was the N type, said N-LDMOS isolated through P type counter-doping trap 242 and other components and parts on the homepitaxy layer 223, and P-LDMOS both can be non-isolation, also can isolate.The structure of isolating is shown in figure 15, comprises that also surrounding said source/drain electrode, said counter-doping trap 241 and said counter dopant regions 235 3 parts constitutes the degree of depth P type dopant well 232 on holistic both sides and following P type embedding layer 224 or P type substrate 211.Not surrounded with following P type embedding layer 224 or P type substrate 211 by said degree of depth P type dopant well 232 like P-LDMOS, then is non-isolation P-LDMOS.
Same N-LDMOS and P-LDMOS on N type epitaxial loayer both can be asymmetric, also can be symmetrical.Shown in Figure 15 is that asymmetric N-LDMOS and the asymmetrical P-LDMOS of asymmetrical P-LDMOS. also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to the assorted district 266 of another P type weight of this raceway groove.Asymmetrical N-LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to another N type heavily doped region 267 of this raceway groove.The P-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another P type light doping section 256 and one of being close to this raceway groove is close to another P type heavily doped region 266 of this another P type light doping section 256.The N-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another N type light doping section 257 and one of being close to this raceway groove is close to another N type heavily doped region 267 of this another N type light doping section 257.
The N-LDMOS of symmetry isolates through P type counter-doping trap 242 and other components and parts on the homepitaxy layer 223, and the P-LDMOS of symmetry equally both can be non-isolation, also can isolate.The structure of isolating comprises that also surrounding said source/drain electrode, said counter-doping trap 241 and said counter dopant regions 235, said another source/drain electrode four parts constitutes the degree of depth P type dopant well 232 on holistic both sides and following P type embedding layer 224 or P type substrate 211.P-LDMOS like symmetry is not surrounded with following P type embedding layer 224 or P type substrate 211 by said degree of depth P type dopant well 232, then is the non-isolation P-LDMOS of symmetry.
Embodiment two
A kind of LDMOS such as Figure 16, shown in Figure 17; Comprise a P-LDMOS and a N-LDMOS; Be positioned at jointly on the semi-conductive substrate 211, said P-LDMOS and N-LDMOS comprise that separately one is positioned at the raceway groove on these substrate 211 surfaces, and are positioned at the grid on this raceway groove; One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region 266,267 that the other and light doping section 256,257 and that be close to this raceway groove of said raceway groove is close to this light doping section 256,257; The one counter-doping trap 241,242 opposite with said source/drain electrode doping type, this counter-doping trap 241,242 are positioned at this raceway groove below and comprise this raceway groove fully; One another doped region 237,238 identical with said source/drain electrode doping type, this another doped region 237,238 surrounds heavily doped region 266,267, said light doping section 256,257 and the said counter-doping trap 241,242 of said source/drain electrodes.
Figure 16 illustrates said LDMOS and on P type epitaxial loayer, realizes.On said substrate 211, also be provided with a P type epitaxial loayer 222; The raceway groove of P-LDMOS and N-LDMOS is positioned at this epitaxial loayer 222 surfaces; Source/drain electrode of said N-LDMOS is N type light doping section 257 and N type heavily doped region 267; The counter-doping trap 242 of said N-LDMOS is P type traps, and another doped region 238 of said N-LDMOS is N type doped regions, and its doping content is lower than said counter-doping trap 242.Source/drain electrode of said P-LDMOS is P type light doping section 256 and P type heavily doped region 266; The counter-doping trap 241 of said P-LDMOS is N type traps; Another doped region 237 of said P-LDMOS is P type doped regions or is formed by P type epitaxial loayer 222 that its doping content is lower than said counter-doping trap 241.
Like Figure 16, when epitaxial loayer was the P type, said N-LDMOS isolated through N type doped region 238 and other components and parts on the homepitaxy layer 222, and P-LDMOS both can be non-isolation, also can isolate.The structure of isolating is shown in figure 16, comprises that also surrounding said source/drain electrode, said counter-doping trap 241 and said another doped region 237 3 parts constitutes the degree of depth N type dopant well 231 on holistic both sides and following N type embedding layer 221 or N type substrate 211.Not surrounded with following N type embedding layer 221 or N type substrate 211 by said degree of depth N type dopant well 231 like P-LDMOS, then is non-isolation P-LDMOS.
In addition, N-LDMOS and P-LDMOS promptly can be asymmetric in the present embodiment, also can be symmetrical.Shown in Figure 16 is asymmetric N-LDMOS and asymmetrical P-LDMOS.Asymmetrical P-LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to another P type heavily doped region 266 of this raceway groove.Asymmetrical N-LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to another N type heavily doped region 267 of this raceway groove.The P-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another P type light doping section 256 and one of being close to this raceway groove is close to another P type heavily doped region 266 of this another P type light doping section 256.The N-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another N type light doping section 257 and one of being close to this raceway groove is close to another N type heavily doped region 267 of this another N type light doping section 257.
The N-LDMOS of symmetry isolates through another doped region 238 of N type and other components and parts on the homepitaxy layer 222, and the P-LDMOS of symmetry both can be non-isolation, also can isolate.The structure of isolating comprises that also surrounding said source/drain electrode, said counter-doping trap 241 and said another doped region 237, said another source/drain electrode four parts constitutes the degree of depth N type dopant well 231 on holistic both sides and following N type embedding layer 221 or N type substrate 211.P-LDMOS like symmetry is not surrounded with following N type embedding layer 221 or N type substrate 211 by said degree of depth N type dopant well 231, then is the non-isolation P-LDMOS of symmetry.
Above-mentioned LDMOS also can realize on N type epitaxial loayer; Shown in figure 17; On said substrate 211, also be provided with a N type epitaxial loayer 223; The raceway groove of P-LDMOS and N-LDMOS is positioned at this epitaxial loayer 223 surfaces, and source/drain electrode of said N-LDMOS is N type light doping section 257 and N type heavily doped region 267, and the counter-doping trap 242 of said N-LDMOS is P type traps; Another doped region 238 of said N-LDMOS is N type doped regions or is formed by N type epitaxial loayer 223 that its doping content is lower than said counter-doping trap 242.Source/drain electrode of said P-LDMOS is P type light doping section 256 and P type heavily doped region 266, and the counter-doping trap 241 of said P-LDMOS is N type traps, and another doped region 237 of said P-LDMOS is P type doped regions, and its doping content is lower than said counter-doping trap 241.
Like Figure 17, when epitaxial loayer was the N type, said P-LDMOS isolated through another doped region 237 of P type and other components and parts on the homepitaxy layer 223, and N-LDMOS both can be non-isolation, also can isolate.The structure of isolating is shown in figure 17, comprises that also surrounding said source/drain electrode, said counter-doping trap 242 and said another doped region 238 3 parts constitutes the degree of depth P type dopant well 232 on holistic both sides and following P type embedding layer 224 or P type substrate 211.Not surrounded with following P type embedding layer 224 or P type substrate 211 by said degree of depth P type dopant well 232 like N-LDMOS, then is non-isolation N-LDMOS.
Equally, N-LDMOS on N type epitaxial loayer and P-LDMOS both can be asymmetric, also can be symmetrical.Shown in Figure 17 is that asymmetric N-LDMOS and the asymmetrical P-LDMOS of asymmetrical P-LDMOS. also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to the assorted district 266 of another P type weight of this raceway groove.Asymmetrical N-LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one, and to be positioned at said raceway groove other and be close to another N type heavily doped region 267 of this raceway groove.The P-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another P type light doping section 256 and one of being close to this raceway groove is close to another P type heavily doped region 266 of this another P type light doping section 256.The N-LDMOS of symmetry also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at by the said raceway groove and another N type light doping section 257 and one of being close to this raceway groove is close to another N type heavily doped region 267 of this another N type light doping section 257.
The P-LDMOS of symmetry isolates through another doped region 237 of P type and other components and parts on the homepitaxy layer 223, and the N-LDMOS of symmetry both can be non-isolation, also can isolate.The structure of isolating comprises that also surrounding said source/drain electrode, said counter-doping trap 242 and said another doped region 238, said another source/drain electrode four parts constitutes the degree of depth P type dopant well 232 on holistic both sides and following P type embedding layer 224 or P type substrate 211.N-LDMOS like symmetry is not surrounded with following P type embedding layer 224 or P type substrate 211 by said degree of depth P type dopant well 232, then is the non-isolation N-LDMOS of symmetry.
Embodiment three
Like Figure 14, shown in 15; The semiconductor device of a kind of integrating with LDMOS and CMOS; Comprise and be located at a CMOS and a LDMOS on the semi-conductive substrate 211; Said CMOS comprises a NMOS and a PMOS, and said LDMOS comprises a N-LDMOS and a P-LDMOS, it is characterized in that said PMOS and said NMOS comprise respectively:
One is positioned at the raceway groove on these substrate 211 surfaces, is positioned at the grid 270 on this raceway groove,
One source/drain electrode, this source/drain electrode comprise a light doping section 251,252 and are close to the heavily doped region 261,262 of this light doping section 251,252,
The one counter-doping trap 241,242 opposite with said source/drain electrode doping type.
Its characteristic is that also said P-LDMOS and said N-LDMOS comprise respectively:
One is positioned at the raceway groove on these substrate 211 surfaces, is positioned at the grid 270 on this raceway groove,
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region 266,267 that the other and light doping section 256,257 and that be close to this raceway groove of said raceway groove is close to this light doping section 256,257;
The one counter-doping trap 241,242 opposite with said source/drain electrode doping type, this counter-doping trap 241,242 are positioned at this raceway groove below and comprise this raceway groove fully;
One counter dopant regions 235,236 opposite with said source/drain electrode doping type, this counter dopant regions 235,236 is at the heavily doped region 266,267 of said source/drain electrode and said counter-doping trap 241, between 242.
Like Figure 14, shown in 15, the doping content of the heavily doped region 267 of source/drain electrode of said N-LDMOS is lower than the doping content of the heavily doped region 262 of said NMOS source/drain electrode.
Like Figure 14, shown in 15, the doping content of the heavily doped region 266 of source/drain electrode of said P-LDMOS is lower than the doping content of the heavily doped region 261 of said PMOS source/drain electrode.
Like Figure 14, shown in 15, the counter-doping trap 242 that said N-LDMOS and said NMOS have identical dopant profiles.
Like Figure 14, shown in 15, the counter-doping trap 241 that said P-LDMOS and said PMOS have identical dopant profiles.
Embodiment four
Like Figure 16, shown in 17; The semiconductor device of a kind of integrating with LDMOS and CMOS; Comprise and be located at a CMOS and a LDMOS on the semi-conductive substrate 211; Said CMOS comprises a NMOS and a PMOS, and said LDMOS comprises a N-LDMOS and a P-LDMOS, it is characterized in that said PMOS and said NMOS comprise respectively:
One is positioned at the raceway groove on these substrate 211 surfaces, is positioned at the grid 270 on this raceway groove,
One source/drain electrode, this source/drain electrode comprise a light doping section 251,252 and are close to the heavily doped region 261,262 of this light doping section 251,252,
The one counter-doping trap 241,242 opposite with said source/drain electrode doping type.
Its characteristic is that also said P-LDMOS and said N-LDMOS comprise respectively: one is positioned at the raceway groove on these substrate 211 surfaces, is positioned at the grid 270 on this raceway groove,
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region 266,267 that the other and light doping section 256,257 and that be close to this raceway groove of said raceway groove is close to this light doping section 256,257;
The one counter-doping trap 241,242 opposite with said source/drain electrode doping type, this counter-doping trap 241,242 are positioned at this raceway groove below and comprise this raceway groove fully;
One another doped region 237,238 identical with said source/drain electrode doping type, this another doped region 237,238 surrounds heavily doped region 266,267 and the light doping section 256,257 and the said counter-doping trap 241,242 of said source/drain electrodes.
Like Figure 16, shown in 17, the doping content of the heavily doped region 267 of source/drain electrode of said N-LDMOS is lower than the doping content of the heavily doped region 262 of said NMOS source/drain electrode.
Like Figure 16, shown in 17, the doping content of the heavily doped region 266 of source/drain electrode of said P-LDMOS is lower than the doping content of the heavily doped region 261 of said PMOS source/drain electrode.
Like Figure 16, shown in 17, said N-LDMOS has the identical counter-doping trap 242 of dopant profiles with said NMOS.
Like Figure 16, shown in 17, said P-LDMOS has the identical counter-doping trap 241 of dopant profiles with said PMOS.
To describe the manufacture process of above-mentioned four embodiment of the present invention below in detail.The structure that it must be noted that device provided by the present invention can realize through many different processes modes.Here described implementation method is a kind of method wherein, and this method should not be construed as limiting the invention.
Description of the invention is with the background that is applied as in power management, but any other application that high tension apparatus and low-voltage device are integrated all will belong to the scope that the present invention is contained.The low-voltage device of indication of the present invention is meant institute's accepted standard operating voltage device in the CMOS technology of being selected for use; And high tension apparatus is meant that drain/source can bear the device higher than normal voltage.Grid voltage is not limit, and can be the voltage identical with standard CMOS process, perhaps higher or lower than standard CMOS process voltage.As long as the drain pole tension is higher than the high tension apparatus that normal voltage is the present embodiment indication.For example, when selecting 0.25 micrometre CMOS process for use, the drain/source operating voltage of normal component is 2.5 volts, and this belongs to the low-voltage device of indication of the present invention.And high tension apparatus is meant that the voltage that drain/source bears is higher than 2.5 volts device, and the ceiling voltage no matter grid can bear is to be higher than, to be less than or equal to 2.5 volts.
Fig. 1 is the main technique flow process profile of processing LDMOS device of the present invention to Figure 13.According to the convention of semicon industry, all profiles of the present invention are not drawn in proportion.Just catch the main processing step of realizing this device architecture in the face of the description of technology down.Those of ordinary skill in the art should know wherein NM minor step, and the description of these main processing steps can not be construed as limiting the invention.
Fig. 1 is the profile after semiconductor device of the present invention is accomplished embedding layer and epitaxial loayer.Semiconductor device is begun by Semiconductor substrate 211, then growth one deck epitaxial loayer 212 on substrate 211.Epitaxial loayer 212 can not need sometimes yet.Common 211,212 all is P types, but also can all be the N type, perhaps one of them be the P type another be the N type.The P type of indication of the present invention is meant because of dopant species is different with the N type and finally makes semiconductor present different electric polarities.The P type mixes and normally injects boron element, but also can be that any other makes semiconductor present the element of P type.The N type mixes and has normally injected nitrogen (N) element or arsenic (As) element, but also any other makes semiconductor present the impurity of N type.Description in the present embodiment is an example with P type substrate.With epitaxial loayer 212 oxidations, pass through a mask then after photoetching earlier, orient the place that needs embedding layer 221.Mentioned herein to photoetching location be one technology commonly used in the semiconductor fabrication process.It is earlier semiconductor surface evenly to be coated the photoresist material, will need not the photoresist material exposure in place of mask through mask then after, remove the photoresist material of exposure again.And the photoresist material that stays is used for the mask of one technology down.Because this photoetching location is a technology commonly used in the semiconductor fabrication process, and its process is detailed in following technology no longer one by one.After embedding layer 221 is oriented in photoetching, the oxide layer at this place being eroded, is that mask carries out N type impurity and injects with photoresist material and oxide layer, and the diffusion of impurities that makes injection of heating up then also activates and forms embedding layer 221.Remove the photoresist material and the oxide layer on surface then, long again one deck epitaxial loayer 222 in the above.This layer epitaxial loayer 222 can be the N type, also can be the P type.Be example with the P type in the present embodiment.Usually this epitaxial loayer impurity concentration is lighter, as 1 * 10 13To 1 * 10 15Individual every cubic centimetre.A kind of in addition method that forms embedding layer 222 is elder generation's long epitaxial loayer 222 on substrate 211 and epitaxial loayer 212, the position of embedding layer 221 is oriented in the place that needs embedding layer 221 through mask lithography after, carries out the impurity formation embedding layer 221 that impurity injects and High temperature diffusion is injected with activation then.In addition, the method for any other formation embedding layer known in the art scope that all belongs to the present invention and covered.
Fig. 2 shows the profile after semiconductor technology is accomplished degree of depth N type trap.The area that needs degree of depth N type trap 231,235 is oriented in photoetching in the basic Chu of Fig. 1, carries out N type impurity and injects, and thermal diffusion forms degree of depth N type trap 231,235 then.Fig. 2 below has marked the formation position of 4 devices, and they are respectively: PMOS, NMOS, P-LDMOS, N-LDMOS.In order to simplify technology, N type trap 231 and 235 can be same Impurity Distribution.This makes forming N type trap 231,235 o'clock, only needs a mask.If N type trap 231,235 needs different impurity to distribute because designs is different, then need to form respectively N type trap 231 and 235 through twice mask.P type trap 236 both can be an epitaxial loayer 222 among the figure, also can be a degree of depth P type trap 236 of orienting through a mask.
Fig. 3 shows the profile after semiconductor technology is accomplished isolation channel.The method that forms isolation channel 225 commonly used has two kinds.A kind of be shallow-trench isolation (Shallow Trench Isolation, STI), another kind be basic regional oxidation isolation technology (LocalOxidation Of Silicon, LOCOS).Be example with LOCOS in the present embodiment.The position of orienting isolation channel through a mask lithography is earlier carried out oxidation then, removes photoresist material and surface oxide layer afterwards.After Fig. 3 showed the formation isolation channel, substrate 211 was divided into 4 zones, is separated by isolation channel between them.These 4 zones will form different devices: PMOS, NMOS, P-LDMOS and N-LDMOS respectively.Wherein NMOS and PMOS are the normal component that is provided in the CMOS technology, belong to the defined low-voltage device of present embodiment.These devices mainly are to be used for various circuit design, like controller, signal processor etc.And P-LDMOS and the N-LDMOS defined high tension apparatus that is present embodiment.Be generally used for the output stage of power transfer, in the drive circuit of power device, also can be used in the control circuit sometimes.
Fig. 4 shows the profile after semiconductor technology is accomplished N type trap 241 steps.Earlier orient the position that needs N type trap 241, form N type trap 241 through impurity injection of N type and thermal diffusion then by mask lithography.N type trap 241 is the essential steps that form PMOS and P-LDMOS.Show among the figure that this N type trap 241 is to be injected in the above-mentioned degree of depth trap 235 as far as P-LDMOS.Usually the impurity concentration of N type trap is higher than the impurity concentration of degree of depth N type trap 235 and epitaxial loayer 222.Usually finish N type trap impurity and inject the threshold voltage adjustment is carried out in the back at once with same N type trap mask impurity injection.PMOS can have different N type trap Impurity Distribution with P-LDMOS, but in order to make work simplification, can adopt same Impurity Distribution, with shared same mask.
Fig. 5 shows the profile after semiconductor technology is accomplished P type trap 242 steps.Earlier orient the place that needs P type trap 242, form P type trap 242 through p type impurity injection and thermal diffusion then by mask lithography.P type trap is the essential step that forms NMOS and N-LDMOS.Show among the figure that this P type trap is to be injected into above-mentioned epitaxial loayer 222 as far as NMOS, as far as N-LDMOS, this P type trap is to be injected in the above-mentioned degree of depth trap 236.Usually the impurity concentration of P type trap is higher than the impurity concentration of degree of depth P type trap 236 and epitaxial loayer 222.Usually after finishing the injection of P type trap impurity, the impurity that carries out the threshold voltage adjustment with same P type trap mask immediately injects.NMOS can have different P type trap Impurity Distribution with N-LDMOS, but equally in order to make work simplification, can adopt same Impurity Distribution, with shared same mask.
The process sequence of above-mentioned Fig. 5 and Fig. 4 can exchange.
Fig. 6 demonstrates the profile of semiconductor technology after accomplishing grid.Initial oxidation forms gate dielectric layer 275,276 to appointed thickness.The common material of dielectric layer is a silicon dioxide.Other typical media material also belongs to the scope that the present invention is contained.In order to simplify technology, improve switching frequency, gate dielectric 275 consistency of thickness of gate dielectric 276 thickness of high tension apparatus P-LDMOS and N-LDMOS best and low-voltage device PMOS and NMOS.Need only pass through the once oxidation process like this can accomplish.Sometimes need gate dielectric 276 thickness of high tension apparatus P-LDMOS or N-LDMOS to be higher than gate dielectric 275 thickness of low-voltage device PMOS and NMOS.At this moment then need carry out twice oxidation.In this case, but initial oxidation forms thick gate dielectric 276, orients the zone that needs thin gate dielectric 275 through a mask lithography then.Erode this regional medium, remove the photoresist material, reoxidize the gate dielectric 275 that forms low-voltage device PMOS and NMOS.Sometimes the gate dielectric of high tension apparatus P-LDMOS or N-LDMOS needs to carry out once threshold voltage adjustment impurity in this step and injects because thickness is too high.After grid oxic horizon forms, polysilicon is deposited on the gate dielectric 275,276, with suitable dopant species polysilicon doping is become N type or P type then.Mix to activate through high annealing then.Locate grid 270 with a mask at last.
Fig. 7 shows the profile after semiconductor technology is accomplished N type low pressure light doping section 252 and P type low pressure light doping section 251.Their position is confirmed by mask lithography location separately respectively.Inject through impurity then and form.Inject N type impurity and form this N type low pressure light doping section 252, inject p type impurity and form this P type low pressure light doping section 251.
Fig. 8 shows the profile after semiconductor technology forms N type high pressure light doping section 257 and P type high pressure light doping section 256.The position of N type high pressure light doping section 257 and P type high pressure light doping section 256 and width are confirmed by mask lithography location separately respectively, are formed through the impurity injection then.N type high pressure light doping section 257 injects N type impurity, and P type high pressure light doping section 256 injects p type impurity.Usually high pressure light doping section 257,256 is lower than 252,251 doping content of low pressure light doping section.This N type high pressure light doping section 257 is to form a necessary step of N-LDMOS, and it makes this utmost point of N-LDMOS to bear to be higher than the voltage that nmos source/drain electrode can bear.This utmost point is the drain electrode of N-LDMOS normally, but also source electrode.When drain electrode and source electrode all needed high pressure simultaneously sometimes, then drain electrode and source electrode all must be introduced this high pressure light doping section 257.P type high pressure light doping section 256 is to form a necessary step of P-LDMOS.It makes this utmost point of P-LDMOS to bear to be higher than the voltage that PMOS leakage/source electrode can bear.This utmost point is the drain electrode of P-LDMOS normally, but also source electrode.
Fig. 9 shows the profile after semiconductor technology forms grid curb wall structure 271.Grid curb wall structure 271 normally forms followed by a part of silica that erodes the grid polycrystalline silicon top layer behind the oxidation grid polycrystalline silicon.The mode of other formation 271 of this area also belongs within scope of invention.
Figure 10 shows the profile after semiconductor technology forms NMOS and N-LDMOS heavily doped region 262,267.They have mask lithography location separately to form through the injection of N type impurity then respectively.For NMOS; This heavily doped region 262 forms source/drain electrode of NMOS; For N-LDMOS, heavily doped region 267 forms the source/drain electrode of a low pressure, and another must bear high-voltage power supply/drain electrode and formed jointly by heavily doped region 267 and the light doping section 257 that is close to.Usually in order to simplify technology, the heavily doped region 262 of low-voltage device NMOS source/drain electrode has with the heavily doped region 267 identical doping contents of high tension apparatus N-LDMOS source/drain electrode and distributes.Can come the photoetching location by shared one deck mask like this.Under specific situation, the heavily doped region 267 of high tension apparatus N-LDMOS source/drain electrode can have the puncture voltage of the dopant profiles different with the heavily doped region of low-voltage device NMOS source/drain electrode 262 with source/drain electrode of improving high tension apparatus.Like this, need different masks to come the photoetching location separately.The heavily doped region 267 of high tension apparatus N-LDMOS source/drain electrode is close to the light doping section 257 of high tension apparatus N-LDMOS source/drain electrode in addition.
Figure 11 shows the profile after semiconductor technology forms PMOS and P-LDMOS source/drain electrode heavily doped region 261,266.They have mask lithography location separately to form through the p type impurity injection then respectively.For PMOS; This heavily doped region 261 forms source/drain electrode of PMOS; For P-LDMOS, heavily doped region 266 forms the source/drain electrode of a low pressure, and another the source/drain electrode that must bear high pressure is formed by heavily doped region 266 and the light doping section 256 that is close to jointly.Usually in order to simplify technology, the heavily doped region 261 of low-voltage device pmos source/drain electrode has with the heavily doped region 266 identical doping contents of high tension apparatus P-LDMOS source/drain electrode and distributes.Can come the photoetching location by shared one deck mask like this.Under specific situation, the heavily doped region 266 of high tension apparatus P-LDMOS source/drain electrode can have the puncture voltage of the dopant profiles different with the heavily doped region of low-voltage device NMOS source/drain electrode 261 with source/drain electrode of improving high tension apparatus.The heavily doped region 266 of high tension apparatus P-LDMOS source/drain electrode is close to the light doping section 256 of high tension apparatus P-LDMOS source/drain electrode in addition.
The process sequence of Figure 10 and Figure 11 can exchange.
Figure 12 shows the profile after semiconductor technology forms metal silicide layer 268.At first need to form the part of metal silicide layer through source/drain electrode among mask lithography location NMOS, PMOS, N-LDMOS, the P-LDMOS, the dielectric corrosion with the surface falls then, precipitates metal material (normally aluminium) to surface of silicon, final high temperature annealing.The metal that contacts with silicon face when high annealing and silicon generation chemical reaction form layer of metal silicide layer 268.Then all the other corrosion of metals that do not react are fallen.
Figure 13 shows the profile after semiconductor technology forms ground floor metal connector.The substrate that to accomplish earlier after the above-mentioned steps all precipitates one deck medium, orients the place that need open ground floor metal connector through a mask lithography then.The dielectric corrosion at this place is fallen and form the medium 280 among Figure 13.
Figure 14 shows that above-mentioned device forms the ground floor metal and connects the profile after 285.Substrate deposition layer of metal material (normally aluminium) after the completion above-mentioned steps is oriented the place that does not need metal through a mask lithography then; Should locate corrosion of metals falls; After removing the photoresist material, the metal that stays forms ground floor metal connecting layer 285.The technical process of Figure 13 and Figure 14 can repeat many times to be connected to form multiple layer metal.Usually semiconductor process flows has 1 to 7 layer of metal connection.
The deep layer N type trap 235 of P-LDMOS uses different masks to carry out horizontal location with N type trap 241 among Figure 14.Demonstration deep layer N type trap 235 from the side to following full the bag, in fact need not wrap N type trap 241 also passable entirely among the figure.Need only deep layer N type trap 235 join with N type trap 241 and to get final product.The current potential that like this guarantees deep layer N type trap 235 contacts with external circuitry through N type trap 241, is unlikely to make the current potential at this place floating empty.Usually deep layer N type trap 235 is more many deeply than N type trap 241, and impurity concentration is also gently many.This deep layer N type trap 235 forms a diode with P type heavily doped region 266 and P type light doping section 256.The maximum breakdown voltage of this P-LDMOS of puncture voltage decision of this diode.In order to increase puncture voltage, make deep layer N type trap impurity concentration low more good more, the degree of depth is good more deeply more.The output capacitance of this P-LDMOS also mainly is the junction capacitance that derives from above-mentioned diode.When deep layer N type trap impurity concentration is low more, when the degree of depth was darker, this junction capacitance was also more little.N type trap 241 is the same with N type trap in the standard P MOS technology, can save a mask.And can so that P-LDMOS minimum gate polar curve wide with the same of PMOS or very approaching.Final grid minimum feature is by Zener breakdown (Punch Through) the voltage decision of raceway groove.Because N type trap 241 impurity concentrations are higher more than 10 times than deep layer N type trap 235 usually, and P-LDMOS light doping section 256 impurity concentrations low and thin than heavily doped region 266, most of reverse pressure drop meeting is fallen at light doping section 256.Like this P-LDMOS grid minimum feature can be the same with PMOS grid minimum feature length or very near and be unlikely to draw the Zener breakdown at raceway groove position.And need not be as traditional P-LDMOS, in order to prevent Zener breakdown, the grid minimum feature is more much longer than corresponding PMOS.P-LDMOS among the present invention is because the grid minimum feature can be done very for a short time; Not only reduced channel resistance; And reduced the electric capacity of grid 270 to N type trap 241, and again because deep layer trap 235 can accomplish that impurity concentration is very low, and very dark; Not only increased the puncture voltage of the base stage/source electrode that drains, and the electric capacity of the base stage/source electrode that reduced to drain.
The same, the deep layer P type trap 236 of N-LDMOS uses different masks to carry out horizontal location with P type trap 242 among Figure 14.Demonstration deep layer P type trap 236 from the side to following full the bag, in fact need not wrap P type trap 242 also passable entirely among the figure.Need only deep layer P type trap 236 join with P type trap 242 and to get final product.The current potential that like this guarantees deep layer P type trap 236 is unlikely to make current potential floating empty through P type trap 242 and outer circuit contacts.Usually deep layer P type trap 236 is more many deeply than P type trap 242, and impurity concentration is also gently many.This deep layer P type trap 236 forms a diode with N type heavily doped region 267 and N type light doping section 257.The maximum breakdown voltage of this N-LDMOS of puncture voltage decision of this diode.In order to increase puncture voltage, make deep layer P type trap impurity concentration low more good more, the degree of depth is good more deeply more.The output capacitance of this N-LDMOS also mainly is the junction capacitance that derives from above-mentioned diode.When deep layer P type trap impurity concentration is low more, when the degree of depth was darker, this junction capacitance was also more little.P type trap 242 is the same with P type trap in the standard NMOS technology, can save a mask.And can be so that N-LDMOS minimum gate polar curve is wide the same with NMOS or very approaching.Final grid minimum feature is by the Zener breakdown voltage decision of raceway groove.Because P type trap 242 impurity concentrations are higher more than 10 times than deep layer P type trap 236 usually, and N-LDMOS light doping section 257 impurity concentrations low and thin than heavily doped region 267, most of reverse pressure drop meeting is fallen at light doping section 257.Like this N-LDMOS grid minimum feature can be the same with NMOS grid minimum feature length or very near and be unlikely to draw the Zener breakdown at raceway groove position.And need not be as traditional N-LDMOS, in order to prevent Zener breakdown, the grid minimum feature is more much longer than corresponding N MOS.N-LDMOS among the present invention is because the grid minimum feature can be done very for a short time; Not only reduced channel resistance; And reduced the electric capacity of grid 270 to N type trap 242, and again because deep layer trap 236 can accomplish that impurity concentration is very low, and very dark; Not only increased the puncture voltage of the base stage/source electrode that drains, and the electric capacity of the base stage/source electrode that reduced to drain.
When epitaxial loayer is the doping of P type, because also being the P type, the P type trap of N-LDMOS mixes, make whole N-LDMOS together like this through other device short circuit on P type epitaxial loayer/P type trap and the same epitaxial loayer.When needing N-LDMOS and other device isolation sometimes, can resemble Figure 14 through degree of depth N type trap 231 and embedding layer 221 N-LDMOS and epitaxial loayer 222 isolation.If substrate 211 is N types, then embedding layer 221 can not need yet, and directly degree of depth N type trap is diffused into N type substrate 211 and joins.
Figure 15 shows the another kind of implementation of this type of device.Principle on the device, advantage are identical with the device analysis of above-mentioned Figure 14.When epitaxial loayer 223 is the N type,, makes P-LDMOS pass through epitaxial loayer 223 like this and be communicated with other device on the same epitaxial loayer because deep layer N type trap 235 is the N type with N type trap 241.When needing P-LDMOS and other device isolation sometimes, can resemble Figure 15 through degree of depth P type trap 232 and P type embedding layer 224 P-LDMOS and epitaxial loayer 222 isolation.If substrate 211 is P types, then P type embedding layer 224 can not need yet, and directly degree of depth P type trap 232 is diffused into to join with P type substrate 211 to get final product.The device operation principle is the same.Because epitaxial loayer 223 is the N type, deep layer N type trap 235 can adopt N type epitaxial loayer 223 to save a mask layer at this moment.Deep layer P type trap 232 also can adopt with deep layer P type trap 236 same impurity branches and save a mask layer.
Figure 16 shows the another kind of implementation of this type of device.Different with Figure 14 is that P-LDMOS mid-deep strata trap 237 is the N types among P type rather than Figure 14.The P type trap that this P type had diffuseed to form after both having been mixed by the P type also can adopt epitaxial loayer 222 to save a mask layer.This P type trap 237 and P type heavily doped region 266 link to each other with other devices on the same substrate through P type epitaxial loayer.Sometimes need be with other device isolation on this device and the same substrate, then should resemble and through deep layer N type trap around this P type trap 231 and following N type embedding layer 221 this P-LDMOS isolated Figure 16.In order to improve puncture voltage, P type trap 237 impurity concentrations are low more good more, and P type trap 237 is darker than N type trap 241.Because this P type trap 237 forms a diode, the puncture voltage of the breakdown voltage limit P-LDMOS of this diode with following N type embedding layer 221.Improve the puncture voltage of P-LDMOS, the one, reduce the concentration of mixing of this P type trap, another is the degree of depth that strengthens this P type trap.If this P type trap adopts P epitaxial loayer 222, then concentration is decided by epitaxial loayer, and the degree of depth can be selected by the thickness of epitaxial loayer, and thermal diffusion process that need not be too much has been simplified technology.The same among N type trap 241 and Figure 14 can make this P-LDMOS grid minimum feature the same or very approaching with PMOS grid minimum feature length, not only reduced channel resistance, and reduced the electric capacity of grid 270 to N type trap 241.
What N-LDMOS was different with Figure 14 among Figure 16 is that deep layer trap 238 is the P types among N type rather than Figure 14.Because this trap 238 has been the N type,, need not to resemble and take special measure that N-LDMOS is isolated from the outside Figure 14 with P type substrate isolation.In order to save a mask, this N type trap 238 can adopt with Figure 16 in deep layer N type trap that P-LDMOS is isolated 231 same impurities concentration distribution.This N type trap 238 and following P epitaxial loayer 222 and P substrate 211 formation-diodes, in order to improve the puncture voltage of this type of N-LDMOS, N type trap 238 is good more deeply more, and it is low more good more to mix concentration.The same among P type trap 242 and Figure 14 can make this N-LDMOS grid minimum feature the same or very approaching with NMOS grid minimum feature length, not only reduced channel resistance, and reduced the electric capacity of grid 270 to P type trap 242.
Figure 17 shows the implementation of device shown in Figure 16 on N type epitaxial loayer.When epitaxial loayer 223 was the N type, deep layer P type trap 237 was isolated P-LDMOS and peripheral devices.In order to improve the P-LDMOS puncture voltage, this deep layer P type trap is good because of more deeply more, and doping content is low more good more.N-LDMOS mid-deep strata N type trap 238 is the N type with N type heavily doped region 267, and source/drain electrode of N-LDMOS is communicated with other device through epitaxial loayer 223.When N-LDMOS need isolate, shown in figure 17, can this N-LDMOS be isolated through deep layer P type trap 232 and following P type embedding layer 224.Perhaps directly deep layer P type trap is diffused into P type substrate and contacts also and can this N-LDMOS be isolated.Ditto said, in order to make this N-LDMOS increase in breakdown voltage, deep layer N type trap 238 is good more deeply more, and doping content is low more good more.In order to reduce one deck mask layer, this deep layer N type trap 238 can adopt N type epitaxial loayer 223.
Above-mentioned Figure 14 all is monolateral high pressure (normally drain electrode is high pressure) to P-LDMOS shown in Figure 17 and N-LDMOS, and another side is a low pressure.Sometimes need the source electrode of P-LDMOS and N-LDMOS can bear high pressure simultaneously with drain electrode, need only the high voltage structures of source/drain electrode among the figure be copied to the source/drain electrode of another side like this, such device will be the device that one source pole and drain electrode can both be born the symmetry of high pressure.Device shown in Figure 14 becomes source electrode and drain electrode, and can both to bear the symmetrical device structure of high pressure shown in figure 18.Draw no longer one by one at this corresponding to Figure 15,16,17 source electrode and the symmetrical device structure that to bear high pressure that drains.

Claims (32)

1. a LDMOS comprises semi-conductive substrate, and one is positioned at the raceway groove of this substrate surface, and is positioned at the grid on this raceway groove, it is characterized in that also comprising:
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section;
The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully;
One with counter dopant regions that said source/the drain electrode doping type is opposite, this counter dopant regions is between the heavily doped region and said counter-doping trap of said source/drain electrode;
The doping content of said counter dopant regions is lower than the doping content of counter-doping trap;
Said LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at said raceway groove other P type or N type heavily doped region.
2. LDMOS according to claim 1 is characterized in that: said source/drain electrode is P type light doping section and P type heavily doped region, and said counter-doping trap is a N type trap, and said counter dopant regions is a N type doped region, and its doping content is lower than said counter-doping trap.
3. LDMOS according to claim 2 is characterized in that: comprise that also surrounding said source/drain electrode, said counter-doping trap and said counter dopant regions three parts constitutes the degree of depth P type dopant well on holistic both sides and following P type embedding layer or P type substrate.
4. LDMOS according to claim 1; It is characterized in that: on said substrate, also be provided with a P type epitaxial loayer; Said raceway groove is positioned at this epi-layer surface, and said source/drain electrode is N type light doping section and N type heavily doped region, and said counter-doping trap is a P type trap; Said counter dopant regions is formed by P type epitaxial loayer, and its doping content is lower than said counter-doping trap.
5. LDMOS according to claim 1; It is characterized in that: on said substrate, also be provided with a N type epitaxial loayer; Said raceway groove is positioned at this epi-layer surface, and said source/drain electrode is P type light doping section and P type heavily doped region, and said counter-doping trap is a N type trap; Said counter dopant regions is formed by N type epitaxial loayer, and its doping content is lower than said counter-doping trap.
6. LDMOS according to claim 1 is characterized in that: said source/drain electrode is N type light doping section and N type heavily doped region, and said counter-doping trap is a P type trap, and said counter dopant regions is a P type doped region, and its doping content is lower than said counter-doping trap.
7. LDMOS according to claim 6 is characterized in that: comprise that also surrounding said source/drain electrode, said counter-doping trap and said counter dopant regions three parts constitutes the degree of depth N type dopant well on holistic both sides and following N type embedding layer or N type substrate.
8. according to claim 2 or 5 described LDMOS, it is characterized in that: this another source/drain electrode comprises one and is positioned at the P type heavily doped region that the other and P type light doping section and that be close to this raceway groove of said raceway groove is close to this P type light doping section.
9. according to claim 4 or 6 described LDMOS, it is characterized in that: this another source/drain electrode comprises one and is positioned at another N type heavily doped region that other and another N type light doping section and one that be close to this raceway groove of said raceway groove is close to this another N type light doping section.
10. LDMOS according to claim 2; It is characterized in that: this another source/drain electrode comprises one and is positioned at the P type heavily doped region that the other and P type light doping section and that be close to this raceway groove of said raceway groove is close to this P type light doping section, surrounds said source/drain electrode, said counter-doping trap and said counter dopant regions, said another source/drain electrode four parts constitute the degree of depth P type dopant well on holistic both sides and following P type embedding layer or P type substrate.
11. LDMOS according to claim 6; It is characterized in that: this another source/drain electrode comprises one and is positioned at another N type heavily doped region that other and another N type light doping section and one that be close to this raceway groove of said raceway groove is close to this another N type light doping section, surrounds said source/drain electrode, said counter-doping trap and said counter dopant regions, said another source/drain electrode four parts constitute the degree of depth N type dopant well on holistic both sides and following N type embedding layer or N type substrate.
12. the semiconductor device of integrating with LDMOS and CMOS comprises and is located at a CMOS and a LDMOS on the semi-conductive substrate that it is characterized in that this LDMOS comprises: one is positioned at the raceway groove of this substrate surface, is positioned at the grid on this raceway groove,
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section;
The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully;
One with counter dopant regions that said source/the drain electrode doping type is opposite, this counter dopant regions is between the heavily doped region and said counter-doping trap of said source/drain electrode;
The doping content of said counter dopant regions is lower than the doping content of counter-doping trap;
Said LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at said raceway groove other P type or N type heavily doped region.
13. the semiconductor device of integrating with LDMOS according to claim 12 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the doping content of the heavily doped region of source/drain electrode of this N-LDMOS is lower than the doping content of the heavily doped region of this NMOS source/drain electrode.
14. the semiconductor device of integrating with LDMOS according to claim 12 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the doping content of the heavily doped region of source/drain electrode of this P-LDMOS is lower than the doping content of the heavily doped region of this PMOS source/drain electrode.
15. the semiconductor device of integrating with LDMOS according to claim 12 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said NMOS and said PMOS include the trap under raceway groove and the raceway groove; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the counter-doping trap of this N-LDMOS has identical dopant profiles with trap under this NMOS raceway groove.
16. the semiconductor device of integrating with LDMOS according to claim 12 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said NMOS and said PMOS include the trap under raceway groove and the raceway groove; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the counter-doping trap of this P-LDMOS has identical dopant profiles with trap under this PMOS raceway groove.
17. a LDMOS comprises semi-conductive substrate, one is positioned at the raceway groove of this substrate surface, and is positioned at the grid on this raceway groove, it is characterized in that also comprising:
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section;
The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully;
One another doped region identical with said source/drain electrode doping type, this another doped region surrounds heavily doped region and the light doping section and the said counter-doping trap of said source/drain electrode:
The doping content of said another doped region is lower than the doping content of counter-doping trap;
Said LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at said raceway groove other P type or N type heavily doped region.
18. LDMOS according to claim 17 is characterized in that: said source/drain electrode is P type light doping section and P type heavily doped region, and said counter-doping trap is a N type trap, and said another doped region is a P type doped region, and its doping content is lower than said counter-doping trap.
19. LDMOS according to claim 18 is characterized in that: comprise that also surrounding said source/drain electrode, said counter-doping trap and said another doped region three parts constitutes the degree of depth N type dopant well on holistic both sides and following N type embedding layer or N type substrate.
20. LDMOS according to claim 17; It is characterized in that: on said substrate, also be provided with a P type epitaxial loayer; Said raceway groove is positioned at this epi-layer surface, and said source/drain electrode is P type light doping section and P type heavily doped region, and said counter-doping trap is a N type trap; Said another doped region is formed by P type epitaxial loayer, and its doping content is lower than said counter-doping trap.
21. LDMOS according to claim 17; It is characterized in that: on said substrate, also be provided with a N type epitaxial loayer; Said raceway groove is positioned at this epi-layer surface, and said source/drain electrode is N type light doping section and N type heavily doped region, and said counter-doping trap is a P type trap; Said another doped region is formed by N type epitaxial loayer, and its doping content is lower than said counter-doping trap.
22. LDMOS according to claim 17 is characterized in that: said source/drain electrode is N type light doping section and N type heavily doped region, and said counter-doping trap is a P type trap, and said another doped region is a N type doped region, and its doping content is lower than said counter-doping trap.
23. LDMOS according to claim 22 is characterized in that: comprise that also surrounding said source/drain electrode, said counter-doping trap and said another doped region three parts constitutes the degree of depth P type dopant well on holistic both sides and following P type embedding layer or P type substrate.
24. according to claim 18 or 20 described LDMOS, it is characterized in that: this another source/drain electrode comprises one and is positioned at the P type heavily doped region that the other and P type light doping section and that be close to this raceway groove of said raceway groove is close to this P type light doping section.
25. according to claim 21 or 22 described LDMOS, it is characterized in that: this another source/drain electrode comprises one and is positioned at the N type heavily doped region that the other and N type light doping section and that be close to this raceway groove of said raceway groove is close to this N type light doping section.
26. LDMOS according to claim 18; It is characterized in that: this another source/drain electrode comprises one and is positioned at another P type heavily doped region that other and another P type light doping section and one that be close to this raceway groove of said raceway groove is close to this another P type light doping section, surrounds said source/drain electrode, said counter-doping trap and said another doped region, said another source/drain electrode four parts constitute the degree of depth N type dopant well on holistic both sides and following N type embedding layer or N type substrate.
27. LDMOS according to claim 22; It is characterized in that: this another source/drain electrode comprises one and is positioned at another N type heavily doped region that other and another N type light doping section and one that be close to this raceway groove of said raceway groove is close to this another N type light doping section, surrounds said source/drain electrode, said counter-doping trap and said another doped region, said another source/drain electrode four parts constitute the degree of depth P type dopant well on holistic both sides and following P type embedding layer or P type substrate.
28. the semiconductor device of integrating with LDMOS and CMOS comprises and is located at a CMOS and a LDMOS on the semi-conductive substrate that it is characterized in that this LDMOS comprises: one is positioned at the raceway groove of this substrate surface, is positioned at the grid on this raceway groove,
One source/drain electrode, this source/drain electrode comprise one and are positioned at the heavily doped region that the other and light doping section and that be close to this raceway groove of said raceway groove is close to this light doping section;
The one counter-doping trap opposite with said source/drain electrode doping type, this counter-doping trap are positioned at this raceway groove below and comprise this raceway groove and this grid fully;
One another doped region identical with said source/drain electrode doping type, this another doped region surrounds heavily doped region and the light doping section and the said counter-doping trap of said source/drain electrode;
The doping content of said another doped region is lower than the doping content of counter-doping trap;
Said LDMOS also comprises another source/drain electrode, and this another source/drain electrode comprises one and is positioned at said raceway groove other P type or N type heavily doped region.
29. the semiconductor device of integrating with LDMOS according to claim 28 and CMOS; It is characterized in that: said CMOS wraps a NMOS and a PMOS; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the doping content of the heavily doped region of source/drain electrode of this N-LDMOS is lower than the doping content of the heavily doped region of this NMOS source/drain electrode.
30. the semiconductor device of integrating with LDMOS according to claim 28 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the doping content of the heavily doped region of source/drain electrode of this P-LDMOS is lower than the doping content of the heavily doped region of this PMOS source/drain electrode.
31. the semiconductor device of integrating with LDMOS according to claim 28 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said NMOS and said PMOS include the trap under raceway groove and the raceway groove; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the counter-doping trap of this N-LDMOS has identical dopant profiles with trap under this NMOS raceway groove.
32. the semiconductor device of integrating with LDMOS according to claim 28 and CMOS; It is characterized in that: said CMOS comprises a NMOS and a PMOS; Said NMOS and said PMOS include the trap under raceway groove and the raceway groove; Said LDMOS comprises a N-LDMOS and a P-LDMOS, and the counter-doping trap of this P-LDMOS has identical dopant profiles with trap under this PMOS raceway groove.
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