CN101377907B - Delay device for analog power supply signal - Google Patents
Delay device for analog power supply signal Download PDFInfo
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- CN101377907B CN101377907B CN 200710121215 CN200710121215A CN101377907B CN 101377907 B CN101377907 B CN 101377907B CN 200710121215 CN200710121215 CN 200710121215 CN 200710121215 A CN200710121215 A CN 200710121215A CN 101377907 B CN101377907 B CN 101377907B
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Abstract
The invention discloses an analog power supply signal retarding device, which comprises following components: an analog power supply, which is used for providing analog power supply to a display drive circuit; a first switch circuit, which is connected between the analog power supply and the display drive circuit and used for retarding the analog power supply and providing the retarded analog power supply to the display drive circuit; a second switch circuit, which is connected with the first switch circuit and used for providing a retarding signal to the first switch circuit; a retarding circuit, which is connected with the second switch circuit and used for providing retarding time to the second switch circuit; a logic power supply, which is connected with the retarding circuit and used for providing power supply to the retarding circuit. The analog power supply signal retarding device can lessen the residue electric charge in the panel, reduce the influence that is generated by pixel recharging during machine restarting, and improve the picture flicker phenomenon that appears during quick and repeated machine starting and stopping.
Description
Technical field
The present invention relates to a kind of delay device for analog power supply signal, particularly a kind of device of analog power supply signal time-delay when start.
Background technology
On some client, frequency input signal is the simulating signal of 60HZ, when starting shooting for the first time, scintillation (Power on flicker) does not appear in display frame, if but during to the rapid switching on and shutting down of system (the switching on and shutting down time interval＜2 second), will glimmer, the time interval of switching on and shutting down is more short, and it is more severe to glimmer, and the time interval of switching on and shutting down is very long, flicker will weaken, even disappears.
The reason of LCD generation scintillation is to have no progeny in the modular power source pass, owing to do not have signal on the thin film transistor (TFT) (TFT) of panel (Panel), remains with the electric charge that the last painting face drives panel in the panel on the pixel.During power remove, electric charge on the pixel mainly comes charge discharge on the counter plate pixel by transistorized electric leakage, the electric leakage of liquid crystal and the electric leakage of other materials, if electric charge does not discharge when just starting shooting on the pixel, remaining electric charge charges again to pixel and has produced influence in the panel, make the interior pixel of panel in the regular hour, can not reach required voltage, therefore scintillation has taken place.
At present, the method that solves the scintillation employing is the discharge resistance reduction with the shutoff voltage of thin film transistor (TFT), when the discharge resistance of shutoff voltage reduces, the fraction defective of scintillation drops to about 10% by original 100%, and the degree of flicker alleviates, this method is exactly the discharge resistance by the shutoff voltage that changes thin film transistor (TFT), make the shutoff voltage of thin film transistor (TFT) when turn-offing, can promptly bring up to 0 volt, accelerate the discharge of panel, this also is common improvement method in each big Liquid Crystal Module producer practical application, namely the discharge resistance resistance of the shutoff voltage by regulating thin film transistor (TFT) changes the drain electrode velocity of discharge of thin film transistor (TFT) to a certain extent, but 10% fraction defective is that module producer and display producer all cannot accept.
In addition, for further reducing the influence that electric charge remaining in panel pixel when starting shooting is again charged again and produced, from panel designs angle and cost angle, directly the flash-over characteristic cost of change panel is all very high, therefore, if can improve from the external circuit angle of panel, it will be reasonable plan.
Summary of the invention
The objective of the invention is provides a kind of delay device for analog power supply signal by some embodiment, electric charge remaining in the panel is reduced, the pixel influence that produces of charging again reduces when starting shooting again, the film flicker phenomenon that occurs when improving rapid repeated switching.
For achieving the above object, the invention provides a kind of delay device for analog power supply signal, comprising:
Analog power is for circuit of display driving provides analog power;
First on-off circuit is connected between described analog power and the circuit of display driving, and being used for provides described analog power time-delay back to circuit of display driving;
The second switch circuit is connected with described first on-off circuit, and being used for provides time delayed signal to described first on-off circuit;
Delay circuit is connected with described second switch circuit, and being used for provides delay time to described second switch circuit;
Logic power is connected with described delay circuit, and being used for provides power supply to described delay circuit.
Wherein, described delay circuit comprises first resistance connected in series and first electric capacity, and the other end of first resistance is connected with described logic power, the other end ground connection of first electric capacity.
Described first on-off circuit comprises P-channel enhancement type field effect transistor and second resistance, the source electrode of described P-channel enhancement type field effect transistor is connected with described analog power, drain electrode is connected with circuit of display driving, grid is connected with the second switch circuit, one end of second resistance is connected with the source electrode of P-channel enhancement type field effect transistor, and the other end is connected with the grid of P-channel enhancement type field effect transistor; Described second switch circuit comprises N channel enhancement field effect transistor and the 3rd resistance, the source ground of described N channel enhancement field effect transistor, drain electrode is connected with the grid of P-channel enhancement type field effect transistor, grid is connected with first resistance of delay circuit, one end of the 3rd resistance is connected other end ground connection with the grid of N channel enhancement field effect transistor.
Described first on-off circuit comprises bipolar npn transistor and second resistance, the transistorized emitter-base bandgap grading of described bipolar npn is connected with described analog power, collector is connected with circuit of display driving, base stage is connected with the second switch circuit, one end of second resistance is connected with the transistorized emitter-base bandgap grading of bipolar npn, and the other end is connected with the transistorized base stage of bipolar npn; Described second switch circuit comprises positive-negative-positive bipolar transistor and the 3rd resistance, the emitter grounding of described positive-negative-positive bipolar transistor, collector is connected with the transistorized base stage of bipolar npn, base stage is connected with first resistance of delay circuit, one end of the 3rd resistance is connected other end ground connection with the base stage of positive-negative-positive bipolar transistor.
Delay device for analog power supply signal of the present invention provides delay time by delay circuit, and then make the analog power supply signal time delays that offers circuit of display driving, remaining electric charge reduces significantly in the panel thereby make, the pixel influence that produces of charging again also further reduces when starting shooting again, the film flicker phenomenon that has occurred when having improved rapid repeated switching greatly.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is the structural representation of delay device for analog power supply signal of the present invention;
Fig. 2 is the structural representation of delay device for analog power supply signal one embodiment of the present invention;
Fig. 3 is the structural representation of another embodiment of delay device for analog power supply signal of the present invention;
Fig. 4 is for adopting the analog power supply signal output timing graph of a relation of delay device for analog power supply signal of the present invention front and back;
Fig. 5 is for adopting the analog power supply signal output waveform figure of delay device for analog power supply signal of the present invention front and back.
Description of reference numerals:
The 1-analog power; 2-first on-off circuit; The 3-circuit of display driving;
4-second switch circuit; The 5-delay circuit; The 6-logic power;
R1-first resistance; C1-first electric capacity; R2-second resistance;
R3-the 3rd resistance; The field effect of Q1-P channel enhancement field effect Q2-N channel enhancement
Pipe; Pipe;
Q3-NPN type bipolarity crystal Q4-PNP type bipolarity crystal 101-analog power supply signal;
Pipe; Pipe;
The 102-thin film transistor (TFT) is opened electric 103-thin film transistor (TFT) and is closed outage 104-analog power time-delay back letter
Press; Press; Number.
Embodiment
Fig. 1 is the structural representation of delay device for analog power supply signal of the present invention, and as shown in Figure 1, delay device for analog power supply signal comprises analog power 1, first on-off circuit 2, circuit of display driving 3, second switch circuit 4, delay circuit 5 and logic power 6.Analog power 1 provides analog power for circuit of display driving 3; First on-off circuit 2 is connected between analog power 1 and the circuit of display driving 3, and being used for provides described analog power time-delay back to circuit of display driving 3; Second switch circuit 4, delay circuit 5 and logic power 6 are connected in series in turn, and an end of second switch circuit 4 is connected with first on-off circuit 2, wherein, logic power 6 is used for providing power supply to described delay circuit 5, delay circuit 5 is used for providing delay time to described second switch circuit 4, and second switch circuit 4 is used for providing time delayed signal to described first on-off circuit 2.
Said apparatus, provide delay time by delay circuit to the second switch circuit, the second switch circuit provides time delayed signal to first on-off circuit, first on-off circuit and then provide the power supply signal of analog power for circuit of display driving by time-delay, be implemented in former hardwoods after the start in the time, unlatching/the shutoff voltage of thin film transistor (TFT) and other signals are all normal, and only delay time for circuit of display driving provides the power supply signal of analog power, thereby the former hardwood in the time in start, circuit of display driving does not carry out work, just on panel, pixel is not charged again, and then reduce remaining electric charge in the panel; At this a few hardwood after the time, remaining electric charge reduces in the panel, thereby the pixel institute of charging again exerts an influence and also reduces when starting shooting again, phenomenon of picture flicker in the time of therefore can improving rapid repeated switching.
Fig. 2 is the structural representation of delay device for analog power supply signal one embodiment of the present invention, as shown in Figure 2, delay circuit 5 is made up of first resistance R 1 connected in series and first capacitor C 1, and first resistance R, 1 other end is connected with the input end of logic power 6, the other end ground connection of first capacitor C 1; The second switch circuit is made of N channel enhancement field effect transistor Q2 and the 3rd resistance R 3, the source S ground connection of N channel enhancement field effect transistor Q2, the grid G of P-channel enhancement type field effect transistor Q1 in drain D and first on-off circuit is connected, grid G is connected with first resistance R 1 of delay circuit, one end of the 3rd resistance R 3 is connected other end ground connection with the grid G of N channel enhancement field effect transistor.
First on-off circuit 2 is made of P-channel enhancement type field effect transistor Q1 and second resistance R 2, the source S of above-mentioned P-channel enhancement type field effect transistor Q1 is connected with analog power 1, drain D is connected with circuit of display driving 3, grid G is connected with second switch circuit 4, one end of second resistance R 2 is connected with the source S of P-channel enhancement type field effect transistor Q1, and the other end is connected with the grid G of P-channel enhancement type field effect transistor Q1.
Starting shooting moment, logic power 4 at first is input to power supply signal in the RC delay circuit 5, because the existence of the typical delay circuit 5 that first resistance R 1, first capacitor C 1 constitute, make the grid G and the no-voltage that arrive N channel enhancement field effect transistor Q2 within a certain period of time exist, namely within delay value, N channel enhancement field effect transistor Q2 opens, and P-channel enhancement type field effect transistor Q1 closes, the output of circuit of display driving 3 no-voltages; When the time surpasses the above-mentioned certain hour of regulation, N channel enhancement field effect transistor Q2 closes, P-channel enhancement type field effect transistor Q1 opens, the voltage of circuit of display driving 3 outputs equals the voltage of analog power 1, thereby realized the time-delay output of analog power 1, adopt the analog power supply signal output timing relation of delay device for analog power supply signal front and back as shown in Figure 4, T1 be under the normal condition analog power supply signal 101 than the output delay time of grid cut-in voltage 102 and gate off voltage 103, T2 is for using this device back analog power supply signal 101 than the output delay time of grid cut-in voltage 102 and gate off voltage 103, as can be seen from Figure 3, the value of T2 will be much larger than the value of T1, remaining electric charge reduced in the time of T2 in the panel thereby make, the pixel institute of charging again exerts an influence and reduces when starting shooting again, the film flicker phenomenon that has occurred when having improved rapid repeated switching greatly.
Fig. 3 is the structural representation of another embodiment of delay device for analog power supply signal of the present invention, as shown in Figure 3, delay circuit 5 is made up of first resistance R 1 connected in series and first capacitor C 1, and first resistance R, 1 other end is connected with the input end of logic power 6, the other end ground connection of first capacitor C 1; Second switch circuit 4 is made of positive-negative-positive bipolar transistor Q4 and the 3rd resistance R 3, the emitter-base bandgap grading E ground connection of positive-negative-positive bipolar transistor Q4, the base stage of bipolar npn transistor Q3 in collector C and first on-off circuit is connected, base stage B is connected with first resistance R 1 of delay circuit 5, one end of the 3rd resistance R 3 is connected other end ground connection with the base stage of positive-negative-positive bipolar transistor Q4.
First on-off circuit is made of bipolar npn transistor Q3 and second resistance R 2, the emitter-base bandgap grading E of bipolar npn transistor Q3 is connected with analog power 1, collector C is connected with circuit of display driving 3, base stage B is connected with second switch circuit 4, one end of second resistance R 2 is connected with the emitter-base bandgap grading E of bipolar npn transistor Q3, and the other end is connected with the base stage B of bipolar npn transistor Q3.
Starting shooting moment, logic power 6 at first is input to power supply signal in the RC delay circuit 5, because the existence of the typical delay circuit that first resistance R 1, first capacitor C 1 constitute, make the base stage and the no-voltage that arrive positive-negative-positive bipolar transistor Q4 within a certain period of time exist, namely within delay value, positive-negative-positive bipolar transistor Q4 opens, and bipolar npn transistor Q3 closes, the output of circuit of display driving 3 no-voltages; When the time surpasses the above-mentioned certain hour of regulation, positive-negative-positive bipolar transistor Q4 closes, bipolar npn transistor Q3 opens, and the voltage of circuit of display driving 3 outputs equals the voltage of analog power 1, thereby has realized the time-delay output of analog power 1.Fig. 5 is for adopting the analog power supply signal output waveform figure of delay device for analog power supply signal of the present invention front and back, generally, after start, analog power supply signal 101 is only than logic power signal lag T1ms (about 5 to 10ms), this is for when providing power supply to circuit of display driving, logic power 6 is provided, to guarantee the normal running conditions of driving circuit prior to analog power 1.But the scintillation for the appearance of start back, the time of T1ms, be enough to make the remaining electric charge in the panel to reduce significantly far from, therefore by this device, analog power time-delay back signal 104 increases to T2ms (about 50-60ms) than the time of logic power signal lag, be enough to make the remaining electric charge in the panel to reduce significantly, use these device front and back analog power supply signal waveform as shown in Figure 5.
It should be noted that at last: above each embodiment is not intended to limit only in order to technical scheme of the present invention to be described; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (4)
1. a delay device for analog power supply signal is characterized in that, comprising:
Analog power is for circuit of display driving provides analog power;
First on-off circuit is connected between described analog power and the circuit of display driving, and being used for provides described analog power time-delay back to circuit of display driving;
The second switch circuit is connected with described first on-off circuit, and being used for provides time delayed signal to described first on-off circuit;
Delay circuit is connected with described second switch circuit, and being used for provides delay time to described second switch circuit;
Logic power is connected with described delay circuit, and being used for provides power supply to described delay circuit;
Described first on-off circuit comprises P-channel enhancement type field effect transistor and second resistance; The source electrode of described P-channel enhancement type field effect transistor is connected with described analog power, and drain electrode is connected with circuit of display driving, and grid is connected with described second switch circuit; One end of described second resistance is connected with the source electrode of described P-channel enhancement type field effect transistor, and the other end is connected with the grid of described P-channel enhancement type field effect transistor;
Perhaps, described first on-off circuit comprises bipolar npn transistor and second resistance; The transistorized emitter-base bandgap grading of described bipolar npn is connected with described analog power, and collector is connected with described circuit of display driving, and base stage is connected with described second switch circuit; One end of described second resistance is connected with the transistorized emitter-base bandgap grading of bipolar npn, and the other end is connected with the transistorized base stage of described bipolar npn.
2. delay device for analog power supply signal according to claim 1, it is characterized in that: described delay circuit comprises first resistance connected in series and first electric capacity, the other end of described first resistance is connected with described logic power, the other end ground connection of described first electric capacity.
3. delay device for analog power supply signal according to claim 1, it is characterized in that: when described first on-off circuit comprised P-channel enhancement type field effect transistor and second resistance, described second switch circuit comprised N channel enhancement field effect transistor and the 3rd resistance; The source ground of described N channel enhancement field effect transistor, drain electrode is connected with the grid of described P-channel enhancement type field effect transistor, and grid is connected with first resistance of described delay circuit; One end of described the 3rd resistance is connected other end ground connection with the grid of described N channel enhancement field effect transistor.
4. delay device for analog power supply signal according to claim 1, it is characterized in that: when described first on-off circuit comprised bipolar npn transistor and second resistance, described second switch circuit comprised positive-negative-positive bipolar transistor and the 3rd resistance; The emitter grounding of described positive-negative-positive bipolar transistor, collector is connected with the transistorized base stage of described bipolar npn, and base stage is connected with first resistance of described delay circuit; One end of described the 3rd resistance is connected other end ground connection with the base stage of positive-negative-positive bipolar transistor.
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| CN 200710121215 CN101377907B (en) | 2007-08-31 | 2007-08-31 | Delay device for analog power supply signal |
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| CN 200710121215 CN101377907B (en) | 2007-08-31 | 2007-08-31 | Delay device for analog power supply signal |
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| CN101377907B true CN101377907B (en) | 2013-07-17 |
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| CN109509454B (en) * | 2018-12-24 | 2021-10-01 | 惠科股份有限公司 | Driving device, circuit driving method and display panel |
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| CN110827784A (en) * | 2019-10-24 | 2020-02-21 | 深圳市华星光电技术有限公司 | Drive circuit and control method thereof |
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Effective date of registration: 20201123 Address after: 215200 No. 1700, Wujiang economic and Technological Development Zone, Suzhou, Jiangsu, Zhongshan North Road Patentee after: Gaochuang (Suzhou) Electronics Co.,Ltd. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Address before: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee before: BOE TECHNOLOGY GROUP Co.,Ltd. Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |