CN101373299A - FFS thin-film transistor LCD device pixel structure and manufacturing method thereof - Google Patents
FFS thin-film transistor LCD device pixel structure and manufacturing method thereof Download PDFInfo
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- CN101373299A CN101373299A CNA2007101205140A CN200710120514A CN101373299A CN 101373299 A CN101373299 A CN 101373299A CN A2007101205140 A CNA2007101205140 A CN A2007101205140A CN 200710120514 A CN200710120514 A CN 200710120514A CN 101373299 A CN101373299 A CN 101373299A
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Abstract
The invention discloses an FFS thin-film transistor LCD (liquid-crystal display) pixel structure including a base plate as well as a grid line and a data line formed on the base plate. The grid line and the data line cross to define a pixel unit including a thin-film transistor part, a common electrode, a first layer of pixel electrode layer and a second layer of pixel electrode layer, wherein, the first layer of pixel electrode layer is insulated with the second layer of pixel electrode layer through an insulating layer; the first layer of pixel electrode layer is connected with the common electrode; the second layer of pixel electrode layer is connected with the source electrode and the drain electrode of the thin-film transistor; and the figures of the first layer of pixel electrode layer and the second layer of pixel electrode layer are arranged across. The invention further discloses a manufacturing method for the FFS thin-film transistor LCD pixel structure. The pixel structure and the manufacturing method of the invention can improve process controllability and reliability and further improve product yield, and improve the generation efficiency of the horizontal component of an electric field and further improve product performance.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD (TFT LCD), relate in particular to a kind of fringe field switching (FFS:Fringe Field Switch) pixel structure for thin film transistor liquid crystal display and manufacture method thereof.
Background technology
The LCD development has become the main flow flat-panel monitor rapidly.From appearance so far, under various countries slip-stick artist's effort, LCD has developed several kinds such as TN, IPS, PVA, MV, FFS, and its drive pattern and display effect are not quite similar, and have his own strong points.Wherein, the FFS Thin Film Transistor-LCD has shown good display capabilities and effect with its its specific structure characteristics and drive principle.According to test data, the contrast of FFS Thin Film Transistor-LCD can reach 350:1, and the visual angle is that aperture opening ratio is more than 53%, no color differnece or the like more than 170 degree.By data as can be seen, the FFS LCD Structure of thin film transistor is a kind of outstanding LCD design.
FFS LCD Structure of thin film transistor more complicated, processing step is more, realizes difficulty.The FFS Thin Film Transistor-LCD is different from the common liquid crystals display at the process sequence of array processes section.In manufacturing process, ground floor is transparent pixels electrode layer (is generally ITO, or claims 1ITO), and the second layer is the grid metal level.Because pixel electrode layer is transparent material, for the making of each layer of back has brought certain difficulty.Simultaneously, FFS Thin Film Transistor-LCD drive principle has determined to have only the horizontal component of electric field at the second transparent pixels electrode layer edge (being called 2ITO) partly to be effective driving electric field.And in the existing FFS thin-film transistor liquid crystal display array structural design, since 1ITO and 2ITO overlapping over against, and apart from very near, the electric field intensity of vertical electric field is very big between 1ITO and the 2ITO, so that the generation efficient of horizontal component of electric field is very low, its electric field synoptic diagram is as shown in Figure 1.
Summary of the invention
The objective of the invention is in order to overcome the defective of prior art, a kind of FFS pixel structure for thin film transistor liquid crystal display and manufacture method thereof are provided, changing to ground floor by the process sequence with the array processes section is the grid metal level, the second layer is the ground floor pixel electrode layer, process controllability and reliability have been improved, and then the yield rate of raising product, and by changing the shape of ground floor pixel electrode layer pattern, reduce driving voltage, the improve the standard generation efficient of electric field, thus the performance of product promoted.
To achieve these goals, the invention provides a kind of FFS pixel structure for thin film transistor liquid crystal display, comprising:
One substrate, a grid line and data line; Described grid line and data line are formed on the described substrate; Described grid line and data line intersection definition one pixel cell, each pixel cell comprises film transistor device, public electrode, ground floor pixel electrode layer and second layer pixel electrode layer;
Wherein, separate by insulation course between described ground floor pixel electrode layer and the second layer pixel electrode layer; Described ground floor pixel electrode layer is connected with public electrode; Described second layer pixel electrode layer is connected with the source-drain electrode of thin film transistor (TFT); The figure of described ground floor pixel electrode layer and second layer pixel electrode layer is for being staggered.
In the such scheme, described ground floor pixel electrode layer segment is formed directly on the described substrate; Part is overlapped on the public electrode and forms described ground floor pixel electrode layer and be connected with public electrode.Perhaps described grid line and public electrode are positioned at on one deck, cover insulation course on it, described ground floor pixel electrode layer is formed on this insulation course top, connect by connecting line between described ground floor pixel electrode layer and the public electrode, and the material of connecting line is identical with the material of described second layer pixel electrode layer.All be formed with opening on the figure of described ground floor pixel electrode layer and second layer pixel electrode layer, the figure A/F of wherein said ground floor pixel electrode layer is 1 μ m-5 μ m; The figure A/F of described second layer pixel electrode layer is 2 μ m-6 μ m.
To achieve these goals, the present invention provides a kind of manufacture method of FFS pixel structure for thin film transistor liquid crystal display simultaneously, comprising:
Step 2, preparation ground floor insulation course on the substrate of completing steps 1; Deposition ground floor pixel electrode layer forms ground floor pixel electrode layer pattern by photoetching and etching technics on the ground floor insulation course;
Step 4, on the substrate of completing steps 3, prepare insulating protective layer, technology by photoetching and etching forms the source-drain electrode connecting hole respectively at the source-drain electrode place, form public electrode and ground floor pixel electrode layer connecting hole at ground floor pixel electrode layer and public electrode intersection location; Wherein, the source-drain electrode connecting hole is driveed to the source and is leaked metal level, and public electrode and ground floor pixel electrode layer connecting hole are opened to public electrode and ground floor pixel electrode layer;
In the such scheme, the ground floor pixel electrode layer pattern that forms in the described step 2 and the second layer pixel electrode layer pattern of step 5 kind of formation are for being staggered.All be formed with opening on the second layer pixel electrode layer pattern that forms in ground floor pixel electrode layer pattern that forms in the described step 2 and the step 5, wherein the figure A/F of the ground floor pixel electrode layer of Xing Chenging is 1 μ m-5 μ m; The figure A/F of the second layer pixel electrode layer that forms is 2 μ m-6 μ m.
To achieve these goals, the present invention also provides a kind of manufacture method of FFS pixel structure for thin film transistor liquid crystal display simultaneously, comprising:
Step 2, deposition ground floor pixel electrode layer forms ground floor pixel electrode layer pattern by photoetching and etching technics on the substrate of completing steps 1, and ground floor pixel electrode layer visuals is overlapped on the public electrode;
Step 4 prepares insulating protective layer on the substrate of completing steps 3, the technology by photoetching and etching forms the source-drain electrode connecting hole respectively at the source-drain electrode place, and wherein the source-drain electrode connecting hole is driveed and leaked metal level to the source;
In the such scheme, the ground floor pixel electrode layer pattern that forms in the described step 2 and the second layer pixel electrode layer pattern of step 5 kind of formation are for being staggered.All be formed with opening on the ground floor pixel electrode layer pattern that forms in the described step 2 and the second layer pixel electrode layer pattern of step 5 kind of formation, wherein the figure A/F of the ground floor pixel electrode layer of Xing Chenging is 1 μ m-5 μ m; The figure A/F of the second layer pixel electrode layer that forms is 2 μ m-6 μ m.
Compare with prior art, the present invention has reduced the density of vertical electric field between upper/lower electrode by in the upper shed of ground floor pixel electrode layer, has increased the intensity of edge horizontal component of electric field, has improved the generation efficient of horizontal component of electric field.Simultaneously, by structural change, gate metal layer as ground floor, has been improved the controllability of technology, thereby improved the yield rate of product.
Description of drawings
Fig. 1 is a prior art FFS dot structure electric field synoptic diagram;
Fig. 2 is a FFS dot structure synoptic diagram in the specific embodiment of the invention 1;
Fig. 3 is an A-A position sectional view among Fig. 2;
Fig. 4 is a FFS dot structure electric field synoptic diagram in the specific embodiment of the invention 1;
Fig. 5 is grid line and gate electrode in the specific embodiment 1, common pattern of electrodes synoptic diagram;
Fig. 6 is a B-B position sectional view among Fig. 5;
Fig. 7 is a pixel structural representation after the ground floor pixel electrode layer completes in the specific embodiment 1;
Fig. 8 is a C-C position sectional view among Fig. 7;
Fig. 9 is a pixel structural representation after insulating protective layer is finished in the specific embodiment 1;
Figure 10 is a D-D position sectional view among Fig. 9;
Figure 11 is a FFS dot structure synoptic diagram in the specific embodiment of the invention 2;
Figure 12 is an E-E position sectional view among Figure 11;
Figure 13 is a pixel structural representation after the ground floor pixel electrode layer completes in the specific embodiment 2;
Figure 14 is a F-F position sectional view among Figure 13;
Figure 15 is a pixel structural representation after insulating protective layer is finished in the specific embodiment 2;
Figure 16 is a G-G position sectional view among Figure 15.
Identify among the figure: 1, glass substrate; 21, grid line and gate electrode; 22, public electrode; 3, ground floor insulation course; 4, second layer insulation course; 5, amorphous silicon layer; 6, doped silicon layer; 71, data line; 72, source-drain electrode; 8, insulating protective layer; 9, ground floor pixel electrode layer; 101, second layer pixel electrode layer and source-drain electrode connecting portion; 102, second layer pixel electrode layer; 103, public electrode and ground floor pixel electrode layer connecting line; 111, source-drain electrode connecting hole; 112, public electrode and ground floor pixel electrode layer connecting hole.
Embodiment
Below in conjunction with the drawings and specific embodiments, dot structure of the present invention is further elaborated.
Fig. 2 is the synoptic diagram of FFS dot structure one specific embodiment of the present invention; Fig. 3 is an A-A sectional view among Fig. 2.As shown in Figures 2 and 3, FFS dot structure of the present invention: glass substrate 1, be formed on grid line and gate electrode 21 and public electrode 22 on the glass substrate, cover ground floor insulation course 3 on it, on the ground floor insulation course 3 ground floor pixel electrode layer 9 (1st ITO); Be second layer insulation course 4 on ground floor pixel electrode layer 9 electrodes; On the second layer insulation course 4 above the gate electrode, form thin-film transistor structure, comprising: amorphous silicon layer 5, doped silicon layer 6, source-drain electrode 72.Signal wire 71 is connected with the source-drain electrode 72 of each pixel; Be insulating protective layer 8 thereon; Second layer pixel electrode layer 102 (2ndITO) is formed on the insulating protective layer 8, is staggered with ground floor pixel electrode layer 9, and second layer pixel electrode layer 102 leaks connecting portion 101 by second layer pixel electrode layer and source and is connected with source-drain electrode 72; Public electrode 22 is connected with ground floor pixel electrode layer connecting line 103 by public electrode with ground floor pixel electrode layer 9.
Owing to, reduced the vertical electric field composition between two electrodes, increased the horizontal component of electric field part, thereby improved the generation efficient of horizontal component of electric field in the present embodiment on the position of second layer pixel electrode layer 102, making blank figure on the ground floor pixel electrode layer 9.The electric field synoptic diagram as shown in Figure 4.
One pixel structure process method to this implementation column is described further below.
At first, be that preparation thickness is the grid metal level of 0.1 μ m-0.5 μ m on the glass substrate of 0.5mm-1.0mm at thickness, the material of grid metal level is metals such as Al, MO/Al alloy, MO or Cu, the preparation method can be methods such as sputter, evaporation or plating.After finishing, use the technology of photoetching to form the photoresist figure on the grid metal film, again through etching technics formation grid line and the figure of gate electrode 21 and the figure of public electrode 22, as shown in Figure 5 and Figure 6, lithographic method can be to do quarter, the wet quarter or both mixing.Preparing thickness thereon by PECVD or other modes again is
The ground floor insulation course, material is silicon nitride (SiNx).Deposit thickness on the ground floor insulation course
Be the ground floor pixel electrode layer, material can be P-indium oxide tantalum (ITO) or indium zinc oxide (IZO) etc.Form ground floor pixel electrode layer 9 figures by photoetching, etching technics successively, forming width on pixel is the opening figure of 1 μ m-5 μ m, and figure is spent to 20 degree from the horizontal by 5.Concrete structure as shown in Figure 7 and Figure 8.
Preparation thickness is on substrate
Second layer insulation course 4, material is silicon nitride (SiNx) or other insulating material, the preparation method can be PECVD or physics coating etc.On second layer insulation course 4, use " 5mask " or " 4mask " technology to prepare film transistor device and data line again, comprising: source-drain electrode 72 and data line 71 etc.Concrete structure such as Fig. 9 and shown in Figure 10.The data line width is 1 μ m-9 μ m.
With methods such as PECVD or physics coatings, preparation thickness is on substrate
Insulating protective layer 8, material are silicon nitride (SiNx) or are other insulating material.Use the technology of photoetching and etching to form source-drain electrode connecting hole 111 respectively in the source-drain electrode position, form public electrode and ground floor pixel electrode layer connecting hole 112 at ground floor pixel electrode layer and public electrode intersection location.Wherein, source-drain electrode connecting hole 111 is driveed to the source and is leaked metal level, and public electrode and ground floor pixel electrode layer connecting hole 112 are opened to public electrode and ground floor pixel electrode layer place.Lithographic method can be dry etching or wet etching or mixed method.
Deposit thickness is
Second layer pixel electrode layer, material P-indium oxide tantalum (ITO) or indium zinc oxide (IZO) or other electrically conducting transparent materials.The preparation method can be modes such as sputter, evaporation or physics coating.The method that re-uses photoetching and etching forms second layer pixel electrode layer 102 figures, reaches public electrode and ground floor pixel electrode layer connecting line 103.Wherein: second layer pixel electrode layer 102 is connected with source-drain electrode 72 by source-drain electrode connecting hole 111, and having width on the electrode is 2 μ m-6 μ m openings (greater than the opening on the ground floor pixel), and the width that visuals is arranged is 3 μ m-8 μ m.Pixel electrode is staggered up and down; Public electrode is connected ground floor pixel electrode layer 9 and public electrode 22 with ground floor pixel electrode layer connecting line 103.Concrete structure as shown in Figures 2 and 3.
In the above-mentioned manufacture method,, improved the controllability of technology, thereby improved the yield rate of product because gate metal is made as ground floor.
Concrete implementation column 2
Figure 11 is the synoptic diagram of FFS dot structure one specific embodiment of the present invention; Figure 12 is an A-A sectional view among Figure 11.As Figure 11 and shown in Figure 12, FFS dot structure of the present invention: glass substrate 1, be formed on grid line and gate electrode 21 and public electrode 22 on the glass substrate, ground floor pixel electrode layer 9 (1stITO) part is formed on the glass substrate, part directly is overlapped on the public electrode 22, covers ground floor insulation course 3 on grid line and gate electrode 21, public electrode 22 and the ground floor pixel electrode layer 9; On the ground floor insulation course 3 above the gate electrode, form thin-film transistor structure, comprising: amorphous silicon layer 5, doped silicon layer 6, source-drain electrode 72.Signal wire 71 is connected with the source-drain electrode 72 of each pixel; Be insulating protective layer 8 thereon; Second layer pixel electrode layer 102 (2nd ITO) is formed on the insulating protective layer 8, is staggered with ground floor pixel electrode layer 9, and is connected with source-drain electrode 72 by second layer pixel electrode layer and source leakage connecting portion 101.
With identical in the specific embodiment 1, present embodiment is owing to making blank figure on the ground floor pixel electrode layer on the position of second layer pixel electrode layer, reduce the vertical electric field composition between two electrode layers, increased the horizontal component of electric field part, thereby improved the generation efficient of horizontal component of electric field.The electric field synoptic diagram as shown in Figure 4.
One pixel structure process method to this implementation column is described further below.
At first, be that preparation thickness is the grid line of 0.1 μ m-0.5 μ m and gate electrode 21, and public electrode 22 figures on the glass substrate of 0.5mm-1.0mm at thickness, method therefor is described identical with embodiment 1, and the formation figure is identical with Fig. 5 and Fig. 6.
Then, deposit thickness
Be the ground floor pixel electrode layer, material can be alpha-oxidation indium tantalum (ITO).After photoetching process, select not alpha-oxidation indium tantalum (ITO) the etching liquid etching that can react with the gate metal material, form ground floor pixel electrode layer 9 figures, forming width on pixel is the opening figure of 1 μ m-5 μ m, and figure is spent to 20 degree from the horizontal by 5.One section is connected with public electrode 22.Concrete structure such as Figure 13 and shown in Figure 14
Preparation thickness is on substrate
Ground floor insulation course 3, material is silicon nitride (SiNx) or other insulating material, the preparation method can be PECVD or physics coating etc.On ground floor insulation course 3, use " 5mask " or " 4mask " technology to prepare TFT device and data line again, comprising: source-drain electrode 72 and data line 71.The data line width is 1 μ m-9 μ m.
With methods such as PECVD or physics coatings, preparation thickness is on substrate
Insulating protective layer 8, material are silicon nitride (SiNx) or are other insulating material.Use the technology of photoetching and the etching drain electrode connecting hole 111 of on source-drain electrode, increasing income respectively.Wherein, connecting hole 111 is driveed to source leakage metal level.Lithographic method can be dry etching or wet etching or mixed method.Concrete structure such as Figure 15 and shown in Figure 16.
Deposit thickness is
The transparent pixels electrode layer, material P-indium oxide tantalum (ITO), alpha-oxidation indium tantalum (ITO) or indium zinc oxide (IZO) or other electrically conducting transparent materials.The preparation method can be modes such as sputter, evaporation or physics coating.The method that re-uses photoetching and etching forms second layer pixel electrode layer 102 figures.Wherein: second layer pixel electrode layer 102 is connected with source-drain electrode 72, and having width on the electrode is 2 μ m-6 μ m openings (greater than the opening on the ground floor pixel), and the width that visuals is arranged is 3 μ m-8 μ m.Pixel electrode is staggered up and down.Concrete structure such as Figure 11 and shown in Figure 12.
In the above-mentioned manufacture method,, improved the controllability of technology, thereby improved the yield rate of product because gate metal is made as ground floor.
It should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can use different materials and equipment to realize it as required, promptly can make amendment or be equal to replacement, and not break away from the spirit and scope of technical solution of the present invention technical scheme of the present invention.
Claims (11)
1. a FFS pixel structure for thin film transistor liquid crystal display is characterized in that, comprising: a substrate, a grid line and data line; Described grid line and data line are formed on the described substrate; Described grid line and data line intersection definition one pixel cell, each pixel cell comprises film transistor device, public electrode, ground floor pixel electrode layer and second layer pixel electrode layer;
Wherein, separate by insulation course between described ground floor pixel electrode layer and the second layer pixel electrode layer; Described ground floor pixel electrode layer is connected with public electrode; Described second layer pixel electrode layer is connected with the source-drain electrode of thin film transistor (TFT); The figure of described ground floor pixel electrode layer and second layer pixel electrode layer is for being staggered.
2. dot structure according to claim 1 is characterized in that: described ground floor pixel electrode layer segment is formed directly on the described substrate; Part is overlapped on the public electrode and forms described ground floor pixel electrode layer and be connected with public electrode.
3. dot structure according to claim 1, it is characterized in that: described grid line and public electrode are positioned at on one deck, cover insulation course on it, described ground floor pixel electrode layer is formed on this insulation course top, connects by connecting line between described ground floor pixel electrode layer and the public electrode.
4. dot structure according to claim 3 is characterized in that: the material of described connecting line is identical with the material of described second layer pixel electrode layer.
5. according to the arbitrary described dot structure of claim 1 to 4, it is characterized in that: all be formed with opening on the figure of described ground floor pixel electrode layer and second layer pixel electrode layer, the figure A/F of wherein said ground floor pixel electrode layer is 1 μ m-5 μ m; The figure A/F of described second layer pixel electrode layer is 2 μ m-6 μ m.
6. the manufacture method of a FFS pixel structure for thin film transistor liquid crystal display is characterized in that, comprising:
Step 1, preparation grid line and gate electrode on substrate, and the figure of public electrode;
Step 2, preparation ground floor insulation course on the substrate of completing steps 1; Deposition ground floor pixel electrode layer forms ground floor pixel electrode layer pattern by photoetching and etching technics on the ground floor insulation course;
Step 3, preparation second layer insulation course, then preparation film transistor device and data line on second layer insulation course on the substrate of completing steps 2;
Step 4, on the substrate of completing steps 3, prepare insulating protective layer, technology by photoetching and etching forms the source-drain electrode connecting hole respectively at the source-drain electrode place, form public electrode and ground floor pixel electrode layer connecting hole at ground floor pixel electrode layer and public electrode intersection location; Wherein, the source-drain electrode connecting hole is driveed to the source and is leaked metal level, and public electrode and ground floor pixel electrode layer connecting hole are opened to public electrode and ground floor pixel electrode layer;
Step 5, deposition second layer pixel electrode layer on the substrate of completing steps 4, by photoetching and etching technics, form the connecting line of second layer pixel electrode layer pattern and public electrode and ground floor pixel electrode layer, wherein second layer pixel electrode layer is connected with source-drain electrode by the source-drain electrode connecting hole, and public electrode is connected by the connecting line of public electrode with the ground floor pixel electrode layer with the ground floor pixel electrode layer.
7. manufacture method dot structure according to claim 6 is characterized in that: the second layer pixel electrode layer pattern that forms in ground floor pixel electrode layer pattern that forms in the described step 2 and the step 5 is for being staggered.
8. manufacture method dot structure according to claim 6, it is characterized in that: all be formed with opening on the second layer pixel electrode layer pattern that forms in ground floor pixel electrode layer pattern that forms in the described step 2 and the step 5, wherein the figure A/F of the ground floor pixel electrode layer of Xing Chenging is 1 μ m-5 μ m; The figure A/F of the second layer pixel electrode layer that forms is 2 μ m-6 μ m.
9. the manufacture method of a FFS pixel structure for thin film transistor liquid crystal display is characterized in that, comprising:
Step 1, preparation grid line and gate electrode on substrate, and the figure of public electrode;
Step 2, deposition ground floor pixel electrode layer forms ground floor pixel electrode layer pattern by photoetching and etching technics on the substrate of completing steps 1, and ground floor pixel electrode layer visuals is overlapped on the public electrode;
Step 3, preparation ground floor insulation course, then preparation film transistor device and data line on the ground floor insulation course on the substrate of completing steps 2;
Step 4 prepares insulating protective layer on the substrate of completing steps 3, the technology by photoetching and etching forms the source-drain electrode connecting hole respectively at the source-drain electrode place, and wherein the source-drain electrode connecting hole is driveed and leaked metal level to the source;
Step 5, deposition second layer pixel electrode layer forms second layer pixel electrode layer pattern by photoetching and etching technics on the substrate of completing steps 4, and wherein second layer pixel electrode layer is connected with source-drain electrode by the source-drain electrode connecting hole.
10. manufacture method dot structure according to claim 9 is characterized in that: the second layer pixel electrode layer pattern that forms in ground floor pixel electrode layer pattern that forms in the described step 2 and the step 5 is for being staggered.
11. manufacture method dot structure according to claim 6, it is characterized in that: all be formed with opening on the second layer pixel electrode layer pattern that forms in ground floor pixel electrode layer pattern that forms in the described step 2 and the step 5, wherein the figure A/F of the ground floor pixel electrode layer of Xing Chenging is 1 μ m-5 μ m; The figure A/F of the second layer pixel electrode layer that forms is 2 μ m-6 μ m.
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| KR101125254B1 (en) * | 2004-12-31 | 2012-03-21 | 엘지디스플레이 주식회사 | Thin Film Transistor Substrate of Fringe Field Switching Type And Fabricating Method Thereof, Liquid Crystal Display Panel Using The Same And Fabricating Method Thereof |
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