CN101370208A - Method for implementing ubiquitous intelligent human-machine interaction chip based on personal identification - Google Patents
Method for implementing ubiquitous intelligent human-machine interaction chip based on personal identification Download PDFInfo
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Abstract
A method for realization of intelligent human-machine interactive chips based on identity identification is disclosed, which integrates information space composed of computation and communication chips and systems with physical space in which human being live to a harmony human-machine interactive information environment, self-organized human-machine interactive infrastructures and human-machine intelligent interaction methods established on this basis are realized using wireless sensor networks and distributive computing techniques, in order to improve performance and quality of the human-machine interaction. The invention provides a method for realizing transparent and intelligent interaction process between human-machine exchanges, which offers interactive service that can be communicated at any moment and can be interacted in time, and flexible information sharing methods.
Description
Technical field
The present invention relates to a kind of design and implementation method of wireless communication chips of short distance low-power consumption, belong to general fit calculation, the crossing domain of embedded system and radio communication.
Background technology
The developing history of man-machine interaction is to adapt to computer constantly adapts to the people to computer development history from the people, it has experienced several stages: handwork stage, graphic user interface (Graphical User Interface, the GUI) appearance at stage, network user interface, multichannel and multimedia intelligent human-machine interaction stage.
In the handwork stage in early days, mutual characteristics are to be used a computer by designer (or the colleague of this department), and they adopt the method for manual operations and dependence machine (binary system machine code) to deacclimatize to it seems it is very clumsy computer now.
In job control language and interactive command language stage, the main user (programmer) of computer can adopt the mode of batch processing job language or interactive command language and computer to come into contacts with, though remember many orders and kbhit expertly, but available more convenient means are come debugging routine, understand the computer implementation status.
Graphic user interface (Graphical User Interface, GUI) the stage main feature is desktop metaphor (Window/Icon/Menu/Pointing Device, WIMP), direct manipulation and What You See Is What You Get (What You See Is WhatYou Get, WYSIWYG), easily learn because GUI is simple and clear, reduced kbhit, realized actual standardization, thereby the domestic consumer that is ignorant of computer also can expertly be used, opened up user crowd, its appearance makes information industry obtain unprecedented development.
When the appearance at network user interface, with HTML (Hypertext Markup Language, HTML) and HTML (Hypertext Markup Language) (Hypertext Transfer Protocol, HTTP) for the web browser on main basis be characteristics that WWW net that the representative at network user interface is formed by it has become this class human-computer interaction technology of pillar of current Internet be development soon, new technology constantly occurs, as search engine, network acceleration, multimedia animation, chat tool etc.
In multichannel and multimedia intelligent human-machine interaction stage, being the personalizing and be microminiaturization, carry-onization, the embeddingization of the computer of representative with Hand Personal Computer, smart mobile phone of computer system of representative with the virtual reality, is two important development trends of current computer.And be that the GUI technology of representative is the bottleneck that influences their development with mouse and keyboard.Utilize people's polyesthesia passage and action channel (as inputs such as voice, hand-written, posture, sight line, expressions), carry out to improve the naturality and the high efficiency of man-machine interaction alternately with (visible or sightless) computer environment with parallel, non-accurate way.Multichannel and multimedia intelligent human-machine interaction are a challenge to us, also are fabulous opportunities, and the research in field of human-computer interaction has at present obtained a lot of progress.
Be in the intelligent human-machine interaction epoch, the present invention has aimed at sight general fit calculation and the wireless sensor network that is rising.The present invention is based on the thought of general fit calculation, made full use of the advantage of wireless sensor network, realized ubiquitous, do not rely on certain computer or particular system, have more the interactive mode of hommization.
Along with fast development of information technology, wireless sensor network is just becoming emerging research direction in the sensor field, and it is that a kind of brand-new information is obtained and treatment technology.Simultaneously, along with the maturation of wireless sensor network technology, general fit calculation also becomes a reality gradually. and by general fit calculation, people can obtain needed various information whenever and wherever possible.These The Application of Technology will be brought unprecedented facility to people's life.The present invention is as the research background.
As the hardware carrier of wireless sensor network platform, the design of wireless sensor chip need be followed microminiaturization, low-power consumption, numerous factors such as autgmentability is strong, and stability is high, and fail safe is good, and cost is low.Yet, as a kind of technology of emerging appearance, set up one run well, wireless sensor network that robustness is good still is faced with many challenges.And because its some unique properties, the method for designing of wireless sensor network and the method for designing of prior wireless network have a great difference.For example, because the sensor chip in the sensor network is densely distributed, so need large-scale data management and treatment technology.In addition, electrical source consumption also is a very important problem, and wireless sensor chip can only be equipped with limited power supply as micro devices, and under some application scenario, it is almost impossible changing power supply.This makes the life-span of sensor chip depend on the life-span of battery to a great extent, is the problem that the wireless sensor network design needs overriding concern so reduce power consumption with the life-span that prolongs system.
Summary of the invention
Technical problem: the objective of the invention is to propose under a kind of network environment implementation method based on the ubiquitous intelligent human-machine interaction chip of identification.This chip called after IDEA chip (IDEA refers to the connotation of " intelligence, innovative point ", therefore name).Final purpose is to develop high-performance, than the strongly-adaptive ability, under the network environment of high integrated level based on the ubiquitous intelligent human-machine interaction chip of identification.
Technical scheme: the invention provides under a kind of network environment implementation method based on the ubiquitous intelligent human-machine interaction chip of identification.This method makes up a kind of wireless sensor network hardware carrier of high-performance low-power-consumption, the general transfer of data of sensor network has not only been satisfied in the design of chip and realization on function, State Control, monitoring in real time, a series of functions such as autonomous location, simultaneously, aspect chip integration, large increase has been arranged, further reduced the energy consumption of chip, strengthened the autonomous stationkeeping ability of chip, improved the mode and the method for the self-performance monitoring and the self of chip, and can identify constant mark that each chip self had number by the information interaction of chip chamber.
Based on the implementation method of the ubiquitous intelligent human-machine interaction chip of identification, chip is made of the real-time perception external sense information and the device that can carry out sensing data transmission and control under a kind of network environment proposed by the invention.
Based on the ubiquitous intelligent human-machine interaction chip of identification, claim the IDEA chip again under the network environment.
The IDEA chip is divided into IDEA-Send chip (receiving chip) and two kinds of chips of IDEA-Receive chip (transmission chip).IDEA-Send chip apparatus has comprised the central primary control processing module, short distance high-frequency wireless communication module, bottom energy supply module; IDEA-Receive chip apparatus has comprised the central primary control processing module, short distance high-frequency wireless communication module, bottom energy supply module and external interface modular converter.Above-mentioned several module is called by SOC (system on a chip) software is organic, carries out
Sensing data transmits, information processing, condition monitoring, a series of activities such as control in real time.The module composition diagram of IDEA-Receive chip is shown in Fig. 1-1, and the module composition diagram of IDEA-Send chip is shown in Fig. 1-2.
Provide the explanation of several concrete parts below for the present invention:
The central primary control processing module: the central primary control processing module is the core of entire I DEA chip, be responsible for the Equipment Control of entire I DEA chip, Task Distribution and scheduling, a plurality of mission criticals such as the integration of data and dump, comprise the transmitting-receiving operation of control chip data and information and to transmitting-receiving speed, coded format, transmitting-receiving frequencies etc. control effectively; Data encryption and safety guarantee; The management of power consumption and control and mode switch etc.Among the present invention, adopted high integrated, low-power consumption, the 8-bit microprocessor of reduced instruction set computer has adopted advanced Harvard bussing technique, makes the processing speed of entire I DEA and accuracy greatly improve.Simultaneously, entire chip also has very strong extensibility, and a plurality of I/O interfaces are provided, and promptly helps the function expansion of chip, also lays the first stone for the exploitation of subsequent product.
Wireless communication module: short distance high-frequency wireless communication module mainly is responsible for the transmitting-receiving of wireless signal, promptly carries out radio communication with other IDEA chips, with this chip with information and other chips exchange.The present invention has used advanced event driven embedded OS, dispatches by message circulation and message between the chip and realizes accurately locating and establishing a communications link.In order to realize the high reliability of high-frequency transmission, low error rate, the radio frequency chip that meets the IEEE802.15.4 standard major part as communication module has been adopted in the requirement of high real-time and transmission range, the present invention.Between the working frequency range 300MHZ-1GHZ, and can pass through its inner register setting, adjust working frequency range flexibly, adaptability is strong.The working frequency range of IDEA chip design is 900MHZ, and can adjust accordingly according to actual conditions.Adopt the FSK modulation system, NRZ, Manchester, the optional coded system of UART is with the optional data transfer rate of 0.6Kbaud/s-76.8Kbaud/s.Module-external uses the SPI interface to link to each other with the central primary control processing module.
Serial ports on external interface modular converter: IDEA-Receive chip changes the mainly responsible information that chip is had of USB module and passes to computer by USB interface, and gives IDEA-Receive chip supply energy simultaneously.The present invention considers that traditional chip links to each other with computer by serial ports and realizes transfer of data, because many-sided restrictions such as equipment, caused a lot of unnecessary troubles to the user,, realized that chip is connected by USB interface with computer so utilize serial ports to change the USB chip.
Bottom energy supply module: bottom energy supply module provides operation needed whole energy for the IDEA chip.In the present invention, promptly can use outside JTAG (Joint Test Action Group) or USB (Universal Serial Bus) to power, also can use chip self power supply to carry out power supply and supply with.In the selection of self power supply, the present invention has adopted the lithium battery of small volume and less weight.
The step that implementation method comprised of IDEA chip is:
Step 1) planning required general function of finishing of IDEA chip and key property index: chip need be finished real-time data acquisition, monitoring in real time, signal processing, transfer of data, independently locate multiple function, requirement has high system reliability and high integration, real-time analysis preferably and disposal ability, the transfer of data accuracy, and possess the condition of work of long-time low energy consumption;
Step 2) determine the input and output of IDEA chip: the data that chip will send from other chip in the network are as input, will be by the determined unique chip identification of these data in user terminal displays as output;
The clear and definite chip data characteristic of step 3): chip signal is transmitted in the general high band of variable-frequency 300MHZ-1000MHZ, has a plurality of fixing frequencies.Frequency modulation(FM) can realize that adopt the adjustable data transmission rate of 0.6KBaud/s-76.8KBaud/s, internal data adopts parallel transmission pattern, Manchester's code by the value of programming change frequency word register;
The executive mode of step 4) chip and function realize: adopt the JTAG programmable device to carry out the in-circuit emulation and the debugging of chip program, provide serial ports, the parallel port downloading mode, chip has been downloaded after the application program, get final product executable operations, and under the control and supervision of terminal controlling platform, finish application task;
Step 5) is carried out the basic boom design of chip: the chip basic boom is made up of four levels, is respectively from bottom to top: functional part layer, device drive layer, embedded system kernel, application system level;
The description of step 6) chip design scheme: system adopts top-down method that the functional part of this chip is carried out Module Division, mainly comprises: central primary control processing module, user interface, high-frequency wireless communication module and energy supply module;
Step 7) design central primary control processing module: the central primary control processing module is carried out data communication and signal transmission by SPI communicator module with the high-frequency wireless communication module;
Step 8) design high-frequency wireless communication module: the high-frequency wireless communication module of chip has comprised low noise amplifier, frequency mixer, filter circuit, frequency divider, modulator-demodulator, phase discriminator, low pass filter, module is with heat transfer agent, mode with wireless frequency spectrum, on the frequency range of 300MHZ-1000MHZ, transmit, simultaneously, reception is from the heat transfer agent transmission of other chip in the self-organizing network, and in real time and base station ic link up;
Step 9) design energy supply module: the energy supply module provides energy resource supply for above-mentioned each module, and the four kinds of different working methods of transmission, reception, dormancy, standby at system provide corresponding energy resource supply mode;
Choosing of step 10) chip periphery device: according to the oneself requirement of chip own characteristic and wireless sensor network, the peripheral components of chip, realized as the function of organizing the chip in the wireless network certainly, but these devices comprise digitlization I/O device, external memory device, external crystal-controlled oscillation system, active antenna;
The circuit design of step 11) chip and realization: chip circuit adopts the digitlization standard design, and element all adopts the SMD encapsulation of 0603 type, has realized the conversion between TTL signal and the RS-232 signal between being connected of chip and PC serial ports; Main control chip has been set up the buffering between high speed signal and the low speed signal, and chip adopts the strategy of four laminates wiring, is undertaken by the mode that hand wired and self routing combine;
Interface design between the step 12) chip module: chip interface mainly is made up of three parts, is respectively series arrangement bus coupling part, bi-directional synchronization data-signal coupling part, and optional part of detecting;
The power supply design of step 13) chip: chip provides 4 kinds of variable mode of operations, is respectively sleep pattern, sending mode, receiving mode, battery saving mode, simultaneously, designed a kind of comparatively accurate power supply early warning mechanism, can finish real-time monitoring for self supply power voltage;
The power managed design of step 14) chip: the power managed of chip has mainly comprised the system level power consumption management, and the software code level is optimized, and register transfer optimization and rear end comprehensive wiring are optimized;
The design of the extensibility of step 15) chip: chip has been reserved sufficient interface in design process, comprises surpassing 30 main control module input/output interfaces, so that calling and expand from now on;
Step 16) chip reliability and anti-interference design: chip loads filter capacitor in HFS design, on IC and connect high frequency capacitance, adopts intensive wiring to reduce the high-frequency noise emission; Aspect the propagation path inhibition, chip design goes out to have the stabilized power supply of filter circuit, is isolated between I/O mouth and noise source, simultaneously, interference source is separated with Sensitive Apparatus;
Step 17) Design of System Software of chip: the harmonious operation of all real-time tasks of the system software controls of chip, system is according to mission requirements, carry out resource management, Message Processing, task scheduling, abnormality processing, and distribute priority, system is according to the priority of each task, dynamically switches and dispatches;
Step 18) software reliability of chip design: adopt digital filtering that suppresses superposition noise on signal path and the method that reduces redundant instruction in the chip design, adopt reduced instruction set;
Step 19) software debugging of chip: chip uses AVR Studio to carry out software debugging, allows the user to carry out emulation of AVR online in real time or simulation, simultaneously, chip is supported the wireless senser operating system platform of main flow, supports .hex .elf, .cof .ihex, many kinds of file formats of .srec;
Step 20) the system-Level software emulation of chip: chip adopts VMLAB to carry out system-Level software emulation, in the software emulation stage, by building of hardware and software platform, the virtual simulated environment of a chip actual motion, by simulated environment, function that can clear and definite chip realizes;
Step 21) the system-level simulation hardware of chip: chip uses the JTAG in-circuit emulator to finish simulation hardware, by firing platform, application program is fired in the chip, finishes application function;
Step 22) download of chip application program and execution: chip design uses JTAG to download, and JTAG downloads and mainly undertaken by JTAGICE.
Beneficial effect: existing interactive mode based on desktop depends on certain computer or particular system, being difficult to adapt to the user may use many computers to carry out the situation etc. of work at different location and environment, for this reason, research and realize under a kind of network environment ubiquitous intelligent human-machine interaction chip based on identification, helping reducing showing in information of man-machine interaction imports, ubiquitous with realizing, do not rely on certain computer or particular system and have more the intelligent human-machine interaction pattern of hommization, this chip can be applied in people's daily life and the work practically, makes people can obtain the special services that computer provides pellucidly under network environment.As the main implementor of identity recognition function and the supplier of the ubiquitous environment of user, the IDEA chip has been born most control, transmission and monitoring work.Have following advantages and useful achievement:
The higher system integrated level: owing to be subjected to the restriction of overall dimension as the IDEA chip of practical application, the critical component that processor module must integrated more chip is as sound attitude memory, ADC transducer, timer conter etc.The IDEA chip has adopted the high-performance of 8 risc architectures, the microprocessor of low-power consumption, and the integrated numerous external equipments that comprise above-mentioned parts have very strong extensibility.
Lower system capacity consumption: as the critical component of entire chip, the power consumption of processor is generally very big.And in wireless network, not having lasting energy resource supply, this just requires the design of chip to consider as a key factor energy-conservation.The energy of IDEA chip is supplied with the mode that has adopted external power source and base station power supply to combine, and provides to comprise idle pulley ADC noise reduction mode, power-down mode, battery saving mode, multiple power management such as standby mode.And can make chip in the whole service process, carry out the conversion of state on one's own initiative, thereby very reduce the energy consumption of chip effectively, prolong the useful life of chip.The energy consumption situation of each module of IDEA as shown in Figure 2.
The speed of service faster: because that wireless sensor network requires for the real-time of chip is very high, this ability that just needs processor real-time to handle is powerful.The bus structures that comprise processor inside, addressing system, the design of instruction pipeline etc. all need be as target.The processor adopting of IDEA program storage and data storage use the different memory spaces and the Harvard structure of ACCESS bus, instruction fetch and program are carried out and are carried out simultaneously, have saved expense greatly.Simultaneously, hardware multiplier only needs two clock cycle, and when working in 16MHz, performance can be up to 16MIPS.System ALU directly is connected with 32 general purpose working registers, and in a system clock cycle, ALU can finish the once-through operation operation.
External interface easily: traditional sensor chip generally is connected with computer by serial ports, and this does not have not have on Serial Port Line or the computer user of serial ports to bring a lot of inconvenience to some.Therefore the present invention has adopted USB interface on the IDEA that need link to each other with computer-Receive chip, makes that the use of chip is more convenient.
Lower hardware cost of manufacture: as the wireless device of networking, sensor chip should be dispersed throughout network everywhere, if single chip cost is too high, will inevitably influence the layout of whole networking.The major part of IDEA chip of the present invention adopts the doubling plate routing strategy, and overall routing is reasonable, and inner member has higher performance, makes the cost of manufacture of chip integral body reduce.
Description of drawings
Fig. 1-the 1st, the integral module composition diagram of IDEA-Receive chip is represented this chip system basic module composition.
Fig. 1-the 2nd, the integral module composition diagram of IDEA-Send chip is represented this chip system basic module composition.
Fig. 2 is the energy consumption situation comparison diagram of each module of IDEA, has shown power consumption situation and the contrast of forming each energy consumption part of the present invention.
Fig. 3 is the detailed structure division figure of IDEA chip.Modular structure that this chip is detailed and the conspiracy relation between the various piece have been represented.
Embodiment
IDEA chip embodiment:
IDEA chip of the present invention is the center with the central primary control processing module, the input of the output termination central primary control processing module of bottom energy supply module, short distance high-frequency wireless communication module and the two-way UNICOM of central primary control processing module, the input of the output termination external interface modular converter of central primary control module; Wherein, short distance high-frequency wireless communication module comprises radio frequency chip, exterior antenna, and the external interface modular converter comprises that serial ports changes USB chip, USB interface, and bottom energy supply module comprises JTAG power supply, external power source, USB interface power supply.
IDEA wireless sensor network hardware platform specific implementation and development procedure are:
(1) the present invention is carrying out on the deeply concrete basis of studying required general function of finishing of clear and definite sensor chip and basic performance index to the wireless sensor network field.At the demand of practical application, the IDEA chip need be finished real-time monitoring, signal processing, transfer of data, information fusion, early warning control, multiple functions such as the autonomous location of chip.In order to reach above-mentioned every basic function, the IDEA chip has had higher system reliability and integrated level, real-time analysis preferably and disposal ability, and accurate data is transmitted accuracy, and possesses the condition of work of long-time low energy consumption.
(2) clear and definite chip application the technical indicator that must reach.Chip is user's input and output controlled function flexibly of providing convenience, and the input of chip comprises that program fires, function selecting and terminal control, and the output of chip comprises data acquisition, information shows.Chip signal is transmitted in the general high band of variable-frequency 300MHZ-1000MHZ, and concrete working frequency points can realize by software.Adopt the adjustable data transmission rate of 0.6KBaud/s-76.8KBaud/s.Internal data adopts parallel transmission pattern, Manchester's code.For realizing function, chip adopts the JTAG programmable device to carry out the in-circuit emulation and the debugging of program, provides serial ports simultaneously, the programming mode of parallel port and USB mouth.Chip has been downloaded after the related application, can carry out associative operation, and under the control and supervision of terminal controlling platform, finishes application task.
(3) basic boom of chip design.
The basic boom of chip has been followed the fundamental mode of general embedded product, simultaneously, based on the needs of practical application, all expansions to some extent on each aspect.The chip basic boom is made up of four levels, is respectively from bottom to top: functional part layer, device drive layer, embedded system kernel, application system level.
A) functional part layer
The functional part layer is the underlying platform and the hardware foundation of entire chip.Comprised the set that all hardware modules of chip are formed and system bottom calls.Each composition module of chip is carried out comprehensive and co-ordination.Simultaneously, defined the bus unit of chip, interrupt system.
B) device drive layer
Device drive layer provides device driver functionality and strategy for the bottom physical unit.Sensor chip in the practical application need work under the various modes, and state exchange is frequent, and energy consumption control requires high.This layer effect is exactly the form with device driver module, and comprehensive scheduling is done in the parts operation of chip.
C) embedded system kernel
The embedded system kernel connects at equipment and between using, and the methods that provide software and hardware system to call provide the function service for upper layer application simultaneously.System kernel at the special requirement of sensor chip, has improved the interruption controls strategy, process scheduling strategy and memory management policy simultaneously based on the management and dispatching strategy of real time operating system.
D) application system level
Application system level provides application oriented system control mode and method of work for the terminal use.Finish the startup of chip, operation, state transition, data acquisition, information processing, signal transmission, energy consumption early warning, a series of application functions such as program download.
(4) carry out the description of chip design scheme.
Chip adopts top-down method, and the functional part of chip is carried out Module Division.Mainly comprise: central primary control processing module, user interface, high-frequency wireless communication module and energy supply module.
A) central primary control processing module:
The central primary control processing module of chip is the nucleus module of entire chip, carries out system's overall scheduling and carries out alternately with the user.Module is carried out data communication and signal transmission by SPI communicator module with the high-frequency wireless communication module.
B) user interface
User interface provides selection for the user, control and signal transmission form many services such as choose.Mutual by with the central primary control module realizes that user's multiple function needs.And the chip chamber information transmitted can be transferred to user terminal.
C) high-frequency wireless communication module
The high-frequency wireless communication module has comprised the low noise amplification, mixing, filtering, a plurality of operating procedures such as modulation are with heat transfer agent, in the mode of wireless frequency spectrum, on corresponding frequency range, transmit, simultaneously, receive heat transfer agent transmission from other chip in the self-organizing network, and the communication of real-time and base station ic.
D) energy supply module
The energy supply module provides energy resource supply for above-mentioned all modules, and four kinds of working methods at system provide corresponding energy resource supply mode.When the user is switched the operating state of chip, system will call corresponding energy supply mode automatically, make chip operation under corresponding pattern.
Division of the level of each module and mutual call relation are as shown in Figure 3 in the chip.
(5) general structure design of enforcement IDEA.According to the scale of chip and the complexity of hardware platform, adopted the structural design mode of sectional type.Chip integral body is divided according to function.Comprised microprocessor module, radio frequency transceiving module and power supply supplying module.In actual design process, corresponding integrated circuit (IC) system that each module is all corresponding, and finally be connected by system bus, finish the realization of the allomeric function of IDEA chip.
(6) following step is to carry out the design of the hardware configuration of chip.In practical operation, adopted the collaborative design technology of software and hardware concurrent development.Comprised several like this aspects and step in the hardware configuration design:
A) selection of microprocessor
Microprocessor is the system core parts of entire I DEA chip, has directly determined the function and the performance of entire chip.Simultaneously, the processor chips of different packing forms also can directly have influence on the physical size and the weight of chip.Therefore, in the selection of microprocessor, the present invention has mainly considered the factor of performance and two aspects of encapsulation.The IDEA chip adopted Atmel the advanced person 8 risc microcontrollers---ATmega128L is as the processor chips of chip.On the basis of AT90 series processors, increased the hardware multiplier of 2 clocks, and can be by the online programming certainly of the BOOT district realization program on the chip, have the IC interface of 2 lines and 8 tunnel 10 A/D converter, and increased JTAG emulation, download interface has improved the development efficiency of chip.
B) selection of peripheral components
The oneself requirement of the characteristics of chip self and wireless sensor network according to the present invention, the selection of peripheral components of the present invention has realized substantially as all functions of organizing the chip in the wireless network certainly.But these devices comprise digitlization I/O device, external memory device, A/D converter spare and other functional parts.
C) high integrated, high efficiency circuit design
In the circuit design of IDEA, demonstrated fully the viewpoint of soft or hard combination.In order to improve chip reliability and to prepare for subsequent development, the function that many use hardware can be finished in the chip also can be finished by software.The function that realizes hardware with software can reduce the hardware development circuit effectively, but the response time is longer than using the realization of hardware separately, and takies the execution of CPU, and the realization of algorithm is more complicated often.In chip development process of the present invention, taken into full account the comprehensive of software and hardware and be connected situation.
The present invention from integration module, to primary element, adopts typical device as far as possible in circuit design, promoted the standardization and the modularization of hardware system.Simultaneously, comprehensive planning the software and hardware resources of chip, in the process of developing, taken into full account the extensibility of chip, thereby helped the secondary development of chip.
Because the interface that has related between a series of different units circuit such as communication between base station ic and the PC is connected and transfer of data, the present invention taken into full account the compatibility of signal in these areas.Realized the conversion between TTL signal and the RS-232 signal between being connected of chip and PC serial ports; Therefore main control chip has also set up the buffering between high speed signal and the low speed signal owing to need to handle in real time and analyze from information that is distributed in each chip in the network and data.
D) Interface design of intermodule
Of the present invention two big basic module---the Interface design of wireless communication module and central primary control module mainly is made up of three parts.Be respectively series arrangement bus coupling part (being mainly used to be provided with and the mode of operation and the parameter setting that change wireless communication chips), bi-directional synchronization data-signal coupling part (being mainly used in data communication and message transmission), and optional part of detecting (being mainly used in chip monitoring operating state and test signal intensity).
E) computer-aided design of hardware platform
The present invention has adopted a series of comparatively advanced circuit CAD (Computer Aided Design, computer-aided design) softwares to carry out the design of system configuration and fairly large integrated circuit.Highly versatile, the development efficiency height.The main modular of chip has all adopted Protel99SE to finish the design and the drafting of hardware circuit.In view of the high-end components and parts of the part of this product do not have predefined packing forms, on stream, added definition, and be bundled in the middle of its encapsulation storehouse, so that expansion is used from now on for the encapsulation of these devices.Consider integration, antijamming capability, and the requirement of the every performance index of chip, the present invention has adopted the strategy of four laminates wirings, is undertaken by the mode that hand wired and self routing combine.
F) design of the power supply of chip and power managed
As the IDEA chip that intersperses among in the self-organizing network, it is very important that the saving of energy seems.In the present invention, power module need be given the central primary control module and the radio frequency transceiving module supply work energy needed on upper strata.Calculate through actual measurement, chip is in service non-energy saver mode, and the operating current of above-mentioned two modules can be up to 25mA.For the IDEA chip that most of the time employing internal electric source is supplied with, it is particularly important that the design of power supply and management seem.The present invention has taken into full account requirements of saving energy in the design and management of power supply, not only on software, for chip provides 4 kinds of variable mode of operations, simultaneously, adopted a considerable amount of low-loss systems components and parts.In the design of IDEA, a kind of comparatively accurate power supply early warning mechanism is provided, can have finished real-time monitoring, when voltage is lower than minimum threshold that chip operation allows and requires for self supply power voltage, IDEA can produce alarm mechanism, and makes chip switch to dormancy or standby mode rapidly.Power managed of the present invention has mainly comprised the system level power consumption management, and the software code level is optimized, register transfer optimization and rear end comprehensive wiring optimization etc.The system level power consumption management will make it to enter sleep state when IDEA does not operate, when Preset Time arrives, promptly produce and interrupt waking up; For the present invention, coding style and code efficiency are extremely important for SOC (system on a chip), and IDEA has adopted good coding style, and the code after the optimization greatly reduces power consumption; Aspect register transfer, the present invention has adopted hardware configuration optimization and the parallel optimisation strategy of system's pipeline processes, reduce the on-chip memory Module Division of register electric capacity simultaneously, reduce the signal gate of activity factor, reduce the propagation velocity of Glitch (burr) etc., the register transfer power consumption is greatly reduced with this; Aspect the comprehensive wiring of rear end, the present invention has adopted the optimization circuit, reduces operation, revises modes such as signal correction relation, has further reduced the generation probability of comprehensive burr.
G) extensibility of IDEA design
Increasingly mature along with the development of sensing technology and network technology, wireless sensor network technology from now on is inevitable towards diversification and intelligent direction development.Therefore, the present invention has reserved sufficient interface in design process, so that calling and expand from now on.
H) reliability design of hardware platform and interference free performance
IDEA chip in the practical application works in the various complex environments, when superior performance requires, also chip reliability has been proposed more and more higher requirement, particularly in the higher field of the real-time of Industry Control and communicating requirement.The present invention is from suppressing interference source, and many-sided reductions the such as antijamming capability of cutting off propagation path and raising sensitive components disturb, and improve the reliability of platform.The inhibition interference source that chip adopted
Measure has: HFS loads filter capacitor; IC is last and connect high frequency capacitance, and it is intensive short and small smoothly to reduce high-frequency noise emission etc. to connect up.Aspect the propagation path inhibition, the present invention has taken into full account the noise effect of power supply for SOC (system on a chip), design the stabilized power supply that has filter circuit, between I/O mouth and noise source, isolated equally, simultaneously, noted crystal oscillator wiring and ground connection, the circuit board rationalization partition separates interference source with Sensitive Apparatus.The present invention has carried out many-sided improvement for improving the antijamming capability of sensitive components, has comprised the area that reduces return rings, reduces the coupling noise, and the idle port of configuration uses Power Supply Monitoring and watchdog circuit, reduces crystal oscillator and uses low speed propagation etc.
What (7) carry out simultaneously with the hardware designs of chip is the software function design of chip.For the IDEA development platform, software design has mainly comprised the design of first floor system software.Systems soft ware of the present invention is based on RTOS (Real-TimeOperation System, real time operating system), timely response external event request, and finish processing at the appointed time.System controls the harmonious operation of all real-time tasks, has independence, reliability and real-time characteristics.System carries out resource management according to mission requirements, Message Processing, and task scheduling, work such as abnormality processing, and distribute priority, system can be according to the priority of each task, dynamically switches and dispatch.Because systems soft ware of the present invention is the embedded software based on SOC (system on a chip), therefore, not only will consider functional integrity and accuracy aspect program circuit, also to guarantee the normal of hardware initialization and running.In view of real-time of the present invention is had relatively high expectations, therefore occupy crucial status in the control of interrupt system and the design that is created in chip, system provides and has comprised soft interruption, hardware interrupts and nested interrupt are in interior multiple interrupt mode, adopted the dynamic real-time dispatching algorithm (to comprise the dull algorithm of speed simultaneously, the earliest deadline priority algorithm, minimum slack time priority algorithm).In order to make stable operation of the present invention, on the basis of improving hardware performance and reliability, also need to guarantee the reliability of software, so that entire chip stable operation is in operational environment.Software reliability design among the present invention has mainly comprised Anti-interference Design and fault-tolerant design.Design of Software Anti-interference is the householder method of hardware anti-interference design.Among the present invention, digital filtering that suppresses superposition noise on signal path and the method that reduces redundant instruction have been used.Digital filtering has multiple mode, and chip has used the weighted average filter method, promptly to target parameter sampling N time, and each sampled value be multiply by one less than 1 weight coefficient, the sampled value after the weighting is added up as this sampled value again.The weight coefficient of each sampled value is all inequality, with outstanding several times sample effect after this, strengthens the recognition capability of chip to parameter variation tendency.
(8) after the collaborative design of having finished software and hardware, need utilize existing hardware and software development instrument, carry out functional part level and system-level emulation and debugging.So both helped finding out the problem that chip exists, the also further clear and definite operational process and the textural association of chip.The present invention has mainly adopted software debugging in this stage, three processes of software systems emulation and hardware system emulation.
(9) finished the artificial debugging of software and hardware after, just system program can have been downloaded among the IDEA.The present invention is mainly the user provides JTAG downloading mode JTAG download mainly to be undertaken by JTAGICE.Do not need extra device promptly can realize the download execution of file destination.
Claims (1)
1. implementation method based on the ubiquitous intelligent human-machine interaction chip of identification is characterized in that realizing that the step that is comprised is:
Step 1) planning required general function of finishing of IDEA chip and key property index: chip need be finished transfer of data, information fusion, early warning control, independently locate multiple function, requirement has higher system reliability and integrated level, accurate data is transmitted accuracy, and possesses the condition of work of long-time low energy consumption;
Step 2) determine the input and output of IDEA chip: the data that chip will send from other chip in the network are as input, with the sensing result transmission to user terminal as output;
Clear and definite chip signal type of step 3) and data characteristic: based on the needs of HF communication, chip signal is transmitted in the general high band of variable-frequency 300MHZ-1000MHZ, concrete modulator approach can realize by the value of programming change frequency word register, adopt the adjustable data transmission rate of 0.6KBaud/s-76.8KBaud/s, internal data adopts parallel transmission pattern, Manchester's code;
The executive mode of step 4) chip and function realize: adopt the JTAG programmable device to carry out the in-circuit emulation and the debugging of chip program, serial ports programming mode and USB downloading mode are provided simultaneously, chip has been downloaded after the application program, get final product executable operations, and under the control and supervision of terminal controlling platform, finish application task;
Step 5) is carried out the basic boom design of chip: the chip basic boom is made up of four levels, is respectively from bottom to top: functional part layer, device drive layer, embedded system kernel, application system level;
Step 6) is launched the description of chip design scheme: chip adopts top-down method that the functional part of this chip is carried out Module Division, mainly comprises: central primary control processing module, user interface, high-frequency wireless communication module, external interface modular converter and energy supply module;
Step 7) design central primary control processing module: the central primary control processing module is by SPI communicator module, carry out data communication and signal transmission with the high-frequency wireless communication module, simultaneously, utilize A/D conversion submodule, the various heat transfer agents that the information sensing module is collected are converted into the form of the signal of telecommunication, and be transferred to the user interface of handling as master control, thereby realize the demonstration of quantitative and qualitative heat transfer agent by the asynchronous serial submodule;
Step 8) design high-frequency wireless communication module: the high-frequency wireless communication module of chip has comprised low noise amplifier, frequency mixer, filter circuit, frequency divider, modulator-demodulator, phase discriminator, low pass filter, module is with heat transfer agent, mode with wireless frequency spectrum, on the frequency range of 300MHZ-1000MHZ, transmit, simultaneously, reception is from the heat transfer agent transmission of other chip in the self-organizing network, and in real time and base station ic link up;
Step 9) is established the external interface modular converter: the external interface modular converter has comprised that serial ports changes USB chip and USB interface two parts.Information is changeed the USB chip by serial ports and is converted to the USB transmission from the serial ports transmission, and carries out information interaction by USB interface and user terminal.
Step 10) design energy supply module: the energy supply module provides energy resource supply for above-mentioned each module, four kinds of different working methods of transmission, reception, dormancy, standby at chip, corresponding energy resource supply mode is provided, when the user is switched the operating state of chip, chip will call corresponding energy supply mode automatically, make chip operation under corresponding pattern;
Choosing of step 11) chip periphery device: according to the characteristics of chip self and the oneself requirement of wireless sensor network, the selection of the peripheral components of chip, substantially realized as all functions of organizing the chip in the wireless network certainly, but these devices comprise digitlization I/O device, external memory device, A/D converter spare, external crystal-controlled oscillation system, active antenna;
The circuit design of step 12) chip and realization: chip circuit adopts the digitlization standard design, and element all adopts the SMD encapsulation of 0805 type, has realized the conversion between TTL signal and the RS-232 signal between being connected of chip and PC serial ports; Main control chip has been set up the buffering between high speed signal and the low speed signal, and chip adopts the strategy of doubling plate wiring, is undertaken by the mode that hand wired and self routing combine;
Interface design between the step 13) chip module: chip interface mainly is made up of three parts, is respectively series arrangement bus coupling part, bi-directional synchronization data-signal coupling part, and optional part of detecting;
The power supply design of step 14) chip: chip provides 4 kinds of variable mode of operations, is respectively sleep pattern, sending mode, receiving mode, battery saving mode, simultaneously, designed a kind of comparatively accurate power supply early warning mechanism, can finish real-time monitoring for self supply power voltage;
The power managed design of step 15) chip: the power managed of chip has mainly comprised the system level power consumption management, and the software code level is optimized, and register transfer optimization and rear end comprehensive wiring are optimized;
Step 16) extensibility of chip design: chip has been reserved sufficient interface in design process, comprises surpassing 30 main control module input/output interfaces, so that calling and expand from now on;
Step 17) chip reliability and anti-interference design: the high-frequency suppressing aspect, chip loads filter capacitor in HFS design, on IC and connect high frequency capacitance, adopts intensive wiring to reduce the high-frequency noise emission; Aspect the propagation path inhibition, chip design goes out to have the stabilized power supply of filter circuit, is isolated between I/O mouth and noise source, simultaneously, interference source is separated with Sensitive Apparatus;
Step 18) Design of System Software of chip: the harmonious operation of all real-time tasks of the system software controls of chip, system is according to mission requirements, carry out resource management, Message Processing, task scheduling, abnormality processing, and distribute priority, system is according to the priority of each task, dynamically switches and dispatches;
Step 19) software reliability of chip design: adopt digital filtering that suppresses superposition noise on signal path and the method that reduces redundant instruction in the chip design, adopt reduced instruction set;
Step 20) software debugging of chip: chip uses AVR Studio to carry out software debugging, allow the user to carry out emulation of AVR online in real time or simulation, before carrying out emulation, but use third party's compiler that source file is compiled as the .cof file of emulation .elf file or .hex file;
Step 21) the system-Level software emulation of chip: chip adopts VMLAB to carry out system-Level software emulation, in the software emulation stage, by building of hardware and software platform, the virtual simulated environment of a chip actual motion, by simulated environment, function that can clear and definite chip realizes;
Step 22) the system-level simulation hardware of chip: chip uses the JTAG in-circuit emulator to finish simulation hardware, by firing platform, application program is fired in the chip, finishes application function;
Step 23) download of chip application program and execution: chip design 2 kinds of downloading modes, be respectively that USBISP downloads and JTAG downloads, the JTAG download is mainly undertaken by JTAGICE.
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| CN102026227A (en) * | 2010-12-14 | 2011-04-20 | 广州市香港科大霍英东研究院 | Distributed deployment method for large-scale wireless sensor network testing and debugging |
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| CN115292237A (en) * | 2022-10-09 | 2022-11-04 | 中科声龙科技发展（北京）有限公司 | Chip and data transmission method thereof |
| CN115292237B (en) * | 2022-10-09 | 2022-12-20 | 中科声龙科技发展（北京）有限公司 | Chip and data transmission method thereof |
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