CN101369237B - Watchdog reset circuit and reset method - Google Patents
Watchdog reset circuit and reset method Download PDFInfo
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- CN101369237B CN101369237B CN2007101296741A CN200710129674A CN101369237B CN 101369237 B CN101369237 B CN 101369237B CN 2007101296741 A CN2007101296741 A CN 2007101296741A CN 200710129674 A CN200710129674 A CN 200710129674A CN 101369237 B CN101369237 B CN 101369237B
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- watchdog
- cpu
- clocking capability
- programming device
- reset signal
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Abstract
The invention discloses a watchdog reset circuit and a reset method thereof, which can guarantee normal operation of the watchdog circuit during the upgrade of programmable device. The watchdog reset circuit includes a CPU, a watchdog module and a programmable device connected in series, and at least one component with timing function; the component and the programmable device are arranged in parallel, a reset signal is output to a reset signal port of the watchdog module, the component receives the bus signal of the CPU, timing is started when the programmable device is under upgrading, if the CPU halts during the time of timing, the component outputs the reset signal to the watchdog module when the timing times out, and the watchdog module outputs a power-up reset signal to the CPU and restarts the CPU.
Description
Technical field
The present invention relates to electronic data processing field (G06) and electric communication technique field (H04), particularly a kind of watchdog reset circuit and repositioning method.
Background technology
At present, on the most of veneers on the base station chips such as CPU, house dog, EPLD are arranged all.Wherein CPU is the brain of veneer management maintenance, and EPLD then serves as address decoding, sheet choosing and the functions such as distributing and cooperate house dog that resets.The version of EPLD realizes that at veneer the back is disposable burned.The watchdog circuit implementation of veneer is various, expands and feeds the dog time but overall thought all is CPU by EPLD, has prolonged the watchdog chip duration that resets.Yet along with the continuous increase of EPLD chip capacity, the function that EPLD finishes is more and more, and in order to improve design flexibility, but a lot of veneer all requires EPLD online upgrading version when design, thereby reduces the design risk that disposable burned version brings.At this moment just produce a problem, EPLD is all IO pin three-states in upgraded version, that is to say that watchdog circuit is ineffective this moment, the problem that watchdog circuit can't work when therefore being badly in need of a kind of circuit or method with solution EPLD upgraded version.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of watchdog reset circuit and repositioning method, to guarantee the operate as normal of watchdog circuit during the programming device upgrading.
In order to solve the problems of the technologies described above, the invention provides a kind of watchdog reset circuit, comprise the CPU that is connected in series, watchdog module, programming device, described programming device is used to cooperate watchdog module to realize the veneer watchdog function, play the effect of expansion time-delay, comprise that also at least one has the element of clocking capability, described element and described programming device are arranged in parallel, the output reset signal is to the reset signal port of described watchdog module, described element receives the bus signals of CPU, when upgrading, described programming device picks up counting, if CPU crashes in the timing time, then described element at timing time then to watchdog module output reset signal, restarts CPU by described watchdog module to CPU output power-on reset signal.
Further, after described programming device and described reset signal with element of clocking capability are passed through the logical and module, output to the reset signal port of watchdog module.
Further, the reset signal port at described watchdog module is provided with a manual switch.
Further, described timing time with element of clocking capability is the update time of the programming device of expectation.
Further, described element with clocking capability is programmable logic device (PLD) or the processor with clocking capability.
Further, when adopting the programmable logic device (PLD) conduct to have the clocking capability element, described programmable logic device (PLD) adopts one of following device: the electrically programmable logical device is that EPLD, CPLD are that CPLD, field programmable gate array are FPGA; When adopting the processor conduct to have the clocking capability element, described processor adopting digital signal processor DSP.
In order to solve the problems of the technologies described above, the present invention also provides a kind of watchdog reset method, programming device is used to cooperate watchdog module to realize the veneer watchdog function, play the effect of expansion time-delay, when CPU judges that programming device need be upgraded, the element that notice has clocking capability picks up counting, and upgrading programming device, if CPU crashes before described element timing arrives, then described element is when timing arrives, to watchdog module output reset signal, watchdog module restarts CPU to CPU output power-on reset signal.
Further, described timing time with element of clocking capability is the update time of the programming device of expectation.
Further, described element with clocking capability is programmable logic device (PLD) or the processor with clocking capability.
Further, when adopting the programmable logic device (PLD) conduct to have the clocking capability element, described programmable logic device (PLD) adopts one of following device: the electrically programmable logical device is that EPLD, CPLD are that CPLD, field programmable gate array are FPGA; When adopting the processor conduct to have the clocking capability element, described processor adopting digital signal processor DSP.
The inventive method is applicable to most digital communication veneers.Adopt circuit of the present invention and method, can guarantee watchdog circuit operate as normal during the programming device upgrading, watchdog circuit is more flexible, and the reset function of system is more reliable.The logical and module is finished the logical and function of two programming device output signals among the present invention, thereby makes two programming devices can finish the cpu function that resets.Dirigibility of the present invention is that the logical and module can be discrete logical AND gate, also can be the chip pin logic line with.Dirigibility of the present invention is that also programming device two also can be other devices such as signal processor, as long as CPU can visit and have clocking capability.
Description of drawings
Fig. 1 is a watchdog reset circuit structural representation of the present invention;
Fig. 2 is embodiment of the invention watchdog reset circuit synoptic diagram in the TD-SCDMA system;
Fig. 3 is the watchdog circuit of the present invention process flow diagram that resets;
Fig. 4 is embodiment of the invention watchdog circuit in TD-SCDMA system process flow diagram that resets.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
As shown in Figure 1, the present invention is for realizing that watchdog circuit during the programming device upgrading is still in the watchdog reset circuit of operate as normal, be provided with plural programming device, newly-increased programming device two is to serve as interim house dog during programming device one upgraded version, be the another one house dog, therefore also watchdog circuit provided by the invention can be considered as a kind of many watchdog reset circuits.Fig. 1 has shown the situation that two programming devices are arranged, and many watchdog circuits comprise with lower module:
The CPU processor is connected with programming device by bus, and receives the power-on reset signal (Power_Reset) that watchdog circuit sends;
Programming device one is used to cooperate watchdog chip to realize the veneer watchdog function, plays the effect of expansion time-delay;
Watchdog chip, its house dog input end (WDI) links to each other with programming device one with house dog output terminal (WDO), when having level in the regular hour, the WDI pin do not change, WDO can export a negative pulse, when hand-reset signal (Manu_Reset) when negative pulse occurring, the reset pulse (Powreset signal) that watchdog chip will produce certain width outputs to CPU;
Except using special watchdog chip, other modules that can realize watchdog function all can.
Programming device two when programming device one upgrading, is provided with timing, and at timing then, the output negative pulse triggers cpu reset by watchdog chip to Manu_Reset;
Timing can be set as required, is generally the update time of the programming device of expectation.Except adopting programming device (as electrically programmable logical device EPLD, complex programmable logic device (CPLD), on-site programmable gate array FPGA etc.), also can adopt processor to realize, as digital signal processor DSP, in a word, as long as there is the element of clocking capability all can realize.
Logical and module log1, the reset signal of reception programming device one and programming device two is through behind the logic and operation, to watchdog chip output Manu_Reset.
Utilize circuit of the present invention, many watchdog reset circuits of in the TD-SCDMA system, realizing, as shown in Figure 2.In the present embodiment, watchdog chip adopts 706; Programming device has been selected EPLD (CPLD) and FPGA (field programmable gate array) for use, and wherein EPLD is as cooperate the programmable logic device (PLD) one that realizes watchdog function with watchdog chip; In addition, between the input of the output of logical AND gate and watchdog chip, increased a manual reset switch Switch, sent hand-reset signal (Manu_Reset) to watchdog chip, with convenient when the practical application, hand-reset CPU.The signal that watchdog chip receives EPLD and/or FPGA sends power-on reset signal to CPU, perhaps by the reset switch hand-reset.
Fig. 3 is the process flow diagram that the present invention realizes many watchdog resets, may further comprise the steps:
Whether CPU can be set to regularly detect programming device one needs upgrading.
The version of step 340, CPU upgrading programming device one;
If step 350 CPU in programming device two timings crashes, forward step 370 to, otherwise jump to step 360;
After CPU notice programming device two programming devices one load successfully in step 360, and in the step 390, after CPU started successfully, CPU can continue to use programming device one as watchdog circuit, and subsequent treatment and the present invention are irrelevant.
For the timer of programming device two, when cpu reset, can close the timer of programming device two by reset signal, if CPU does not reset, then can after the success of CPU loading programmable device one redaction, close this timer, this prescribing method has a variety of.
In the TD-SCDMA system, adopt flow process that said method realizes many house dogs as shown in Figure 4, programming device has been selected EPLD and FPGA for use, and the timer timing was an example with 5 seconds, and step is as follows:
Step 410, CPU normally move, the watchdog circuit operate as normal;
Step 420, judge EPLD whether need the upgrading, if jump to step 430, otherwise jump to step 410;
Step 430, CPU notice FPGA opening timing function, countdown begins for 5 seconds;
Step 440, CPU upgrading EPLD version;
If step 450 is the success of CPU upgrading EPLD version in timing, execution in step 460 jumps to step 470 if CPU crashes;
Step 460, CPU notice FPGA programming device one EPLD version load successfully, and clocking capability is closed, and returns step 410;
Step 470, FPGA timing in 5 second end, output cpu reset pulse signal;
Step 480, CPU restart;
Step 490, CPU start successfully, return step 410;
Though describe embodiments of the invention in detail in conjunction with the above-mentioned application of diagrammatic sketch, but this is not a practical application unique method of the present invention, for those skilled in the art, still can modify and do not change the spirit and scope of the invention above-mentioned embodiment.
Claims (10)
1. watchdog reset circuit, comprise the CPU that is connected in series, watchdog module, programming device, described programming device is used to cooperate watchdog module to realize the veneer watchdog function, play the effect of expansion time-delay, it is characterized in that, comprise that also at least one has the element of clocking capability, described element and described programming device are arranged in parallel, the output reset signal is to the reset signal port of described watchdog module, described element receives the bus signals of CPU, when upgrading, described programming device picks up counting, if CPU crashes in the timing time, then described element at timing time then to watchdog module output reset signal, restarts CPU by described watchdog module to CPU output power-on reset signal.
2. circuit as claimed in claim 1 is characterized in that, after described programming device and described reset signal with element of clocking capability are passed through the logical and module, outputs to the reset signal port of watchdog module.
3. circuit as claimed in claim 1 or 2 is characterized in that, at the reset signal port of described watchdog module one manual switch is set.
4. circuit as claimed in claim 1 or 2 is characterized in that, described timing time with element of clocking capability is the update time of the programming device of expectation.
5. circuit as claimed in claim 1 or 2 is characterized in that, described element with clocking capability is programmable logic device (PLD) or the processor with clocking capability.
6. circuit as claimed in claim 5 is characterized in that,
When adopting the programmable logic device (PLD) conduct to have the clocking capability element, described programmable logic device (PLD) adopts one of following device: the electrically programmable logical device is that EPLD, CPLD are that CPLD, field programmable gate array are FPGA;
When adopting the processor conduct to have the clocking capability element, described processor adopting digital signal processor DSP.
7. watchdog reset method, programming device is used to cooperate watchdog module to realize the veneer watchdog function, play the effect of expansion time-delay, it is characterized in that, when CPU judges that programming device need be upgraded, the element that notice has clocking capability picks up counting, and upgrading programming device, if CPU crashes before described element timing arrives, then described element is when timing arrives, to watchdog module output reset signal, watchdog module restarts CPU to CPU output power-on reset signal.
8. method as claimed in claim 7 is characterized in that, described timing time with element of clocking capability is the update time of the programming device of expectation.
9. method as claimed in claim 8 is characterized in that, described element with clocking capability is programmable logic device (PLD) or the processor with clocking capability.
10. method as claimed in claim 9 is characterized in that,
When adopting the programmable logic device (PLD) conduct to have the clocking capability element, described programmable logic device (PLD) adopts one of following device: the electrically programmable logical device is that EPLD, CPLD are that CPLD, field programmable gate array are FPGA;
When adopting the processor conduct to have the clocking capability element, described processor adopting digital signal processor DSP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101296741A CN101369237B (en) | 2007-08-14 | 2007-08-14 | Watchdog reset circuit and reset method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101296741A CN101369237B (en) | 2007-08-14 | 2007-08-14 | Watchdog reset circuit and reset method |
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| CN101369237A CN101369237A (en) | 2009-02-18 |
| CN101369237B true CN101369237B (en) | 2011-01-05 |
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| CN2007101296741A Active CN101369237B (en) | 2007-08-14 | 2007-08-14 | Watchdog reset circuit and reset method |
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Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996129B (en) * | 2009-08-17 | 2013-01-02 | 英业达股份有限公司 | Method for detecting computer system crash |
| CN102169451B (en) * | 2011-04-26 | 2016-01-20 | 中兴通讯股份有限公司 | The method and apparatus that a kind of monitoring CPU is run |
| CN102508533B (en) * | 2011-09-21 | 2014-07-09 | 迈普通信技术股份有限公司 | Reset control device and method |
| CN102768501A (en) * | 2012-08-02 | 2012-11-07 | 广西电网公司电力科学研究院 | Automatic rebooting machine for personal computer (PC) with monitoring unit |
| CN104281479B (en) * | 2014-10-31 | 2019-01-08 | 深圳市大疆创新科技有限公司 | A kind of firmware upgrade method and device |
| CN104750567B (en) * | 2015-03-26 | 2017-11-17 | 南京大全自动化科技有限公司 | A kind of watchdog reset method based on FPGA |
| CN105159698B (en) * | 2015-07-14 | 2019-05-21 | 江苏欧帝电子科技有限公司 | A kind of flexible system crash monitoring system and its operating method |
| CN105656638B (en) * | 2015-12-30 | 2019-03-15 | 东莞市义仁汽车租赁有限公司 | One kind, which automatically powers off, restarts control equipment and control method |
| CN105929811B (en) * | 2016-04-06 | 2018-11-20 | 清华大学 | A kind of protection circuit for program deadlock |
| CN107133119A (en) * | 2017-05-02 | 2017-09-05 | 郑州云海信息技术有限公司 | A kind of method that hardware watchdog function is realized by CPLD |
| CN107229495A (en) * | 2017-05-25 | 2017-10-03 | 沃太能源南通有限公司 | A kind of system and method for preventing EMS remote upgrade from failing |
| CN109032822B (en) * | 2017-06-09 | 2024-01-09 | 中兴通讯股份有限公司 | Method and device for storing crash information |
| CN108319352B (en) * | 2017-12-17 | 2021-03-05 | 天津津航计算技术研究所 | Reset time self-adaptive reset detection circuit |
| CN110134549B (en) * | 2019-05-09 | 2023-04-14 | 中国航空工业集团公司西安航空计算技术研究所 | FPGA reloading circuit |
| CN113110966A (en) * | 2021-03-12 | 2021-07-13 | 广东纳睿雷达科技股份有限公司 | System upgrade monitoring management method, embedded system and storage medium |
| CN113961059A (en) * | 2021-09-08 | 2022-01-21 | 北京国科天迅科技有限公司 | Reset method and circuit of communication equipment, electronic equipment and storage medium |
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| CN101369237A (en) | 2009-02-18 |
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Effective date of registration: 20141218 Address after: 200122 Shanghai City, Pudong New Area source deep road, No. 1122 Patentee after: State Grid Shanghai Municipal Electric Power Company Address before: 518057 Nanshan District high tech Industrial Park, Guangdong, South Road, science and technology, ZTE building, legal department Patentee before: ZTE Corporation |