CN101364802A

CN101364802A - Bur generating method for test apparatus

Info

Publication number: CN101364802A
Application number: CNA2007101199775A
Authority: CN
Inventors: 欧阳秋笙; 李丹
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2007-08-06
Filing date: 2007-08-06
Publication date: 2009-02-11

Abstract

The invention provides a burr generation method in test equipment. The method supports to generate burrs with a programmable width and a programmable extent. The circuit principle comprises a logic burr addition circuit (10) and a burr control logic circuit (40), wherein the logic burr addition circuit (10) is used for superposing a controllable logic burr signal on a stable signal under the control of the burr control logic circuit (40); a logic level conversion circuit (20) for converting a signal level with the logic burr into a signal level acceptable by a subsequent simulation burr generation circuit (30); and the simulation burr generation circuit (30) for converting the logic signal with the burr after conversion of the circuit (20) into a simulation burr signal under the control of the burr control logic circuit (40). The burr generation method is particularly characterized in that the circuit section for forming the burrs at last is achieved by using the switch property of an electronic device so as to ensure the abruptness of the changing edge of the burr; and the adjustments of the burr pulse width and the voltage amplitude are achieved in different circuit periods. The burr generation method suits estimation of burr interference resistance of a device to be tested in the test field, in particular to test estimation in the presence of an extremely narrow burr.

Description

Burr generation method in a kind of testing equipment

Technical field

The present invention relates to the burr generation technique in the Electronic Testing field.

Background technology

In Electronic Design, generally to manage to avoid the generation of burr in the circuit.But in some testing equipments,, need artificial structure width and the controllable burr of amplitude in circuit sometimes in order to test the influence of burr to electronic devices and components.General function signal generator equipment does not provide such function or is difficult to be incorporated in the concrete test circuit, and this just requires a kind of method of giving a concrete signal adding burr in physical circuit.

Single digital to analog converter (DAC) and the out drive stage structure (Fig. 1) thereof of the normal employing of conventional method, its realization dependence microcontroller (MCU) etc. carries out timing controlled, and by certain hour relation to DAC output signal voltage value to be made up, thereby obtain desired burr waveform.Because the method needs the long waveform reconstruction time (Fig. 2) when using the DAC conversion, be difficult to realize that width and amplitude all meet the requirements of extremely narrow burr.

In the research and development of some testing equipments, brought into use FPGA (Field Programmable Gate Array) as its logic control nuclear, thereby be easy to increase on this basis as required some extra control logics.The present invention adopts a kind of simple new method to solve foregoing problems on the basis of the hardware cost that does not increase extra control logic.

Summary of the invention

The present invention is intended to for the burr generation technique in the electronic test equipment provides a new method, and the invention provides a kind of burr change in voltage along the burr generative circuit precipitous, that the width adjusting scope is big.

Adopt the circuit structure of this method to comprise: a logic burr adds circuit and a burr control logic circuit, in order to logic burr signal that width is controlled of stack on signal, the logic burr signal here is meant the logical zero signal (negative logic burr) of stack certain width on the logical one signal, or, the logical one signal (positive logic burr) of stack certain width on the logical zero signal; A logic level translation circuit is transformed to the receptible logic level of buffer stage in order to the logic level that control logic is produced; A buffering output stage, the logical signal that will have burr is converted to the variable analog signal of spur amplitude.

More particularly, the burr control logic circuit comprises burr formation logic, signal formation logic, switch control logic, and logic level translation circuit and the buffer stage adjustable voltage power generation circuit that need use.This power circuit adopts redundant method to use many covers, and its magnitude of voltage is preset by main control end MCU or microprocessor (MPU) before burr produces.

The present invention is applicable in the testing equipment assessment to the anti-interference of tested device.The simulation burr signal that its key is a formation switching rate height, amplitude is adjustable.Adopt default burr output voltage values of a plurality of DAC and the numeral mode of cut-offfing to realize that level changes the abruptness on edge.Based on the mode of operation of MCU and logic control nuclear, then realized the width and the amplitude controllability of burr signal.

Description of drawings

The burr generation method figure that Fig. 1 is traditional

Fig. 2 negative voltage burr oscillogram

Fig. 3 system architecture diagram

Fig. 4 burr control logic and logic burr add schematic diagram

Conversion of Fig. 5 logic level and simulation burr generative circuit block diagram

Fig. 6 DAC out drive stage (Vo end) circuit diagram

Fig. 7 DAC out drive stage (Vg end) circuit diagram

Fig. 8 logic-level voltages conversion figure

The controlled selector switch that Fig. 9 relay is realized

Description of reference numerals:

The inner DC power supply voltage (9V) of V9

Vo burr high level voltage value

Vg negative voltage burr channel voltage value

GND system reference ground voltage

Vs selects Vg or GND value by switching logic

The rise time of Tr voltage buffer integrated circuit (IC) chip

T _fThe fall time of voltage buffer integrated circuit (IC) chip

t _gThe duration of burr

The inner DC power supply voltage (5V) of V5

NPN NPN type transistor

Embodiment:

Further specify the preferred embodiments of the present invention below with reference to Figure of description.The present invention is not limited to following the disclosed embodiments, and it can be the various changes and modifications at the embodiment of different application.

For the sake of simplicity, preferred embodiment is only discussed the generation circuit of negative voltage burr.

1) generation (Fig. 4) of the signal of the controlled band negative logic burr of width.When not starting the burr generation, burr width counter is not worked, and its value remains 0, and everybody (32 bit wide) is output as 1 through NOR gate burr width counter.When starting burr and generate, burr width counter just begins counting because everybody of counting beginning back burr width counter is not 0 entirely, this moment burr width counter everybody is output as 0 through NOR gate.When Counter Value is burr width register value, be reset to 0 by comparator output reset enable signal burr width counter, NOR gate is output as 1.Therefore, NOR gate output signal and the signal that normally is in the logical one state with, just become the signal of band negative logic burr.The duration t of NOR gate output logic 0 signal _gFor the clock cycle be multiply by burr width register value.Therefore, just can obtain the signal of the controlled negative logic burr of width by the size that burr width register value is set.

The count enable position of burr control register is used to start the work of burr width counter, and with the switch control bit go to select buffer stage " " current potential.

Burr width register and burr control register are read and write by the control logic data/address bus by the MCU program.

2) generation of the controlled simulation burr signal of amplitude.The generative circuit (Fig. 5) of the simulation burr signal that amplitude is controlled comprises the generation, logic-level voltages conversion of Vo and Vg voltage source, three parts of generation of simulation burr signal.

3) generation of Vo and Vg voltage source (Fig. 6, Fig. 7).The meaning of Vo and Vg voltage source and effect are referring to Fig. 2.Its production process is that MCU controls DAC by port output, DAC driving output stage 50 and output stage 51 acquisition Vo and Vg.Drive output stage and adopt improved amplifier in-phase proportion amplifying circuit, and power with direct voltage source V9 (9V).

Because the power supply of the driving output stage 51 of Vg and the simulation burr generative circuit 30 of back level " " during the generation burr, require direct current to be connected, in order not change the voltage characteristic of circuit, Vg drives output stage 51 (Fig. 7) does not have employing to be similar to the driving triode that is used for the electric current amplification in the Vo driving output stage 50 (Fig. 6).

According to the thinking of burr of the present invention structure, Vo and Vg voltage source are finished by DAC is default by the MCU program before burr produces, and therefore, the variation of burr is along steepness and do not rely on the conversion speed of DAC.

4) logic-level voltages conversion (Fig. 8)." reference power source " of simulation burr generative circuit is Vo, and its " with reference to ground " Vs is Vg or GND.In order to satisfy the voltage request of simulation burr generative circuit, requirement will have the in addition conversion of logic signal levels voltage of logic burr.BUF among Fig. 8 is used for logic high and logic low voltage are transformed to Vo and Gnd value respectively; The effect of diode D1 and resistance R is that when the D1 anode was input as high level Vo, it was (Vo-0.7) V that negative terminal is output as high level; When the D1 anode was input as low level 0, D1 ended, and its negative terminal output level is Vs.High-low level voltage after the conversion satisfies the late-class circuit requirement.

5) generation of simulation burr signal.Simulation burr signal generative circuit 30 can adopt the voltage buffer integrated circuit (IC) chip, and its power end is connected to Vo, and its ground end Vs then connects respectively with reference to ground or Vg by a controlled selector switch 32 (referring to Fig. 5).

Controlled selector switch 32 moves under the control of burr control logic.Switch driving circuit 33 (Fig. 5) is the grounded emitter circuit that NPN transistor constitutes, and is used to drive the controlled selector switch 32 that relay is realized.Fig. 9 is the detailed annexation of controlled selector switch 32 and switch driving circuit 33.Wherein, switch common port 31 is the reference ground Vs end of voltage buffer integrated circuit (IC) chip.

Similarly, thinking according to burr structure of the present invention, the selector switch of simulation burr voltage follower circuit ground end Vs has been preset by MCU program and control logic before burr produces and has been finished, and therefore, the variation of burr is along steepness and do not rely on the conversion speed of selector switch.

In fact, the variation of burr along the rise time Tr of steepness and voltage buffer integrated circuit (IC) chip and fall time Tf closely related.

6) based on the burr generative process of MCU and control logic.At first, the burr width register is set, and the bottom of trench voltage amplitude Vg of negative burr is set by the MCU firmware program; Then, the switch control bit that the burr control register is set by the MCU firmware program with the voltage buffer integrated circuit (IC) chip " " the controlled selector switch 32 (Fig. 5) of end 31 (Vs) dials to burr low-voltage end Vg; At last, the burr signal start bit that the burr control register is set by the MCU firmware program starts control logics such as burr width counter and generates burr.Finished by the burr control logic except the width control of burr signal, whole burr generative process is by the MCU program control.

Before burr generates, the voltage buffer integrated circuit (IC) chip " " hold 31 pins to receive ground.When burr generates, with the conversion chip " " end 31 pins move the value of setting to, after burr generates again with the conversion chip " " end 31 pins receive ground again.Before and after burr generated, circuit all was operated in normal condition.

Claims

1. the burr generation method in the testing equipment is characterized in that this method from generating the controlled logic burr signal of width in logic, and the logic burr signal obtains the controlled simulation burr signal of amplitude by logic level conversion and simulation burr generative circuit.

2. the burr generation method in a kind of testing equipment as claimed in claim 1 is characterized in that its burr control logic module ties up to logic burr signal that width is controlled of stack on the holding wire with the multiple pass of clock cycle.

3. the burr generation method in a kind of testing equipment as claimed in claim 1 is characterized in that its logic level translation circuit is by the signal level that must seek survival the back level to discern.

4. the burr generation method in a kind of testing equipment as claimed in claim 1 is characterized in that its simulation burr generative circuit is by the controlled analog signal of the amplitude of must seeking survival into.

5. the burr generation method in a kind of testing equipment as claimed in claim 1 is characterized in that its simulation burr generative circuit adopts the buffer stage circuit to realize.

6. the burr generation method in a kind of testing equipment as claimed in claim 5, it is characterized in that buffer stage " power supply " and " " DAC that drives output stage by a band respectively provides.

7. the burr generation method in a kind of testing equipment as claimed in claim 5 is characterized in that buffer stage comprises a relay.

8. the burr generation method in a kind of testing equipment as claimed in claim 5 is characterized in that buffer stage comprises a single-pole double-throw switch (SPDT) or similar device.

9. the burr generation method in a kind of testing equipment as claimed in claim 5 is characterized in that buffer stage comprises the protective circuit that a diode and resistance constitute.