CN101364567B - Preparation of nano-scale phase-changing memory cell array - Google Patents
Preparation of nano-scale phase-changing memory cell array Download PDFInfo
- Publication number
- CN101364567B CN101364567B CN2007100446099A CN200710044609A CN101364567B CN 101364567 B CN101364567 B CN 101364567B CN 2007100446099 A CN2007100446099 A CN 2007100446099A CN 200710044609 A CN200710044609 A CN 200710044609A CN 101364567 B CN101364567 B CN 101364567B
- Authority
- CN
- China
- Prior art keywords
- array
- multistage
- memory cell
- shrinkage pool
- tower
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention relates to a preparation method of a nanometer phase change memory cell array, and belongs to the technical field of micro-/nano- electronics. The preparation method is characterized by the following steps: preparing an inverted cone-shaped nanometer phase change memory cell multistep concave hole array, wherein the conical tip is in a nanometer scale; and filling the inverted cone with a specific phase-change material, a transition material and an electrode material, so as to obtain the nanometer phase change memory cell array. The preparation method can effectively reduce the contact area of the phase-change material and the electrode material, and smartly replace the commonly used double-exposure etching process in the prior art with one-exposure etching process, thereby resulting in a simple process. The method simplifies the preparation process of the nanometer multilayer cell structure, solves the etching problem of the nanometer phase change memory cell multilayer structure, and has the advantages of high processing precision, low cost, applicability to industrial production, and suitability for preparation of low-power and high-density phase change memory devices.
Description
Technical field
The present invention relates to a kind of preparation of nano-scale phase-changing memory cell array, belong to the micro-nano person in electronics.
Technical background
Phase transition storage (PCRAM) is the novel memory device that a kind of characteristic of utilizing phase-change material to have different resistance values under amorphous and polycrystalline two states realizes signal storage, it is little that PCRAM has a volume, driving voltage is low, power consumption is little, read or write speed is fast, non-volatile characteristics, with flash memory (FLASH) commonly used at present, dynamic random access memory (DRAM) and iron spot memory (FeRAM) are compared, competitive advantage is obvious, has high-low temperature resistant simultaneously, radioresistance, the characteristic of anti-vibration, therefore, PCRAM will have broad application prospects at civil area or in the national defence field, become the research and development focus.
Yet the subject matter that phase transition storage research and development at present face is exactly how further to reduce its operating current, reduce operating current help reducing power consumption and with present CMOS technology coupling.
To this, industry has proposed by reducing the multiple scheme that electrode points and phase-change memory cell structure reduce operating current, but the preparation method mainly adopts traditional photoetching technique, complex process, processing cost height.A kind of short-cut method that The present invention be directed to the nano-scale phase-changing memory cell array preparation and propose has the outstanding advantage that technology is simple, processing cost is low.This processing method is suitable for the industrialization of phase change memory device to be produced in batches, has substantive distinguishing features and obvious improvement at nanoscale sandwich construction manufacture field.
Summary of the invention
The object of the invention is to propose a kind of preparation of nano-scale phase-changing memory cell array, to satisfy the needs of phase change memory device nanoscale memory cell preparation.Process nano-scale phase-changing material array structure in this way, one-shot forming is repeatedly filled, both can guarantee that phase-change material contacted with nanoscale between the electrode, avoided complicated alignment process again, have that technology is easy, machining accuracy is high, the advantage of with low cost, array structure high conformity, good reproducibility, particularly important for the high-density phase-change memory spare preparation that performance and exposure parameter are in close relations.
Preparation process of the present invention is as follows: at first design " tower " the multistage shrinkage pool array of type nano-scale phase-changing memory cell, and this multistage shrinkage pool array is defined on the transparent solid-state panel according to concavo-convex opposite regular correspondence, on solid-state panel, form the multistage boss array of " tower " type; Depositing insulating material, metal material, transition material, insulating material then, be coated with the multilayer film substrate surface of figure transfer medium, disposable being defined on the figure transfer dielectric layer of the multistage boss array on the solid-state panel formed " tower " multistage shrinkage pool array of type by the stamp method; Then by etching will this multistage shrinkage pool array transfer to again be positioned at above the transition material layer with the figure transfer dielectric layer below insulation material layer on, on the insulation material layer on the transition material layer once property produce the multistage shrinkage pool array of nano-scale phase-changing memory cell, and can reuse repeatedly moulding; Fill certain thickness phase-change material, transition material, metal material successively for the multistage shrinkage pool on the insulation material layer above the transition material layer by the multilayer film depositing operation at last, thereby obtain required nano-scale phase-changing memory cell array.
Concrete preparation process of the present invention is:
(1) the multistage shrinkage pool array of structures design of " tower " type nano-scale phase-changing memory cell: on the transition material layer of lower electrode surface, cover one deck insulating material, thickness must be more than the total height 2nm greater than multistage boss structure, and whole " tower " multistage shrinkage pool array of structures of type is embedded in (Fig. 1) in the insulation material layer fully.Described " tower " type is meant and contains two-layer or two-layer above handstand pyramidal structure that each layer all is cylinder or conical structure in the tower.Wherein cat head one deck is a cone shape, floor height 20nm～200nm, and the vertex of a cone directly links to each other with transition material, and vertex of a cone end area is at 1～3000nm
2Between, awl bottom area is at 100nm
2More than; A floor height 100nm～1000nm at the bottom of the tower, the bottom end area is at 400nm
2More than; When described " fall tower " type structure comprises two-layerly when above, the intermediate layer height increases to the bottom cross-sectional area gradually from the top layer of tower between 20nm～1000nm, and promptly the contact face area last layer of adjacent two layers is less than or equal to time one deck in the tower.The disposable machine-shaping of the many ledge structures of described nanoscale.
(2) described multistage shrinkage pool array is defined on the transparent solid-state panel according to concavo-convex opposite regular correspondence, on solid-state panel, forms the multistage boss array of " tower " type (Fig. 2).Described correspondence is meant that solid-state panel convex platform part is concavo-convex opposite with the multistage shrinkage pool memory cell structure of designed nanoscale shrinkage pool part.The saturating ultraviolet light of this solid-state panel material, the surface smoothness error is no more than 10nm, thickness between 200 μ m～20mm, material be in quartz glass or polydimethylsiloxanepolymer polymer (PDMS) or the polymethyl methacrylate (PMMA) any one.Multistage boss array is that any one little processing method is defined on the transparent solid-state panel in shifting by electron beam lithography method, focused-ion-beam lithography method, electron beam exposure, optical lithographic methods, x ray method, master mold.Doing finishing on the solid-state panel construction that defines handles to reduce surface energy.Coating material is the F based compound, and method of modifying is that dressing agent vapour deposition or liquid phase are soaked or centrifugal spin coating.
(3) " tower " the multistage shrinkage pool array of type disposal molding.At substrate surface deposition of insulative material successively, metal material, transition material, insulating material, apply the figure transfer medium, disposable being defined on the figure transfer dielectric layer of the multistage boss structure on the solid-state panel formed " tower " multistage shrinkage pool array of type (Fig. 3) by the stamp method; Then should transfer to (Fig. 4) on the insulation material layer again by multistage shrinkage pool array by the etching transfer method, must guarantee cat head is etched on the transition material layer, once property is produced the multistage shrinkage pool array of nano-scale phase-changing memory cell on insulation material layer, and can repeat stamp repeatedly.Described figure transfer thickness of dielectric layers and following insulating material layer thickness thereof must be greater than total height 2nm of the multistage boss structure on the solid-state panel.Described insulating material is that SIO2, SIN (x) or other have a kind of in the compound of insulation function, metal material is a kind of among Al, W, Ti, Pt, Ag, Au, the Cu, described transition material has heating function, transition material is any one in TiN, Cr or the Cr compound, and insulating material, metal material, transition material and phase-change material film forming thickness are all in 2nm～500 mu m ranges.Described figure transfer dielectric material be one or both and the above combination in the ultraviolet light photosensitive polymer or mix after the ultraviolet light photosensitive polymer in one or both and above combination.
(4) the multilayer film deposition is filled and is formed phase-change memory cell structure, at first adopting multistage shrinkage pool sediment phase change material, the bed thickness of sputtering method on the good insulation material layer of etching is 10nm～500nm (Fig. 5), sputter is thick then is the transition material layer (Fig. 6) of 5nm～100nm, and last sputter is thick to be the top electrode metal material layer (Fig. 7) of 10nm～1000nm.Thereby obtain required nano-scale phase-changing memory cell array.Described phase-change material is any one in GeSbTe base or SiSbTe base or SbTe base or GeTe base or the GeSb base in the chalcogenide compound, transition material is any one in TiN, Cr or the Cr compound, and metal material is any one among Al, W, Ti, Pt, Ag, Au, the Cu.
Description of drawings
Fig. 1 " tower " the multistage shrinkage pool array of structures of type nano-scale phase-changing memory cell schematic diagram
The multistage boss array of " tower " type schematic diagram that defines on the solid-state panel of Fig. 2
Fig. 3 " fall tower " multistage shrinkage pool structure of type moulding process schematic diagram once on the figure transfer layer
Fig. 4 " tower " multistage shrinkage pool structure of type is transferred to the structural representation on the insulation material layer again
Fig. 5 " tower " multistage shrinkage pool structure of type has been filled the structural representation behind the phase-change material
Fig. 6 " tower " multistage shrinkage pool structure of type has been filled the structural representation behind the transition material
The phase-change memory cell structure array schematic diagram that obtains behind Fig. 7 " tower " the multistage shrinkage pool structure of type top electrode
Among the figure:
Embodiment
Further illustrate substantive distinguishing features of the present invention and obvious improvement below by specific embodiment.But limit the present invention by no means, the present invention also only is confined to embodiment by no means.
Embodiment one:
Preparation nanoscale Si2Sb2Te5 phase-change memory cell, the contact area that makes phase-change material and electrode material is less than 10nm2.
By method provided by the invention, concrete steps are:
(1) the multistage shrinkage pool array of structures design of " tower " type nano-scale phase-changing memory cell: on transition material (TiN) layer on bottom electrode (Ti) surface, cover one deck insulating material (SIN (x)), thickness 200nm, three layers of " tower " multistage shrinkage pool array of structures of type are embedded in (Fig. 1) in the insulation material layer fully.Wherein cat head one deck is a cone shape, floor height 20nm, and the vertex of a cone directly links to each other with transition material, vertex of a cone end area 6nm2, awl bottom area 100nm2; Bottom and intermediate layer are the cylinder bodily form, a floor height 120nm, end area 400nm2 at the bottom of the tower; Middle floor height 50nm, end area 200nm2.
(2) multistage shrinkage pool array is defined on the transparent quartz glass by electron beam lithography method correspondence according to concavo-convex opposite rule, forms the multistage boss array of " tower " type (Fig. 2).Surface smoothness error 6nm, thickness 1mm carries out vapour deposition with the CF3CH2CH2SiCl3 counter plate and modifies.Cat head one deck is a cone in the multistage boss array of " tower " type, floor height 20nm, vertex of a cone end area 6nm2, awl bottom area 100nm2; Bottom and intermediate layer are the cylinder bodily form, a floor height 120nm, end area 400nm2 at the bottom of the tower; Middle floor height 50nm, end area 200nm2.
(3) " tower " the multistage shrinkage pool array of type disposal molding.At the substrate surface that deposits insulating material (SIN (x)), bottom electrode metal material (Ti), transition material (TiN) successively, the insulating material SIN (x) of sputter one deck 200nm, cover one deck Germany AMO AMONIL-ms450 of company ultraviolet photoresist as the figure transfer medium with centrifugal spin-coating method, thick is 200nm, be defined on the figure transfer dielectric layer the multistage boss structure on the quartz glass is disposable by the UV imprint method, form " fall tower " multistage shrinkage pool array of type (Fig. 3); Then should transfer to (Fig. 4) on the insulation material layer again by multistage shrinkage pool array by the etching transfer method, must guarantee cat head is etched on the transition material layer, so just on insulation material layer once property produce the multistage shrinkage pool array of nano-scale phase-changing memory cell, and can repeat the stamp repeatedly.
(4) the multilayer film deposition is filled and is formed phase-change memory cell structure, at first adopting multistage shrinkage pool sediment phase change material Si2Sb2Te5, the bed thickness of sputtering method on good insulating material SIN (x) layer of etching is 20nm (Fig. 5), sputter is thick then is the transition material TiN layer (Fig. 6) of 5nm, and last sputter is thick to be the top electrode metal material Ti layer (Fig. 7) of 180nm.Thereby obtain required nano-scale phase-changing memory cell array, wherein phase-change material Si2Sb2Te5 and transition material TiN contact area are 6nm2.
The foregoing description will help to understand the present invention, but not limit content of the present invention.
Claims (4)
1. preparation of nano-scale phase-changing memory cell array is characterized in that structural design and disposal molding:
(1) at first designs " tower " multistage shrinkage pool array of type nano-scale phase-changing memory cell, and this multistage shrinkage pool array is defined on the transparent solid-state panel according to concavo-convex opposite regular correspondence, on solid-state panel, form the multistage boss array of " tower " type; Described " tower " type is meant and contains two-layer or two-layer above handstand pyramidal structure that each layer all is cylinder or conical structure in the tower; Wherein cat head one deck is a cone shape, floor height 20nm～200nm, and the vertex of a cone directly links to each other with transition material, and vertex of a cone end area is at 1～3000nm
2Between, awl bottom area is at 100nm
2More than; A floor height 100nm～1000nm at the bottom of the tower, the bottom area is at 400nm
2More than; Increase gradually to the bottom cross-sectional area from the top layer of tower, promptly the contact face area last layer of adjacent two layers is less than or equal to one deck down in the tower; When described " fall tower " type structure comprises two-layerly when above, the intermediate layer height is between 20nm～1000nm;
(2) depositing insulating material, metal material, transition material, insulating material then, be coated with the multilayer film substrate surface of figure transfer medium, disposable being defined on the figure transfer dielectric layer of the multistage boss array on the solid-state panel formed " tower " multistage shrinkage pool array of type by the stamp method; Then by etching will this multistage shrinkage pool array transfer to again be positioned at above the transition material layer with the figure transfer dielectric layer below insulation material layer on, on the insulation material layer on the transition material layer once property produce the multistage shrinkage pool array of nano-scale phase-changing memory cell, and can reuse repeatedly moulding;
(3) fill certain thickness phase-change material, transition material, metal material successively for the multistage shrinkage pool on the insulation material layer above the transition material layer by the multilayer film depositing operation at last, thereby obtain required nano-scale phase-changing memory cell array.
2. by the described preparation of nano-scale phase-changing memory cell array of claim 1, it is characterized in that this multistage shrinkage pool array is defined on the transparent solid-state panel according to concavo-convex opposite regular correspondence, form the multistage boss array of " tower " type on solid-state panel, described correspondence is meant that solid-state panel convex platform part is concavo-convex opposite with the multistage shrinkage pool memory cell structure of designed nanoscale shrinkage pool part; The saturating ultraviolet light of this solid-state panel material, the surface smoothness error is no more than 10nm, thickness between 200 μ m～20mm, material be in quartz glass or polydimethylsiloxanepolymer polymer (PDMS) or the polymethyl methacrylate (PMMA) any one; Multistage boss array is that any one little processing method is defined on the transparent solid-state panel in shifting by electron beam lithography method, focused-ion-beam lithography method, electron beam exposure, optical lithographic methods, x ray method, master mold; Doing finishing on the solid-state panel construction that defines handles to reduce surface energy.
3. by the described preparation of nano-scale phase-changing memory cell array of claim 1, it is characterized in that described " tower " the multistage shrinkage pool array of type disposal molding, substrate surface is deposition of insulative material, metal material, transition material, insulating material successively, apply the figure transfer medium, disposable being defined on the figure transfer dielectric layer upper strata of the multistage boss structure on the solid-state panel formed " tower " multistage shrinkage pool array of type by the stamp method; Then by etching method will this multistage shrinkage pool array transfer to again be positioned at above the transition material layer with the figure transfer dielectric layer below insulation material layer on, must guarantee to etch on the transition material layer, on the insulation material layer on the transition material layer once property produce the multistage shrinkage pool array of nano-scale phase-changing memory cell, and can repeat the stamp repeatedly; Described figure transfer thickness of dielectric layers and following insulating material layer thickness thereof must be greater than total height 2nm of the multistage boss structure on the solid-state panel; Described insulating material is SIO
2, SIN
(x)Or other has a kind of in the compound of insulation function; Metal material is a kind of among Al, W, Ti, Pt, Ag, Au, the Cu; Described transition material has heating function, and transition material is any one in TiN or other N compound or Cr or the Cr compound; Insulating material, metal material, transition material and phase-change material film forming thickness are all in 2nm～500 mu m ranges; Described figure transfer dielectric material be one or both and the above combination in the ultraviolet light photosensitive polymer or mix after the ultraviolet light photosensitive polymer in one or both and above combination.
4. by the described preparation of nano-scale phase-changing memory cell array of claim 1, it is characterized in that multilayer film deposition fill process, at first adopting multistage shrinkage pool sediment phase change material, the bed thickness of sputtering method on the good insulation material layer of etching is 10nm～500nm, sputter is thick then is the transition material layer of 5nm～100nm, and last sputter is thick to be the metal material layer of 10nm～1000nm; Thereby obtain required nano-scale phase-changing memory cell array; Described phase-change material is any one in GeSbTe base or SiSbTe base or SbTe base or GeTe base or the GeSb base in the chalcogenide compound, and transition material is any one in TiN or other N compound or Cr or the Cr compound; Metal material is any one among Al, W, Ti, Pt, Ag, Au, the Cu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100446099A CN101364567B (en) | 2007-08-06 | 2007-08-06 | Preparation of nano-scale phase-changing memory cell array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100446099A CN101364567B (en) | 2007-08-06 | 2007-08-06 | Preparation of nano-scale phase-changing memory cell array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101364567A CN101364567A (en) | 2009-02-11 |
| CN101364567B true CN101364567B (en) | 2011-09-14 |
Family
ID=40390847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100446099A Expired - Fee Related CN101364567B (en) | 2007-08-06 | 2007-08-06 | Preparation of nano-scale phase-changing memory cell array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101364567B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112635666B (en) * | 2020-12-22 | 2023-05-12 | 华中科技大学 | Phase change memory cell |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1556550A (en) * | 2004-01-09 | 2004-12-22 | 中国科学院上海微系统与信息技术研究 | Preparation method of phase storage unit device |
| US20060192193A1 (en) * | 2005-02-25 | 2006-08-31 | Samsung Electronics Co., Ltd. | Phase-change RAM and method for fabricating the same |
| CN1971964A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Vacuum cell thermal isolation for a phase change memory device |
-
2007
- 2007-08-06 CN CN2007100446099A patent/CN101364567B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1556550A (en) * | 2004-01-09 | 2004-12-22 | 中国科学院上海微系统与信息技术研究 | Preparation method of phase storage unit device |
| US20060192193A1 (en) * | 2005-02-25 | 2006-08-31 | Samsung Electronics Co., Ltd. | Phase-change RAM and method for fabricating the same |
| CN1971964A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Vacuum cell thermal isolation for a phase change memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101364567A (en) | 2009-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103078057B (en) | Organic solar batteries and preparation method thereof | |
| US11678495B2 (en) | Three-dimensional stacked phase change memory and preparation method thereof | |
| CN101335328B (en) | Phase-change memory device unit construction and manufacturing method thereof | |
| TWI335033B (en) | Laser beam directed pattern formation for disc stamper creation | |
| US9276202B2 (en) | Phase-change storage unit containing TiSiN material layer and method for preparing the same | |
| WO2021003904A1 (en) | Phase change memory and manufacturing method thereof | |
| CN106030406A (en) | Methods for uniform imprint pattern transfer of sub-20 nm features | |
| CN1693182A (en) | Deep submicron three-dimensional rolling mould and its mfg. method | |
| Liu et al. | Universal memory based on phase-change materials: From phase-change random access memory to optoelectronic hybrid storage | |
| CN101364567B (en) | Preparation of nano-scale phase-changing memory cell array | |
| CN103000807B (en) | Titanium-antimony-tellurium phase-changing material depositing method and preparation method of phase-changing storage unit | |
| CN103187523A (en) | Semiconductor device and manufacturing method thereof | |
| CN101051185B (en) | Photoetching positioning self-assembly filling method | |
| CN107111200A (en) | Conductive support for electrochromic device, the electrochromic device and its autofrettage for including the conductive support | |
| CN101364564A (en) | Preparation of large-area high-density phase-variant material array | |
| CN103531710B (en) | A kind of high-speed low-power-consumption phase change memory unit and preparation method thereof | |
| CN102487123B (en) | Nanoscale non-volatile resistive random access memory unit and preparation method thereof | |
| CN100379047C (en) | Method for producing nano phase transition storage unit | |
| CN101546728A (en) | Preparation method for nano level columnar phase change memory cell array | |
| CN1588613A (en) | Process for preparing nano phase change storage device unit | |
| CN101483220A (en) | Process for preparing phase-change memory | |
| CN101567421A (en) | Prismatical phase transition material nano-array and preparation method thereof | |
| CN203871379U (en) | Phase transition memory and heating electrodes thereof | |
| CN104051623B (en) | The preparation method of multidigit high integration vertical stratification memorizer | |
| CN101494196B (en) | Method for preparing low-voltage, low power consumption, high-density phase-change memory cell array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170911 Address after: 201203 Shanghai city Pudong New Area Keyuan Road No. 1278 3 floor Co-patentee after: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences Patentee after: Shanghai Industrial Institute for Research and Technology Address before: 200237 Shanghai Xuhui District City Jia Chuan Road No. 245 Building No. 3 on the third floor Co-patentee before: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences Patentee before: Shanghai Nanotechnology Promotion Center |
|
| TR01 | Transfer of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110914 Termination date: 20180806 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |