CN101358880A - Infrared focal plane read-out circuit and output stage structure thereof - Google Patents
Infrared focal plane read-out circuit and output stage structure thereof Download PDFInfo
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- CN101358880A CN101358880A CNA2008101197581A CN200810119758A CN101358880A CN 101358880 A CN101358880 A CN 101358880A CN A2008101197581 A CNA2008101197581 A CN A2008101197581A CN 200810119758 A CN200810119758 A CN 200810119758A CN 101358880 A CN101358880 A CN 101358880A
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Abstract
The invention relates to an output level structure of an infrared focal plane playback circuit, comprising a row output level which comprises N row amplifiers used for reading each row pixel signal; an output buffer level which is used for outputting the signal of the row output level in serial; N first switches which connect each row of amplifiers with the input end of the output buffer level; N second switches which connect the output end of the output buffer level with the positive input end of each row of amplifiers; wherein, the first switch and the second switch are controlled and conducted by row chosen signals which read the circuit, thus realizing that the signal is outputted in serial through the output buffer level. The invention also discloses a playback circuit which adopts the output level structure. In the output level structure and the applied infrared focal plane output circuit of the invention, the row amplifier and the whole structure of the output buffer level form a unit plus connection, thus the reading efficiency of the signal is improved greatly, and simultaneously the structure of the playback circuit is simplified and the power dissipation is reduced.
Description
Technical field
The present invention relates to the infrared imagery technique field, relate in particular to a kind of infrared focal plane read-out circuit and output stage structure thereof.
Background technology
Infrared imaging system has important use in fields such as military affairs, industrial or agricultural, medical science, astronomy at present.As the infrared focal plane array of infrared imagery technique core, comprise infrared detector array and sensing circuit two parts.The effect of detector array is to realize opto-electronic conversion, and the effect of sensing circuit then is to finish the processing of picture element signal and read.Wherein, sensing circuit has material impact to the performance of infrared imaging system.In recent years, along with CMOS (ComplementaryMetal-Oxide Semiconductor, complementary matal-oxide semiconductor) development of technology, extensive CMOS infrared focal plane read-out circuit has replaced CCD (Charge CoupledDevice, charge-coupled image sensor) becomes the infrared reading circuit main flow.
Typical face battle array infrared focal plane read-out circuit comprises that pixel is read array 11, row are read level 12, output buffer stage 13 and row, column control signal and produced logical one 4,15 as shown in Figure 1 in the prior art.Wherein, pixel is read the interface that array 11 is detector and sensing circuit, finishes functions such as the reception of detector biasing, photocurrent and integration; Row are read the operational amplifier that level 12 is generally the unity gain connection, finish the processing of row photocurrent integrated signal separately; Output buffer stage 13 also is the operational amplifier of unity gain connection generally, finishes the final output to signal; Usually row are read level 12 and are adopted one-level amplifier structure, and therefore output buffer stage 13 adopts two-layer configuration usually owing to need the driving resistor load.
Sensing circuit is according to first integration, after the sequential working read.Be pixel read array 11 with the behavior unit sequence to the photocurrent integration, after delegation's integration finishes, under the control of column selection signal, the integrated signal of every row successively by row read the level 12 and output buffer stage 13 read.In the column signal readout, the next line pixel begins integration.The picture element signal output speed of circuit is by the restriction of the readout delay of every column signal.The readout delay of every column signal can be estimated by following formula:
T
delay≈T
slew+T
col_amp+T
buffer
Wherein, T
SlewBe large-signal Time Created, usually by a large-signal long decision of Time Created in column amplifier and the output buffer stage.T
Col_ampAnd T
BufferRepresent the small-signal Time Created of column amplifier and output buffer stage respectively, they are determined by gain bandwidth product separately.In order to guarantee that signal accurately exports, each row cycle must be greater than the readout delay of column signal.
In recent years, the infrared focal plane array scale constantly enlarges, and maximum is to 4096 * 4096 scales.Because the pixel that every two field picture comprises increases, under the fast constant condition of frame, the rate requirement that sensing circuit is read pixel is more and more higher.Though can use the method for multi-channel parallel work to increase read-out speed, its cost is to increase extra row to read level and output buffer stage, thereby has increased power consumption, area and circuit complexity.
Summary of the invention
(1) technical matters that will solve
The purpose of this invention is to provide a kind of infrared focal plane read-out circuit and output stage structure thereof, to solve the defective that traditional reading out structure power consumption is big, complexity is high, speed is low.
(2) technical scheme
In order to achieve the above object, technical scheme of the present invention proposes a kind of output stage structure of infrared focal plane read-out circuit, and this output stage structure comprises:
The row output stage comprises N column amplifier, is used for reading of every row picture element signal;
The output buffer stage is used for the train of signal line output with described row output stage;
N first switch connects each column amplifier output terminal to exporting the buffer stage input end;
N second switch connects output buffer stage output terminal to each column amplifier positive input terminal;
Described first switch and second switch are by the column selection signal controlling conducting of described sensing circuit, and the realization signal is exported by described output buffer stage serial.
In the above-mentioned output stage structure, also comprise:
Building-out capacitor and compensating resistance are connected in series between the input end and output terminal of described output buffer stage, are used to provide miller compensation, and overcome the RHP influence at zero point.
In the above-mentioned output stage structure, described column selection signal produces logic by the row control signal in the described sensing circuit and produces.
In the above-mentioned output stage structure, the steering logic of described first, second switch is:
After each row readout interval of described sensing circuit began, producing length in proper order by described row control signal generation logic control was T
ColThe column selection pulse signal, T
ColIt is a row readout interval; Each described column selection pulse signal does not overlap mutually, controls first, second switch conduction of each described column amplifier correspondence successively, thereby finishes reading of every column signal successively in described row readout interval.
In the above-mentioned output stage structure, described first, second switch is made of complementary MOS transistor.
Technical scheme of the present invention also proposes a kind of infrared focal plane read-out circuit, comprise that the pixel of output photocurrent integration picture element signal is read array, and the row control signal produces logic and the row control signal produces logic, and this sensing circuit also comprises:
The row output stage comprises N column amplifier, reads array with described pixel respectively and is connected, and is used for reading of every row picture element signal;
The output buffer stage is used for the train of signal line output with described row output stage;
N first switch connects each column amplifier output terminal to exporting the buffer stage input end;
N second switch connects output buffer stage output terminal to each column amplifier positive input terminal;
Described row control signal produces logic, produces the conducting of N described first, second switch of column selection signal controlling, thereby the realization signal is exported by described output buffer stage serial.
In the above-mentioned sensing circuit, be connected in series with building-out capacitor and compensating resistance between the output terminal of described output buffer stage and the input end, be used to provide miller compensation, and overcome the RHP influence at zero point.
In the above-mentioned sensing circuit, the steering logic of described first, second switch is:
After each row readout interval of described sensing circuit began, producing length in proper order by described row control signal generation logic control was T
ColThe column selection pulse signal, T
ColIt is a row readout interval; Each described column selection pulse signal does not overlap mutually, controls first, second switch conduction of each described column amplifier correspondence successively, thereby finishes reading of every column signal successively in described row readout interval.
In the above-mentioned sensing circuit, described first, second switch is made of complementary MOS transistor.
(3) beneficial effect
The infrared focus plane output circuit of output stage structure that technical solution of the present invention provides and application thereof, connect by column amplifier and the whole component unit gain of output buffer stage, the read-out speed of signal is greatly improved, makes the structure of sensing circuit obtain simplifying the also corresponding power consumption that reduced simultaneously.
Description of drawings
Fig. 1 is a face battle array infrared focal plane read-out circuit synoptic diagram in the prior art;
Fig. 2 is an infrared focal plane read-out circuit embodiment synoptic diagram of the present invention;
Fig. 3 is the column signal working timing figure of sensing circuit embodiment of the present invention;
Fig. 4 is the output buffer stage circuit structure diagram of sensing circuit embodiment of the present invention;
Fig. 5 is the column amplifier circuit structure diagram of sensing circuit embodiment of the present invention.
Embodiment
Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
Fig. 2 is an infrared focal plane read-out circuit embodiment synoptic diagram of the present invention, and as shown in the figure, the sensing circuit of present embodiment comprises: M column amplifier array 21 is used to realize reading of every row picture element signal; Output buffer stage 22, realization are read row the train of signal line output of level; M first switch 23 connects the input end of each column amplifier output terminal to output buffer stage 22; M second switch 24 connects the output terminal of each column amplifier positive input terminal to output buffer stage 22; The row control signal produces logic 25, produces the column selection signal, controls an above-mentioned 2M switch, makes signal by exporting buffer stage 22 serials output.Also comprise pixel unit array 28 and the row control signal generation logic 29 as broad as long in addition with prior art.
The sensing circuit of the foregoing description also comprises building-out capacitor 26 and compensating resistance 27, is connected in series to the input end and the output terminal of output buffer stage 22.
In the foregoing description, first and second switch can be made of complementary MOS transistor.
As shown in Figure 2, column amplifier 21 and output buffer stage 22 are structurally merged into a two-stage calculation amplifier, and wherein column amplifier 21 is as the amplifier first order, and output buffer stage 22 is as the amplifier second level.The merging method is as follows:
After two direct cascades of amplifier, can produce stability problem if connect into the unity gain connection.Therefore, building-out capacitor 26 and compensating resistance 27 are to be used to provide miller compensation, and overcome the RHP influence at zero point, to guarantee enough phase margins.
The row control signal produces logic 25 by certain sequential working, and its work schedule as shown in Figure 3.At each row after readout interval begins, column selection signal Col＜1 〉, Col＜2 〉, Col＜M〉and producing logic 25 control sequences by the row control signal, to produce length be T
ColPulse.T
ColBe a row readout interval, must finish reading of each column signal during this period.For avoiding the interference between each column amplifier, each column selection pulse signal does not overlap.Each is listed as when selected, corresponding first switch and second switch closure, and the column amplifier of respective column connects into a unity gain connection two stage amplifer with the output buffer stage, other column amplifiers and output stage first switch and the second switch switch partition by disconnecting.
After adopting the output stage structure of the foregoing description, can shorten greatly the readout time of each column signal, and signal can be estimated by following formula readout time:
T
col＝T
slew+T
setup
T wherein
SlewBe large-signal switching time, generally by of the charge rate decision of row amplifier to building-out capacitor 26.T
SetupBe the small-signal Time Created of two stage amplifer integral body, generally by its unity gain bandwidth decision.
Be compared with the prior art as can be known, in original structure, small-signal Time Created is small-signal sum Time Created of two amplifiers, and in the improvement structure of the embodiment of the invention, small-signal Time Created is by the bandwidth decision of whole amplifier, so the signal read-out speed has very big lifting.
In addition, whole output-stage circuit structure has also obtained great simplification.In the structure before improvement, the output buffer stage generally is designed to two-layer configuration, and inner compensation and biasing circuit that need be independent.And in the structure after improvement, because the output buffer stage second level of two stage amplifer as a whole just, its design can be adopted the simplest single-stage two pipe structure for amplifying.Usually adopt NMOS to do amplifier tube, the PMOS current source is done load, as shown in Figure 4.The structure of output buffer stage is simplified by complicated two-stage Miller amplifier structure and is the simplest single-stage two pipe common source configurations like this.For identical load capacitance driving force, owing to saved the first order, its power consumption also can correspondingly reduce.
At the embodiment of the invention described above infrared focal plane read-out circuit and output stage structure thereof, following design verification an extensive infrared reading circuit.Row ripple reading method is adopted in design, require the pixel output speed greater than 10M, so the row cycle is 100ns.Owing at each row in the cycle, need reserve the one stable period (about 40ns), so require signal Time Created less than 60ns for subsequent conditioning circuit sampling sense data.Column amplifier has adopted five pipe differential configurations, as shown in Figure 5.In order to reduce power consumption, column amplifier is by its unlatching of the switch controlled above the tail current pipe and shutoff.Disconnect when being connected in column amplifier and output buffer stage like this, can eliminate the power consumption of this column amplifier by turn-offing above-mentioned switch.So at any time, the total power consumption of sensing circuit output stage includes only output buffer stage power consumption and a column amplifier power consumption.The output buffer stage adopts above-mentioned single-stage two pipe common source configurations.
Then use a traditional reading out structure as reference on the other hand, in this traditional isostructure, column amplifier adopts identical five pipe differential configurations; The output buffer stage adopts two-stage Miller amplifier, and its first order is five pipe difference amplifiers, and the second level is the single-stage common source configuration.Through emulation, performance comparison is as shown in table 1.
Table 1
| The tradition output stage | Novel output stage | |
| The column amplifier power consumption | 2mW | 2.8mW |
| Output buffer stage power consumption | 11mW | 9mW |
| Always read a grade power consumption | 13mW | 11.8mW |
| Signal readout time | 61ns | 52ns |
From last table 1 as seen, the output stage structure of infrared focal plane read-out circuit of the present invention has improved reading speed when reducing power consumption.Therefore the novel output stage structure of the present invention's proposition has remarkable advantages than traditional structure, so can in the extensive infrared imaging system of a new generation important application be arranged.
More than be preferred forms of the present invention, according to content disclosed by the invention, those of ordinary skill in the art can expect some identical, replacement schemes apparently, all should fall into the scope of protection of the invention.
Claims (9)
1, a kind of output stage structure of infrared focal plane read-out circuit is characterized in that, this output stage structure comprises:
The row output stage comprises N column amplifier, is used for reading of every row picture element signal;
The output buffer stage is used for the train of signal line output with described row output stage;
N first switch connects each column amplifier output terminal to exporting the buffer stage input end;
N second switch connects output buffer stage output terminal to each column amplifier positive input terminal;
Described first switch and second switch are by the column selection signal controlling conducting of described sensing circuit, and the realization signal is exported by described output buffer stage serial.
2, output stage structure as claimed in claim 1 is characterized in that, this output stage structure also comprises:
Building-out capacitor and compensating resistance are connected in series between the input end and output terminal of described output buffer stage, are used to provide miller compensation, and overcome the RHP influence at zero point.
3, output stage structure as claimed in claim 1 is characterized in that, described column selection signal produces logic by the row control signal in the described sensing circuit and produces.
4, output stage structure as claimed in claim 3 is characterized in that, the steering logic of described first, second switch is:
After each row readout interval of described sensing circuit began, producing length in proper order by described row control signal generation logic control was T
ColThe column selection pulse signal, T
ColIt is a row readout interval; Each described column selection pulse signal does not overlap mutually, controls first, second switch conduction of each described column amplifier correspondence successively, thereby finishes reading of every column signal successively in described row readout interval.
As each described output stage structure of claim 1～4, it is characterized in that 5, described first, second switch is made of complementary MOS transistor.
6, a kind of infrared focal plane read-out circuit, comprise that the pixel of output photocurrent integration picture element signal is read array, and the row control signal produces logic and the row control signal produces logic, it is characterized in that this sensing circuit also comprises:
The row output stage comprises N column amplifier, reads array with described pixel respectively and is connected, and is used for reading of every row picture element signal;
The output buffer stage is used for the train of signal line output with described row output stage;
N first switch connects each column amplifier output terminal to exporting the buffer stage input end;
N second switch connects output buffer stage output terminal to each column amplifier positive input terminal;
Described row control signal produces logic, produces the conducting of N described first, second switch of column selection signal controlling, thereby the realization signal is exported by described output buffer stage serial.
7, sensing circuit as claimed in claim 6 is characterized in that, is connected in series with building-out capacitor and compensating resistance between the output terminal of described output buffer stage and the input end, is used to provide miller compensation, and overcomes the RHP influence at zero point.
8, sensing circuit as claimed in claim 6 is characterized in that, the steering logic of described first, second switch is:
After each row readout interval of described sensing circuit began, producing length in proper order by described row control signal generation logic control was T
ColThe column selection pulse signal, T
ColIt is a row readout interval; Each described column selection pulse signal does not overlap mutually, controls first, second switch conduction of each described column amplifier correspondence successively, thereby finishes reading of every column signal successively in described row readout interval.
As each described sensing circuit of claim 6～8, it is characterized in that 9, described first, second switch is made of complementary MOS transistor.
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| CN2008101197581A CN101358880B (en) | 2008-09-08 | 2008-09-08 | Infrared focal plane read-out circuit and output stage structure thereof |
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| CN2008101197581A CN101358880B (en) | 2008-09-08 | 2008-09-08 | Infrared focal plane read-out circuit and output stage structure thereof |
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| CN101582978B (en) * | 2009-06-18 | 2011-02-09 | 东南大学 | Background suppression method for infrared reading circuit and circuit thereof |
| CN102095501A (en) * | 2010-12-02 | 2011-06-15 | 北京广微积电科技有限公司 | IRFPA (Infrared Focal Plane Array) and read-out circuit thereof |
| CN102447845A (en) * | 2011-09-30 | 2012-05-09 | 北京大学 | Infrared focal plane array readout circuit and adaptive power consumption regulation method thereof |
| CN103234640A (en) * | 2013-04-02 | 2013-08-07 | 电子科技大学 | Scanning control circuit of infrared focal plane array |
| CN103267579A (en) * | 2013-04-27 | 2013-08-28 | 电子科技大学 | Detection circuit of line control circuit of infrared focal plane reading circuit |
| CN106500847A (en) * | 2016-09-26 | 2017-03-15 | 东南大学 | A kind of quick measuring circuit of two-dimentional resistive sensor array |
| CN106706138A (en) * | 2017-01-19 | 2017-05-24 | 中国科学院上海技术物理研究所 | Phase self-compensation infrared detector readout circuit |
| CN108234909A (en) * | 2018-01-17 | 2018-06-29 | 北京大恒图像视觉有限公司 | A kind of industrial camera based on every column jump type CCD |
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| DE69218755T2 (en) * | 1992-01-24 | 1997-07-10 | Rockwell International Corp | Readout amplifier for staring infrared image plane system |
| CN1193595C (en) * | 2003-06-18 | 2005-03-16 | 北京大学 | Readout circuit of focal plane for quick-flasing charge amplifying structure and its readout method |
| CN100490497C (en) * | 2007-01-26 | 2009-05-20 | 东南大学 | Read-out circuit of infrared focal plane |
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- 2008-09-08 CN CN2008101197581A patent/CN101358880B/en not_active Expired - Fee Related
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| CN101582978B (en) * | 2009-06-18 | 2011-02-09 | 东南大学 | Background suppression method for infrared reading circuit and circuit thereof |
| CN102095501A (en) * | 2010-12-02 | 2011-06-15 | 北京广微积电科技有限公司 | IRFPA (Infrared Focal Plane Array) and read-out circuit thereof |
| CN102095501B (en) * | 2010-12-02 | 2012-06-27 | 北京广微积电科技有限公司 | IRFPA (Infrared Focal Plane Array) and read-out circuit thereof |
| CN102447845A (en) * | 2011-09-30 | 2012-05-09 | 北京大学 | Infrared focal plane array readout circuit and adaptive power consumption regulation method thereof |
| CN102447845B (en) * | 2011-09-30 | 2013-07-31 | 北京大学 | Infrared focal plane array readout circuit and adaptive power consumption regulation method thereof |
| CN103234640A (en) * | 2013-04-02 | 2013-08-07 | 电子科技大学 | Scanning control circuit of infrared focal plane array |
| CN103234640B (en) * | 2013-04-02 | 2015-07-22 | 电子科技大学 | Scanning control circuit of infrared focal plane array |
| CN103267579A (en) * | 2013-04-27 | 2013-08-28 | 电子科技大学 | Detection circuit of line control circuit of infrared focal plane reading circuit |
| CN106500847A (en) * | 2016-09-26 | 2017-03-15 | 东南大学 | A kind of quick measuring circuit of two-dimentional resistive sensor array |
| CN106500847B (en) * | 2016-09-26 | 2019-03-12 | 东南大学 | A kind of rapid survey circuit of the resistive sensor array of two dimension |
| CN106706138A (en) * | 2017-01-19 | 2017-05-24 | 中国科学院上海技术物理研究所 | Phase self-compensation infrared detector readout circuit |
| CN106706138B (en) * | 2017-01-19 | 2023-07-04 | 中国科学院上海技术物理研究所 | Phase self-compensating infrared detector reading circuit |
| CN108234909A (en) * | 2018-01-17 | 2018-06-29 | 北京大恒图像视觉有限公司 | A kind of industrial camera based on every column jump type CCD |
| CN108234909B (en) * | 2018-01-17 | 2020-05-01 | 北京大恒图像视觉有限公司 | Industrial camera based on spaced-column transfer type CCD |
| CN114422731A (en) * | 2022-01-17 | 2022-04-29 | 华中科技大学 | Infrared reading circuit and pixel circuit |
| CN114422731B (en) * | 2022-01-17 | 2023-09-22 | 华中科技大学 | Infrared reading circuit and pixel circuit |
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