CN101355040A - Stacking structure for multiple chips and manufacturing method thereof - Google Patents
Stacking structure for multiple chips and manufacturing method thereof Download PDFInfo
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- CN101355040A CN101355040A CNA2007101390230A CN200710139023A CN101355040A CN 101355040 A CN101355040 A CN 101355040A CN A2007101390230 A CNA2007101390230 A CN A2007101390230A CN 200710139023 A CN200710139023 A CN 200710139023A CN 101355040 A CN101355040 A CN 101355040A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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Abstract
The invention discloses a multi-chip piling structure and a manufacturing method thereof. In the multi-chip piling structure, a chip supporting piece is provided with a first surface and a second surface, so that at least one first chip and a second chip can be connected to the first surface of the chip supporting piece, and are electrically connected to the chip supporting piece through a weld line, and at least one third chip is separated by a film and is piled on the first chip and the second chip, wherein the third chip is connected with the first chip in stepped mode; the film at least covers the part of the weld line end connected to the second chip; and the third chip and the chip supporting piece are electrically connected through the weld line; therefore, more chips can be piled on the third chip continuously in the stepped mode so as to improve the electric function.
Description
Technical field
The present invention relates to a kind of semiconductor structure and method for making thereof, particularly relate to a kind of multi-chip stacking structure and method for making thereof.
Background technology
Because the microminiaturization of electronic product and the increase of high speed of service demand, and be to improve the performance of single semiconductor package and capacity to meet the demand of miniaturization of electronic products, semiconductor package is into a trend with multi-chip moduleization (Multichip Module), thereby thus with two or more chip portfolios in single encapsulating structure, with reduction electronic product integrated circuit structural volume, and promote electrical functionality.That is multichip packaging structure can pass through two or more chip portfolios in single encapsulating structure the restriction of system running speed to be minimized; In addition, multichip packaging structure can reduce the length of chip chamber connection line and reduce signal delay and access time.
Common multichip packaging structure is for adopting side-by-side (side-by-side) multichip packaging structure, and it is the main installed surface that plural chip is installed on each other abreast a common substrate.Being connected between the conducting wire generally is to reach by wire bonds mode (wire bonding) on chip and the common substrate.Yet to be packaging cost too high and the encapsulating structure size is too big for the shortcoming of this side-by-side multichip package structure, because the area of this common substrate can increase along with the increase of core number.
For solving above-mentioned existing issue, in recent years for using rectilinear stacking method that the chip that is increased is installed, its mode of piling up is according to the design of its chip, the routing processing procedure is had nothing in common with each other, but if this chip is designed to weld pad when concentrating on one side, set flash chip (flash memory chip) or DRAM (Dynamic Random Access Memory) chip (DynamicRandom Access Memory in the electronic installation of memory card for example, DRAM) etc., convenience for routing, its stack manner is to carry out with stair-stepping form, United States Patent (USP) the 6th shown in Figure 1A and Figure 1B, 538, the multi-chip stacking structure that is disclosed for No. 331 (wherein Figure 1B is the vertical view of corresponding Figure 1A), be on chip bearing member 10, to have piled up a plurality of flash chips, so that first flash chip 11 is installed on the chip bearing member 10, it is to be scalariform under the principle to be stacked on this first chip 11 that second flash chip 12 does not hinder the routing operation of first chip, 11 weld pads with the distance of a skew, in addition, in the electronic installation of this memory card, be provided with control chip (controller) 13 again, the periphery of this control chip 13 is provided with a plurality of weld pads, to pass through a plurality of bonding wires 15 with those flash chips 11,12 and control chip 13 be electrically connected to this chip bearing member 10.
And be to save the substrate usage space, this control chip 13 can be stacked on this second flash chip 12, but so will increase integrally-built height; Moreover since the planar dimension of general this control chip 13 much smaller than the planar dimension of this flash chip 11,12, therefore when utilizing bonding wire 15 that this control chip 13 is electrically connected to this chip bearing member 10, those bonding wires 15 certainly will be crossed over the flash chip 11,12 of these control chip 13 belows, so promptly easily cause bonding wire 15 to touch to flash chip 11,12 and the problem that is short-circuited, also increase the degree of difficulty of bonding wire operation simultaneously.
Relatively, this control chip 13 is placed on the chip bearing member 10 for connecing the zone of putting flash chip 11,12, can increase the usable floor area of chip bearing member again, unfavorable integrally-built miniaturization as desire.
Therefore, how a kind of structure and method for making thereof of stacked multichip are provided, integrate a plurality of chips and need the extra encapsulating structure area, highly of increasing again to reach, to be applicable to thin type electronic device, reduce bonding wire operational difficulty degree simultaneously and avoid the problem of being short-circuited, real target for demanding urgently at present reaching.
Summary of the invention
In view of the shortcoming of above prior art, main purpose of the present invention provides a kind of multi-chip stacking structure and method for making thereof, thereby can carry out piling up of multilayer chiop additionally not increasing under encapsulating structure area and the height principle.
Another object of the present invention provides a kind of multi-chip stacking structure and method for making thereof, must be applicable to thin type electronic device.
Another purpose of the present invention provides a kind of multi-chip stacking structure and method for making thereof, is minimized bonding wire operational difficulty degree and avoids bonding wire to touch chip and the problem that is short-circuited.
For reaching above-mentioned and other purpose, the invention provides a kind of method for making of multi-chip stacking structure, comprise: a tool first and second surperficial chip bearing member relatively is provided, place this chip bearing member first surface so that at least one first chip and at least one second chip are connect, wherein this first and second chip is to be electrically connected to this chip bearing member by bonding wire; At least one the 3rd street one glued membrane (film) is the scalariform mode is stacked on this first chip, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and makes this glued membrane coat the part bonding wire end of this second chip at least; And utilize bonding wire to electrically connect the 3rd chip and chip bearing member.
By aforementioned method for making, the present invention also provides a kind of multi-chip stacking structure, comprising: a tool is first and second surperficial chip bearing member relatively; At least one first chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire; At least one second chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire; And at least one the 3rd chip, a glued membrane (film) and be the scalariform mode and be stacked on this first chip at interval, and make this glued membrane coat the part bonding wire end of this second chip at least, and be electrically connected to this chip bearing member by bonding wire.
In addition, can on the 3rd chip, be the scalariform mode again and pile up the four-core sheet.In addition those chips generally the routing mode or oppositely welding (Reverse Wired Bond) mode and with this chip bearing member electric connection, wherein this reverse welding manner is that the weldering earlier of bonding wire outer end is tied to this chip bearing member, again its inner is soldered to this chip, use and reduce the bank height, and then further reduce the thickness of glued membrane, so that more frivolous multi-chip stacking structure to be provided.
This first, the 3rd and the four-core sheet be the monolateral weld pad of tool (for example for memory chip), an and side of corresponding its tool weld pad and depart from square chip one predefined distance down, and stepped piling up.This second chip is provided with a plurality of weld pads (for example being control chip) at least on one side, and the planar dimension of this second chip less than first, the 3rd and four-core plate plane size.
Therefore, multi-chip stacking structure of the present invention and method for making thereof, be at least one first and second chip to be connect place the chip bearing member surface, and utilize bonding wire to be electrically connected to this chip bearing member, on this first and second chip, utilize glued membrane envelope curve technology (Film over Wire again, FOW) being the scalariform mode with interval one glued membrane is stacked on this first chip, and the part bonding wire end that this glued membrane is coated at least be connected to this second chip, and be electrically connected to chip bearing member by bonding wire, use avoid prior art with this planar dimension when second chip (control chip) of the first and the 3rd chip (memory chip) planar dimension is stacked in the 3rd chip, increase integrally-built height, and can avoid bonding wire to cross over and touching is short-circuited to the first and the 3rd chip (memory chip) and increases bonding wire operational difficulty degree problem, moreover, because of this second chip is directly to connect to place on the chip bearing member and utilize glued membrane envelope curve technology to be the scalariform mode with interval one glued membrane by the 3rd chip to be stacked on this first chip, and the part bonding wire end that this glued membrane is coated at least be connected to this second chip, so can save the chip bearing member usage space, in order to integrally-built miniaturization.
Description of drawings
Figure 1A and Figure 1B are United States Patent (USP) the 6th, 538, the multi-chip stacking structure section and the floor map that are disclosed for No. 331;
Fig. 2 A to Fig. 2 C is the generalized section of multi-chip stacking structure of the present invention and method for making first embodiment thereof;
Fig. 3 is the generalized section of multi-chip stacking structure of the present invention and method for making second embodiment thereof; And
Fig. 4 is that multi-chip stacking structure of the present invention and method for making the 3rd thereof are implemented generalized section.
The component symbol explanation
10 chip bearing members, 11 first chips
12 second chips 13 the 3rd chip
15 bonding wires, 20 chip bearing members
21 first chips, 22 second chips
23 the 3rd chips, 210,220,230 weld pads
251,252,253 bonding wires, 26 glued membranes
30 chip bearing members, 31 first chips
32 second chips 33 the 3rd chip
34 four-core sheets, 354 bonding wires
40 chip bearing members, 41 first chips
42 second chips 43 the 3rd chip
420 weld pads, 452 bonding wires
46 glued membranes
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
First embodiment
See also Fig. 2 A to Fig. 2 C, be the generalized section of multi-chip stacking structure of the present invention and method for making first embodiment thereof.
Shown in Fig. 2 A, one tool first and second surperficial chip bearing member 20 relatively is provided, place this chip bearing member 20 first surfaces so that at least one first chip 21 and at least one second chip 22 are connect, and make this first and second chip 21,22 be electrically connected to this chip bearing member 20 by bonding wire 251 and 252 respectively.
This first chip 21 and second chip 22 for example are memory chip and control chip, these second chip, 22 planar dimensions are less than first chip, 21 planar dimensions, and these first chip, 21 monolateral marginal surfaces are provided with a plurality of weld pads 210, this second chip 22 is provided with a plurality of weld pads 220 (representing with the polygon weld pad that is provided with among this figure) at least on one side, to be electrically connected to this chip bearing member 20 by bonding wire 251,252 respectively, this chip bearing member 20 can be a spherical grid array type (BGA) substrate, planar gate array (LGA) substrate or lead frame.
Shown in Fig. 2 B and Fig. 2 C, utilize glued membrane envelope curve (Film over Wire, FOW) technology, at least one the 3rd chip 23 interval one glued membranes (film) 26 are stacked on this first and second chip 21,22, wherein the 3rd chip 23 is the scalariform mode and connects and place on this first chip 21, and makes this glued membrane 26 coat part bonding wire 252 ends that are connected to this second chip 22 at least.Then, utilize bonding wire 253 to electrically connect the 3rd chip 23 and chip bearing member 20.
The 3rd chip 23 for example is the memory chip of the monolateral weld pad of tool, the 3rd chip 23 is to depart from first chip, 21 1 predefined distances with a side of its tool weld pad 230, make and be able to be electrically connected to this chip bearing member 20 for this first and the 3rd chip 21,23 in the unlikely weld pad 210 that keeps off first chip 21 of the 3rd chip 23 zone vertically upward by many bonding wires 251,253.
So comparing prior art piles up a plurality of chips merely, the present invention connects first chip 21 to place on the chip bearing member 20 together with second chip 22, again in this first and second chip 21, utilize glued membrane envelope curve (FOW) technology to make the 3rd chip 23 glued membranes (film) 26 and be the scalariform mode and be stacked on this first chip 21 at interval on 22, and make this glued membrane 26 coat part bonding wire 252 ends that this is connected to this second chip 22 at least, reaching compact purpose, and can avoid connecting second chip 22 is crossed over the bonding wire 252 of chip bearing member 20 and touching to the first and the 3rd chip 21,23 and be short-circuited and increase bonding wire operational difficulty degree problem.
By aforementioned method for making, the present invention also provides a kind of multi-chip stacking structure, comprising: a tool is first and second surperficial chip bearing member 20 relatively; At least one first chip 21 connects and places this chip bearing member 20 first surfaces, and is electrically connected to this chip bearing member by bonding wire 251; At least one second chip 22 connects and places this chip bearing member 20 first surfaces, and is electrically connected to this chip bearing member 20 by bonding wire 252; And at least one the 3rd chip 23, a glued membrane (film) 26 and being stacked on this first and second chip 21,22 at interval, and and be electrically connected to this chip bearing member 20 by bonding wire 253, wherein the 3rd chip 23 is the scalariform mode and connects and place on this first chip 21, and makes this glued membrane 26 coat part bonding wire 252 ends that are connected to this second chip 22 at least.
Therefore, multi-chip stacking structure of the present invention and method for making thereof, be at least one first and second chip to be connect place the chip bearing member surface, and utilize bonding wire to be electrically connected to this chip bearing member, on this first and second chip, utilize glued membrane envelope curve technology (Film over Wire again, FOW) being the scalariform mode with interval one glued membrane is stacked on this first chip, and the part bonding wire end that this glued membrane is coated at least be connected to this second chip, and be electrically connected to chip bearing member by bonding wire, use avoid existing with this planar dimension when second chip (control chip) of the first and the 3rd chip (memory chip) planar dimension is stacked in the 3rd chip, increase integrally-built height, and can avoid bonding wire to cross over and touching is short-circuited to the first and the 3rd chip (memory chip) and increases bonding wire operational difficulty degree problem, moreover, because of this second chip is directly to connect to place on the chip bearing member and utilize glued membrane envelope curve technology to be the scalariform mode with interval one glued membrane by the 3rd chip to be stacked on this first chip, and the part bonding wire end that this glued membrane is coated at least be connected to this second chip, so can save the chip bearing member usage space, in order to integrally-built miniaturization.
Second embodiment
See also Fig. 3, be the schematic diagram of multi-chip stacking structure of the present invention and method for making second embodiment thereof.Present embodiment and previous embodiment are roughly the same, main difference is to connect on the 3rd chip 33 that places first and second chip 31,32, continue to pile up four-core sheet 34 as memory chip with the scalariform stack manner, and be electrically connected to chip bearing member 30 by bonding wire 354, to promote integrally-built memory capacity.
The 3rd embodiment
See also Fig. 4, be the schematic diagram of multi-chip stacking structure of the present invention and method for making the 3rd embodiment thereof.Present embodiment and previous embodiment are roughly the same, main difference is that second chip 42 can adopt reverse welding manner (Reverse Wired Bond) and be electrically connected to chip bearing member 40, also be about to burn the weld pad 420 of ball bonding knot earlier with bonding wire 452 outer ends of chip bearing member 40 to second chip 42 in order to connect second chip 42, to form a projection (stud), again from chip bearing member 40 welding, on draw and be soldered on this projection, so that (StitchBond) sewed up to the projection of these second chip, 42 weld pads 420 in bonding wire 452 the inners, so, can reduce the bank height that this second chip 42 and chip bearing member 40 electrically connect, and then reduce to connect and place this first and second chip 41 for the 3rd chip 43, required glued membrane 46 thickness on 42 are with the height of further reduction integral stacked structure.
Generally routing mode or reverse welding manner and be electrically connected to this chip bearing member 40 of this first chip 41 and the 3rd chip 43 in addition by bonding wire.
Above-described specific embodiment, only release characteristics of the present invention and effect in order to example, but not in order to limit the category of implementing of the present invention, do not breaking away under above-mentioned spirit of the present invention and the technology category, the disclosed content of any utilization and the equivalence finished changes and modify, the scope that all still should be claims contains.
Claims (16)
1. the method for making of a multi-chip stacking structure comprises:
Relatively first and second surperficial chip bearing member of one tool is provided, places this chip bearing member first surface so that at least one first chip and at least one second chip are connect, and make this first and second chip be electrically connected to this chip bearing member by bonding wire;
At least one the 3rd street one glued membrane (film) is stacked on this first and second chip, and wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and the part bonding wire end that this glued membrane is coated at least be connected to this second chip; And
Utilize bonding wire to electrically connect the 3rd chip and chip bearing member.
2. the method for making of multi-chip stacking structure according to claim 1, wherein, this second chip planar dimension is less than the first chip planar dimension.
3. the method for making of multi-chip stacking structure according to claim 1, wherein, this first chip and the 3rd chip are memory chip, this second chip is a control chip.
4. the method for making of multi-chip stacking structure according to claim 3, wherein, this first chip and the monolateral marginal surface of the 3rd chip are provided with a plurality of weld pads, and this second chip marginal surface at least on one side is provided with a plurality of weld pads.
5. the method for making of multi-chip stacking structure according to claim 1, wherein, this chip bearing member is wherein one of spherical grid array type (BGA) substrate, planar gate array (LGA) substrate and a lead frame.
6. the method for making of multi-chip stacking structure according to claim 1, wherein, the 3rd chip is to utilize the glued membrane envelope curve (Film over Wire, FOW) technology are stacked on this first and second chip with a glued membrane (film) at interval.
7. the method for making of multi-chip stacking structure according to claim 1 also is included on the 3rd chip and piles up the four-core sheet in the scalariform mode.
8. the method for making of multi-chip stacking structure according to claim 1, wherein, this first, second and third chip is to select to utilize wherein one of general routing mode and reverse welding manner (ReverseWired Bond), and is electrically connected to this chip bearing member.
9. multi-chip stacking structure, it comprises:
One tool is first and second surperficial chip bearing member relatively;
At least one first chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire;
At least one second chip connects and places this chip bearing member first surface, and is electrically connected to this chip bearing member by bonding wire; And
At least one the 3rd chip, a glued membrane (film) and being stacked on this first and second chip at interval, and utilize bonding wire to be electrically connected to this chip bearing member, wherein the 3rd chip is to be the scalariform mode to connect and place on this first chip, and makes this glued membrane coat the part bonding wire end of this second chip at least.
10. multi-chip stacking structure according to claim 9, wherein, this second chip planar dimension is less than the first chip planar dimension.
11. multi-chip stacking structure according to claim 9, wherein, this first chip and the 3rd chip are memory chip, and this second chip is a control chip.
12. multi-chip stacking structure according to claim 11, wherein, this first chip and the monolateral marginal surface of the 3rd chip are provided with a plurality of weld pads, and this second chip marginal surface at least on one side is provided with a plurality of weld pads.
13. multi-chip stacking structure according to claim 9, wherein, this chip bearing member is wherein one of spherical grid array type (BGA) substrate, planar gate array (LGA) substrate and a lead frame.
14. multi-chip stacking structure according to claim 9, wherein, the 3rd chip is to utilize the glued membrane envelope curve (Film over Wire, FOW) technology are stacked on this first and second chip with a glued membrane (film) at interval.
15. multi-chip stacking structure according to claim 9 also is included on the 3rd chip and piles up the four-core sheet in the scalariform mode.
16. multi-chip stacking structure according to claim 9, wherein, this first, second and third chip is to select to utilize wherein one of general routing mode and reverse welding manner (Reverse WiredBond), and is electrically connected to this chip bearing member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101390230A CN101355040B (en) | 2007-07-23 | 2007-07-23 | Stacking structure for multiple chips and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101390230A CN101355040B (en) | 2007-07-23 | 2007-07-23 | Stacking structure for multiple chips and manufacturing method thereof |
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| Publication Number | Publication Date |
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| CN101355040A true CN101355040A (en) | 2009-01-28 |
| CN101355040B CN101355040B (en) | 2010-06-09 |
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| CN2007101390230A Active CN101355040B (en) | 2007-07-23 | 2007-07-23 | Stacking structure for multiple chips and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891137A (en) * | 2011-07-19 | 2013-01-23 | 矽品精密工业股份有限公司 | Semiconductor package |
| CN103000588A (en) * | 2011-09-09 | 2013-03-27 | 东琳精密股份有限公司 | Chip packaging structure and manufacturing method thereof |
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2007
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102891137A (en) * | 2011-07-19 | 2013-01-23 | 矽品精密工业股份有限公司 | Semiconductor package |
| CN103000588A (en) * | 2011-09-09 | 2013-03-27 | 东琳精密股份有限公司 | Chip packaging structure and manufacturing method thereof |
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| CN101355040B (en) | 2010-06-09 |
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