Embodiment
In order to realize that firmware to the universalization of inductor and the support of mobilism, the invention provides a kind of method and device thereof of supporting different inductors of firmware.Next will specify this method and device thereof.
Fig. 1 illustrates structure drawing of device of the present invention.As shown in Figure 1, this device comprises the processor that contains firmware, inductor 1 and inductor 2, and EEPROM, wherein: processor, inductor 1 and inductor 2 and EEPROM are connected by the I2C bus, and processor also is connected by data bus with inductor.
When inductor 1 or 2 need reinitialize configuration information, by the processor that contains firmware pseudo-assembly code among the described EEPROM is resolved, be converted to standard assembly code instruction and inductor 1 or 2 is configured.
In one embodiment, inductor is that the type that parameter is adjusted in real time is set, as the imaging inductor of camera or camera.What need dynamically change and setting is the time shutter of inductor.When inductor need reinitialize configuration information, by the processor that contains firmware pseudo-assembly code among the described EEPROM is resolved, be converted to standard assembly code instruction and inductor is configured, the time shutter of also promptly setting inductor gets final product.
Specifically, the firmware of process chip solidifies often, and will support different inductors, often needs to utilize exposure formula manipulation function in real time the time shutter of inductor to be made amendment.If firmware is after solidifying, the exposure-processed function can't be revised.Utilize the I2C interface of system to support EEPROM, in EEPROM, add one piece of data (the pseudo-assembly code that also promptly comprises inductor configurations information).When inductor needs initialization, firmware is read the pseudo-assembly code in the ram space of system or system from EEPROM, when finding to need to revise the time shutter, by pseudo-assembly code analysis program the pseudo-assembly code among the RAM is resolved, the assembly code execution command that converts standard to is carried out, and realizes the calculation exposure time and is write the function of inductor the time shutter.
Fig. 2 illustrates workflow diagram of the present invention.As shown in Figure 2, this technical scheme comprises peripheral operation and built-in function two parts.The concrete steps of peripheral operation are: the text of editor TXT also is the pseudo-assembly code of text formatting, and this pseudo-assembly code comprises the configuration information of inductor; Through the operation of PC, be converted to the Bin file that processor can be discerned by PC end software; The Bin file storage in EEPROM.
The step of built-in function is: when inductor needs initial configuration, read in the processor leaving among the EEPROM Bin file in, or among the RAM, the Bin file that comprise inductor configurations information this moment is the data form; After firmware (code form) parsing in the processor, be converted to the code formatted file, also be real assembly language; Carried out by firmware, inductor is configured and drives with conversion back code file.
Next, the form of described pseudo-assembly code and the form of dependent instruction are described further, specific as follows:
Pc holds order format
[instruction title]
Data movement instruction:
The MOV data transmit
Arithmetic operation instruction:
The ADD add instruction
The SUB subtraction instruction
The MUL multiplying order
The DIV divide instruction
The instruction that rems of RDIV division
Logic instruction:
The instruction of AND logical and
The instruction of 0R logical OR
The ROR right shift instruction
The ROL left shift instruction
Conditional branch instruction:
LARGE judges whether greater than instruction
CJNE judges whether to equal instruction
The END instruction of END IF block
Delaye statement:
DELAY postpones the time of appointment
The Sensor operational order:
WSEN writes the Sensor instruction
RSEN reads the Sensor instruction
The EEPROM operational order:
WE2P writes a byte in EEPROM
RE2P reads a byte from EEPROM
Batch Write instruction:
BDATA is provided with the data of Batch Write
BSTART is provided with and startup Batch Write
[order format]
Order format: instruction word destination operand, source operand CMD AIM, SOURCE
SOURCE:R0, R1, R2, R3, T, TIMES, address, several immediately
AIM:R0, R1, R2, R3, T, TIMES, address, several immediately
[operand format]
Operand comprises register, address, counts immediately.
Data type separately:
R0-R3 DWORD
T DWORD
TIMES WORD
Address WORD
Count 1-4BYTE immediately
[register]
The operable register of system is: R0, R1, R2, R3, T, TIMES, totally 6.Wherein R0-R3 is a common register, is used to deposit temporary variable.
T and TIMES are used for AE formula (exposure-processed formula), and its special function is arranged, and can not be used for public register and use.
[address]
System can visit the value in the register of Chip, and format write is: [operand].
" [] " is used to identify the value representation address of operand but not data; Operand that can presentation address can be register and count immediately that wherein register can only be these four registers of R0-R3; Number is 2 byte lengths immediately.
[counting immediately]
The length of Shuoing can be the 1-4 byte immediately; Number is directly used numerals immediately, can be with 10 systems and 16 system modes (front adds " 0x ").
Can be expressed as numeral 1234: 1,234 10 systems
0x,4D2 16 systems
[conditional statement form]
The form of conditional statement is:
LARGE/CJNEAIM,SOURCE
Condition is genuine handling procedure
END
Condition is false handling procedure
END
LARGE judges that whether the value of AIM is greater than SOURCE;
CJNE judges whether AIM equates with SOURCE.
Whether two handling procedures all must have two END corresponding with the condition judgment instruction no matter need.
The binary code of conditional statement correspondence is:
The binary code of conditional statement+
Condition be genuine handling procedure degree (2 byte)+condition be genuine handling procedure binary code+
Condition be false handling procedure degree (2 byte)+condition for the binary code of false handling procedure+
That is to say that for binary code, each condition judgment statement also has 4 bytes to represent the length of true and false two handling procedures except instruction length itself.
[order format]
Instruction word |
The instruction word machine |
The destination operand type |
The source operand type |
Command function |
|
The device sign indicating number |
|
|
|
MOV |
0x01 |
Register, address |
Register, address, several immediately |
Be used for source operand is written to destination operand |
ADD |
0x02 |
Register, address |
Register, address, several immediately |
Destination operand is added source operand, and the result is write in the destination operand. |
SUB |
0x03 |
Register, address |
Register, address, several immediately |
|
MUL |
0x04 |
Register, address |
Register, address, several immediately |
Destination operand and source operand are multiplied each other, and the result is write in the destination operand. |
DIV |
0x05 |
Register, address |
Register, address, several immediately |
Destination operand is removed source operand, and the result is write in the destination operand. |
RDIV |
0x06 |
Register, address |
Register, address, several immediately |
Destination operand is removed source operand, and remainder is write in the destination operand. |
AND |
0x07 |
Register, address |
Register, address, several immediately |
With destination operand step-by-step and last source operand, and the result write in the destination operand. |
0R |
0x08 |
Register, address |
Register, address, several immediately |
With the destination operand step-by-step with or source operand, and the result write in the destination operand. |
ROR |
0x09 |
Register, address |
Register, address, several immediately |
With the move to right figure place of source operand appointment of destination operand, and the result write in the destination operand. |
ROL |
0x0A |
Register, address |
Register, address, several immediately |
With the move to left figure place of source operand appointment of destination operand, and the result write in the destination operand. |
END |
Do not have |
Do not have |
Do not have |
Only be used to indicate the end of judgement formula branch, do not produce machine code. |
LARGE |
0x10 |
Register, address, several immediately |
Register, address, several immediately |
Comparison order if destination operand greater than source operand, is then carried out first branch, otherwise is carried out second branch. |
CJNE |
0x11 |
Register, address, several immediately |
Register, address, several immediately |
Comparison order if destination operand equals source operand, is then carried out first branch, otherwise carries out second branch. |
DELAY |
0x0F |
Do not have |
Register, address, several immediately |
The time that postpones appointment; Parameter is that firmware carries out for round-robin number of times. |
WSEN |
0x20 |
The address |
Register, address, several immediately |
The data of source operand are write in the Sensor address of destination operand appointment. |
RSEN |
0x21 |
Register, address |
The address |
Read in the Sensor address of appointment from source operand |
|
|
|
|
Fetch data and be written in the destination operand. |
WE2P |
0x22 |
The address |
Register, address, several immediately |
The data of source operand are write in the eeprom address of destination operand appointment. |
RE2P |
0x23 |
Register, address |
The address |
Reading of data is written in the destination operand in the eeprom address of appointment from source operand. |
BDATA |
0x30 |
Register, address, several immediately |
Register, address, several immediately |
Be used for writing register information to Batch Write variable.Source operand is deposited the data of the register that will write.Destination operand is deposited the address of the register that will write.The sequence number of register begins to be arranged in order according to the appearance of BDATA instruction in proper order among the Batch Write.After each BSTART instruction, sequence number is again since 0. |
BSTART |
0x31 |
Do not have |
Register, address, several immediately |
Batch Write attribute is set, and starts Batch Write operation.Deposit the number of registers group in the source operand. |
[machine code form]
Instruct finally can become to be translated into machine code, deposit in EEPROM, be used for the firmware correlation functions and carry out.
Form can be: instruction word (1 byte)+operand identification (1 byte)
+ destination operand (address or data, variable-length)
+ source operand (address or data, variable-length)
Instruction word, operand identification and each operand are described as follows:
<instruction word 〉
The machine code value that instruction is corresponding.
<operand identification 〉
The attribute that is used for recognition purpose operand and source operand, just which kind of variable this operand is, counts if comprise immediately, also will identify its data length; Bit0-bit3 is used for the attribute of identification sources operand, and bit4-bit7 is used for the attribute of recognition purpose operand.If be address or data, then operation mark or last its length corresponding identification value of address or data to be represented its attribute and length.
Length mark is represented with 2bit, has 4 kinds of length, and the corresponding relation of length and sign is as follows:
1 byte corresponding identification is 0x00 (00b)
2 byte corresponding identification are 0x01 (01b)
3 byte corresponding identification are 0x02 (10b)
4 byte corresponding identification are 0x03 (11b)
The value of each variable in sign is:
Operand |
Operand identification (4bit) |
R0 |
0x00(0000b) |
R1 |
0x01(0001b) |
R2 |
0x02(0010b) |
R3 |
0x03(0010b) |
T |
0x04(0011b) |
TIMES |
0x05(0101b) |
Reserve |
0x06(0110b) |
Number format address immediately |
0x07(0111b) |
The register format address |
0x08(1000b) [R0]1000b [R1]1001b [R2]1010b [R3]1011b |
Count immediately |
0x0C (1100b) 1 byte 1100b 2 byte 1101b 3 byte 1110b 4 byte 1111b |
<destination operand 〉:
If destination operand is address or data, then be used for the value of storage address or data, length is identical with the length of operand identification, the deposit data form is big end mode, promptly high position data is preceding, low data after.
If destination operand is other type, then not needing destination operand, destination operand length is 0.
<source operand 〉:
If but the source operand is address or data, then be used for the value of storage address or data, length is identical with the length of operand identification, and the deposit data form is big end mode, and promptly high position data is preceding, low data after.
If source operand is other type, then not needing source operand, source operand length is 0.
Instruction length is: 2+ destination operand length+source operand length.
[the binary code storage format that control information is used]
When VASM is used in control information, handle outside the binary code data of VASM itself, also need extra data to identify the attribute of these binary code data.
The storage format of formula is:
The total length of formula (2 byte)+// refer to the total length of back data
The kind of the form that formula comprises (1 byte)+// suppose to have the n kind
The formula type of form 1 (1 byte)+//VGA, CIF etc.
The offset address (2 byte) of the formula of form 1 in the formula data+
// offset address calculates from initial beginning of formula data
...
The formula type of form 1 (n byte)+//VGA, CIF etc.
The offset address (2 byte) of the formula of form n in the formula data+
Formula data (variable)
Wherein the form of formula data is:
The length of the formula of form 1 (2 byte)+
The formula data (variable) of form 1
...
The length of the formula of form n (2 byte)+
The formula data (variable) of form n
The form of formula data is: VASM binary code length (2 byte)+binary code data
Wherein, length is meant the length of binary data, does not comprise VASM binary code length itself.
Further, with to inductor resolution be set to exemplify example and describe.
The Test.vasm file comprises the pseudo-assembly code of inductor resolution configuration information, and it is the TXT text formatting, and code is as follows in detail:
@VGA
//uTemp=(t+224)/892;
MOV R0, t
ADD R0,224
DIV R0,892
//pBatchWrite->Reg[0].Value=uTemp;
BDATA 0x09,R0
//AeBatchWrite(pBatchWrite);
BSTART 1
At as above code,, do following detailed description in conjunction with relevant requirements such as the order format among the present invention and operand and numbers immediately:
@VGA
Resolution to inductor is provided with;
//uTemp=(t+224)/892;
The explanatory notes of the computation process of uTemp function;
MOV R0,t
Variable t is sent to common register R0;
ADD R0,224
Immediately several 224 with common register R0 in t numerical value carry out addition, simultaneously the result is composed to common register R0;
DIV R0,892
Numerical value among the common register R0 divided by several 892 immediately, and is composed a result of being divided by to common register R0;
//pBatchWrite->Reg[0].Value=uTemp;
The explanatory notes part is promptly composed the value of uTemp to pBatchWrite->Reg[0] .Value;
BDATA 0x09,R0
The value of common register R0 is composed to register 0x09, the data of BatchWrite promptly are set;
//AeBatchWrite(pBatchWrite);
Start the note of write operation in batches;
BSTART 1
The BatchWrite attribute is set, when being genuine, starts the BatchWrite operation.
Get back to above-mentioned Test.vasm file, externally under the non-productive operation of PC, the conversion through PC end software becomes Test.Bin to this Test.vasm file, is binary Bin file.
This Bin file storage is to eeprom chip inside.Processor is read among the RAM of system or system's setting the Bin file in the eeprom chip by the I2C bus.By the processor firmware code it being made an explanation, is the code form by the data format conversion promptly.Simultaneously, carried out one by one, be configured by the resolution of I2C bus again inductor.
More than specific descriptions of the present invention are intended to illustrate the implementation of specific embodiments can not be interpreted as it is limitation of the present invention.Those of ordinary skills can make various variants on the basis of the embodiment that describes in detail under instruction of the present invention, these variants all should be included within the design of the present invention.The present invention's scope required for protection is only limited by described claims.