CN100586768C - Hardware system structure of intellectualized full-graphics automobile instrument - Google Patents
Hardware system structure of intellectualized full-graphics automobile instrument Download PDFInfo
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Abstract
The present invention relates to a hardware system structure of intelligent wholly-graphic vehicle instrument, and consists of a microprocessor ARM and a field programmable gate array FPGA. The ARM isused for data acquisition and system control; the FPGA is used for video processing and graphic depiction display. The hardware system structure is characterized in that the FPGA and the ARM adopt anIIC mode or a shared memory for communication; the FPGA module is arranged outside, with an AVALON/SRAM serving as a static random access memory SRAM of the ARM processor; the graphic data transmitted from the ARM processor is stored in a synchronous dynamic random access memory SDRAM; the display and drawing array VGA display is driven according to the instructions of the ARM processor, so as torealize the functions of multilayer aliasing display, picture-in-picture display and point-line plotting. The hardware system adopts the highly efficient and flexible ARM+FPGA structure; the ARM is used for data collection, collation, analysis, storage and other functions; and the FPGA field programmable gate array is used for displaying the user interface.
Description
Technical field
The invention belongs to vehicle electronics instrument field, be specifically related to a kind of hardware system structure of intellectualized full-graphics automobile instrument.
Background technology
The electron steering degree of automobile and the level of IT application are in continuous improve, and various mobile units and information service simultaneously also all is being on the increase.Meter system shows the new demand of large amount of complex information as traditional Message Display Terminal under the potential competent new trend.Upgrading conventional instrument system is that intelligent full-graphics of new generation can finely satisfy the demands, and traditional mechanical or the irreplaceable advantage of electromechanical instrument are arranged.
" intellectualized full-graphics automobile instrument " is on the hardware and software platform of independent research, realize multi-functional intellectualized full-graphics automobile instrument system, all information of vehicles are shown to substitute existing analog meter by the TFT LCDs, TFT (Thin Film Transistor) is meant thin film transistor, be that each liquid crystal pixel point all is to be driven by the thin film transistor that is integrated in the pixel back, thereby can accomplish high-speed, high brightness, high-contrast display screen information.Radical function with following 9 aspects:
1. meter system
Core system, specification need according to concrete styling design, all functions of mainly forgiving conventional instrument.By TFT liquid crystal display figure, satisfy high real-time response, can receive signal from CAN bus and sensor, CAN (Controller Area Network) is a controller local area network, is one of most widely used fieldbus in the world.
2. Vehicle Information System
Carry out the diagnosis and the analysis of information of vehicles by the information of collecting, the performance of Zhi Neng monitoring vehicle and situation more, and give user prompt.
3. vehicle-mounted pick-up system
Based on the liquid crystal display of system, realize the vehicle-mounted pick-up function.Support multichannel shooting, maximum 3 the tunnel, and possess anti-dazzle and function night vision, high-end product also can add range only radar.
4. vehicle ' register system
Automobile black box, based on the hardware of meter system, function satisfies the standard of national automobile travel recorder.
5. navigation information system
Realize simple and clear navigation feature.The demonstration of navigation information system is limited to regional area, shows when should not influence meter system.
6. vehicle monitoring system
By connecting global position system GPS (Global Positioning System) module and communication module outward, and, carry out vehicular theft-prevention monitoring and Long-distance Control by monitoring and control centre.
7. telephone system
Mainly be to communicate, can carry out the hands-free phone service by bluetooth and mobile phone.
8. vehicle entertainment system
When vehicle guarantees safety, provide simple amusement and game function.
9. driver assistance safety system
Mainly comprise the driving information that cruises, anticollision information and night travel safety system.
Along with the electron steering degree of automobile improves constantly, the digitalisation of auto meter, graphically also become the development tendency of following auto meter.Intelligent information terminal has not only replaced traditional auto meter with patterned form but also has had the advantage of the information that can provide a large amount of, complicated, but also have high precision and high reliability, the function of a-table-multi-purpose, configuration design is attractive in appearance, degree of freedom is high, it is small-sized to satisfy, weight-saving requires, the characteristics such as function design of hommization, and has extremely strong extensibility.Therefore intelligent information terminal becomes the development new trend of modern automobile, has boundless development space.The integrated information instrument of simultaneous altitude also has bigger cost advantage.
The conventional instrument present situation is as follows at present:
Domestic automobile instrument present situation
◆ stepping electrodynamic type auto meter will be the leading product of auto meter in following a period of time;
◆ adopt the instrument of plane electronics technique of display progressively moving towards market;
◆ adopt the graphical instrument market of TFT blank fully;
◆ part producer and the scientific research institutions research and development similar products that have a mind.
Product on the existing vehicle all is based on traditional electromechanical pointer instrument, still machinery or electrical accident can occur, accuracy and reliability that influence is measured, and its performance remains further to be promoted; The part vehicle has increased that the gray scale liquid crystal is auxiliary to be shown, but the information limitation is big, and function is limited and do not possess extensibility.Look into new record:
◆ digital figure automobile instrument/applicant's Kang Hansong // Chinese patent: publication number 1750048
◆ digital automobile instrument/HeFei XieLi meter Manufacturing Co., Ltd //yahoo.com.cn
◆ Auto Apparatus Information System/Li Bo, Wuhan University of Technology Institute of Automation // electron mass .-2005, (1)
◆ automobile intelligent meter system/applicant's Dongfeng Electric Vehicles Co., Ltd. // Chinese patent of band CAN communication: application number 200320115454
◆ bus type automobile instrument assembly (pointer indication)/Nengfaweiye Automobile Instrument Co., Ltd., Liaoning //google.com
◆ the electronic type automobile combination meter //google.com
◆ NJ1020 series of combination instrument, NJ1035 series of combination instrument/Nanjing Automobile instrucment and meter plant //google.com
◆ the exploitation/Ji Changwei of automobile intelligent digital meter, Beijing University of Technology's environment and energy project institute // journal .-2006 of Beijing University of Technology, (4)
There are following relevant issues in above-mentioned technology:
◆ the liquid crystal display operating temperature is-30～85 degree now ,-45 degree that low temperature out of reach automobile requires
◆ also slightly be worse than traditional mechanical formula instrument on the stability of system
Summary of the invention
Purpose of the present invention is in order to overcome the problems referred to above that prior art exists, and provide a kind of hardware system structure of intellectualized full-graphics automobile instrument, the present invention adopted efficiently, ARM+FPGA framework flexibly, wherein ARM (Advanced RISC Machine) is a kind of performance-oriented 32 and simplifies to hold and make computing collection microprocessor, mainly finish the external data collection, arrangement, analyze, functions such as storage, FPGA (Field Programmable Gate Array) is a field programmable gate array, is mainly used in the demonstration of user interface.
The hardware system structure of intellectualized full-graphics automobile instrument, form by microprocessor ARM+ on-site programmable gate array FPGA, wherein ARM is used for data acquisition and system's control, FPGA is used for video processing and graphic describing shows, it is characterized in that: the signalling methods between FPGA and the ARM is communication of IIC mode or shared drive mode, the FPGA module is played the part of the SRAM SRAM external device of arm processor by the AVALON/SRAM bridge, the image data that arm processor is sent is stored in the synchronous DRAM SDRAM, instruction promotes to show drawing array VGA telltale according to arm processor, finishes the multilayer aliasing and shows, picture-in-picture shows or the line drawing function that stipples.
Described ARM is made up of hardware layer, hardware driving layer, hardware abstraction layer, operating system layer, application layer, the mode that adopts hierarchy, hierarchical design, layering to realize in design, the inside of each layer is realized transparent to other layers, lower floor can only be called by the upper strata is unidirectional, each interlayer functional definition is clear, interface is clear and definite, wherein hardware layer is the hardware platform of whole embedded OS and application program operation, is made of various hardware resources such as concrete chip, module, electronic components.The hardware driving layer is used for these hardware resources of direct drive, the hardware driving layer comprises expansion serial ports, IIC, main frame Peripheral Interface HPI (hostperipherial interface) and chip internal hardware resource etc., its role is to the hardware details of the system that hides, provide software interface hardware operation to upper layer module; Hardware abstraction layer encapsulates the register manipulation of hardware driving layer, provides the service of hardware being carried out after abstract to operating system layer and application layer by the hardware abstraction layer interface; When operating system layer or application layer use hardware abstraction layer API to design, as long as hardware abstraction layer API can realize on lower floor's hardware platform, the code of operating system layer and application layer just can be transplanted easily so, hardware abstraction layer is kept apart system software and hardware components fully, so just makes the driving of system and the exploitation and the hardware device of application program have nothing to do.Operating system layer is by calling the interface of hardware abstraction layer, realize its function as the operation platform of the system platform of managing software and hardware resources and user's control algorithm, and the running and the behavior of application layer control system on the platform of operating system, to realize various concrete functions and application.
Described FPGA internal module is divided into the soft core module of NIOS2, AVALON/SRAM interface module, SDRAM driver module, ram in slice module, configuration device interface module, VGA driver module, is coupled together by the AVALON bus between each module.
Realize the method for intellectualized full-graphics automobile instrument, carry out according to the following steps:
1) signals of vehicles collection: ARM comes in various signals of vehicles collections, and the signals of vehicles collection comprises AD collection, on-off signal collection of vehicle speed pulse collection, tacho-pulse collection, oil mass water temperature etc.;
2) signal condition: because it is serious directly to gather the data noise of coming from driving engine, can't be directly used in demonstration, so need vehicle speed pulse, the rotational speed pulse signal of coming in be analyzed to gathering, conditioning, optimization process with data processing algorithm;
3) signal is given FPGA by protocol transmission: the signal after handling according to self-defining host-host protocol, is transferred to FPGA by iic bus; Self-defining host-host protocol basic format is as follows:
The agreement basic format
* represent arbitrary string
| $ | * | ， | * | ， | * | ， | * | ， | * | ， | * | ， | * | * | * | Carriage return | Line feed |
| Protocol header | Protocol type one | Separator | Protocol type two | Separator | Parameter 1 | Separator | Parameter 2 | Separator | Parameter 3 | Separator | Parameter 4 | Separator | Parameter 5 | Separator | Check code | Carriage return character | Newline |
$ is a protocol header, and # is the agreement tail, and with CSV, first field after the protocol header is the protocol type explanation between the protocol fields, and second field is the agreement direction, and last field before the agreement tail is cyclic redundancy check code CRC.Cyclic redundancy check (CRC) Cyclic RedundancyCheck/Code carries out verification to a transmission block, is a kind of error control method efficiently.
The protocol type explanation:
| Protocol type one | Protocol type two |
| Address bit | Write order |
| Read command |
Main frame sends agreement
| $ | Address bit | ， | Command bit | ， | ， | ， | ， | ， | * | CRC | Carriage return | Line feed |
| Protocol header | The address | Separator | Order | Separator | Separator | Separator | Separator | Separator | Separator | The CRC check sign indicating number | Carriage return character | Newline |
| 1 byte | 3 bytes | 1 byte | 3 bytes | 1 byte | 1 byte | 1 byte | 1 byte | 1 byte | 1 byte | 2 bytes | 1 byte | 1 byte |
Slave sends agreement
| $ | Address bit | ， | Command bit | ， | ， | ， | ， | ， | * | CRC | Carriage return | Line feed |
| Protocol header | The address | Separator | Order | Separator | Separator | Separator | Separator | Separator | Separator | The CRC check sign indicating number | Carriage return character | Newline |
| 1 byte | 3 bytes | 1 word | 3 bytes | 1 byte | 1 byte | 1 byte | 1 byte | 1 byte | 1 byte | 2 bytes | 1 byte | 1 byte |
4) analytic signal: after FPGA receives signal, concrete signal content is parsed according to above self-defining host-host protocol;
5) graphic describing comprises that pointer is drawn, icon is drawn: the image data that FPGA sends arm processor is stored in the synchronous DRAM SDRAM, instruction promotes the VGA telltale according to arm processor, finish the demonstration of multilayer aliasing, picture-in-picture demonstration or the line drawing function that stipples, processing through pointer bitmap compression storage algorithm and pointer rotation and vision optimization algorithm, with the icon display of representing the pointer of rotating speed, the speed of a motor vehicle and various switching values on VGA telltale or liquid crystal display, and realization and signals of vehicles accurately synchronously.In the ARM chip, move real-time kernel, have cooresponding real-time and stability.In order in data accuracy and user adaptation, to obtain a good balance, a plurality of data processing algorithms have also been used in the system, be used for the data of actual acquisition are shown in the mode that the user is easy to accept, avoid causing a large amount of shakes because data precision is too high.
FPGA is by the control of hardware-accelerated realization LCD (Liquid Crystal Display) Liquid Crystal Display (LCD), FPGA supports 5 layers of visual aliasing output, wherein the 0th layer is data format: be the background layer of RGB565 (Red Green Blue) with three kinds of primary colours of RGB, the 1st layer for data format is the image layer of RGB565, and layer 2-4 is to call the drawing layer that data format is 8 palettes of RGB666.Except that basic LCD Presentation Function, also expanded the hardware layering, Alpha mixes, and functions such as video processing have also reached the level of present special-purpose 2D speed-up chip on the 2D acceleration capability.
Description of drawings
Fig. 1 is the system global structure block diagram.
Fig. 2 is an ARM part system architecture diagram.
Fig. 3 is a FPGA part system architecture diagram.
Fig. 4 is system works flow process figure.
The specific embodiment
Overall system design:
As shown in Figure 1, hardware system adopts the ARM+FPGA framework, and wherein ARM is mainly used in data acquisition and system's control, and FPGA is mainly used in video processing and graphic describing shows, details are as follows in the particular hardware design:
The ARM hardware design
As shown in Figure 2, be the design of ARM sub-population, mainly form by hardware layer, hardware driving layer, hardware abstraction layer, operating system layer, application layer.
The mode that adopts hierarchy, hierarchical design, layering to realize in design, the inside of each layer is realized transparent to other layers, and lower floor can only be called by the upper strata is unidirectional, and each interlayer functional definition is clear, interface is clear and definite.Wherein hardware layer is the hardware platform of whole embedded OS and application program operation, is made of various hardware resources such as concrete chip, module, electronic components.The hardware driving layer is used for these hardware resources of direct drive, comprises expanding serial ports, IIC, HPI and chip internal hardware resource etc., its role is to the hardware details of the system that hides, and provides software interface to hardware operation to upper layer module.Hardware abstraction layer encapsulates the register manipulation of hardware driving layer, provides the service of hardware being carried out after abstract to operating system layer and application layer by the hardware abstraction layer interface.When operating system layer or application layer use hardware abstraction layer API to design, as long as hardware abstraction layer API can realize on lower floor's hardware platform that the code of operating system layer and application layer just can be transplanted easily so.Hardware abstraction layer is kept apart system software and hardware components fully, so just makes the driving of system and the exploitation and the hardware device of application program have nothing to do.Operating system layer is by calling the interface of hardware abstraction layer, realize its function as the operation platform of the system platform of managing software and hardware resources and user's control algorithm, and the running and the behavior of application layer control system on the platform of operating system, to realize various concrete functions and application.
Wherein, relevant with ARM part hardware design mainly is hardware abstraction layer and hardware driving layer, and details are as follows respectively.
1 hardware abstraction layer
◆ operating system OS clock
Operating system OS uses a clock to carry out timeticks (Tick) counting, this counting be OS provide all regularly, the basis of time-delay.The frequency of OS clock is generally 1-2Hz/MIPS (per 1,000,000 frequencies that instruction is carried out) generally by the performance of processors decision.For example performance of processors is 100MIPS, and the frequency of OS clock should probably be got between the 100-200Hz so, and the too low meeting of frequency makes the task response-time of OS become big, and the too high meeting of frequency reduces the cpu busy percentage of system.
The OS clock signal triggers clock and interrupts, thereby the corresponding clock interrupt function is called, and the clock interrupt function is understood calling system OS clock service function _ tickTimerISR after handling some necessary programs, this function is responsible for the Tick of system is counted, and safeguards timing, time-delay formation.
On Target Board, the OS clock is served as by timer 0 (Timer0), and the initialization step of timer 0 is as follows:
1. the correlation parameter register is set;
2. assigned interrupt priority is given Timer0;
3. the service function of Timer0 is set to the response function of respective priority;
4. allow the interruption on this priority.
◆ the OS interrupt management;
The processing of interrupting might influence the task executions order, so OS will carry out unified management to the interrupt source of ARM, and ARM does not provide the interrupt nesting on the hardware, so interrupt management also will be responsible for interrupting taking place context to be carried out necessary protection when nested.
The interrupt handling process that meets the OS requirement is as follows:
1. preserve the treater context to the current task storehouse, switch because End of Interrupt might cause task;
2. the interrupt nesting variable adds 1;
3. carry out user's break in service function;
4. in the time of might allowing to interrupt in the user function, close interruption;
5. the interrupt nesting variable subtracts 1;
6. the task that judges whether to carry out is switched;
7. if then carrying out task switches, otherwise interrupt returning.
◆ the OS task is switched
It is the core of whole OS running that task is switched, because contextual switching relates to the characteristic of treater itself, so must finish at level of abstraction.The C CompilerTools of ARM does not provide the direct control to storehouse, and therefore switching must be to finish with assembly code.
Task switching processing process is as follows:
1. handle the current task storehouse, make it be in the preceding state of End of Interrupt;
2. preserve the treater context to the current task storehouse;
3. it is the current task storehouse that next task stack is set;
4. from current task storehouse restore processor context;
5. interrupt returning.
2 hardware driving layers
◆ vehicle speed signal drives
Vehicle speed signal is transmitted with pulse mode, the frequency decision speed of a motor vehicle of pulse.On ARM, the counting procedure by a software calculates the speed of a motor vehicle.Each vehicle speed pulse can cause once interruption, after the response of break in service function speed of a motor vehicle counting machine is added 1, timer Timer1 writes down the value of a speed of a motor vehicle counting machine here as the measurement of the speed of a motor vehicle every a unit time, then his zero clearing, to carry out the record of next unit time.Timer1 will calculate the good speed of a motor vehicle and directly pass to application program with message mode, so the vehicle speed signal driving does not provide interface to application program except the initialization function.The initialization mode of Timer1 and system clock Timer0 are similar.
◆ standard asynchronous transceiver UART drives
UART is exactly the standard asynchronous transceiver, just our serial ports of usually saying.Here serial ports is initialized to standard output device, so that use the printf function that literal demonstration information is outputed to hyper terminal.
What the communication of serial ports was used is the coded system of non-return-to-zero, and just high level is represented logical one, and low level is represented logical zero.Here we are initialized as the standard operation mode with serial ports, 8 bit data positions just, and 1 stop bit, no parity check, data transmission stream is as follows:
The serial initialization step is as follows:
1. the serial ports mode of operation is set;
2. the serial ports baud rate is set;
3. be serial ports assigned interrupt vector;
4. serial ports break in service function is set;
5. allow serial ports to interrupt.
The application programming interfaces that the serial port drive program provides have following two:
_initUart0
Parameter: the baud rate of baudRate serial ports
Return: void
Function: initialization serial ports 0
_uart0Send
Parameter: data, the data that send, least-significant byte is effective;
Return: void;
Function: send a byte data by serial ports 0;
Wherein _ the general application program of uart0Send function can directly not use, he is packaged into standard output function _ putc, called by printf indirectly, so application program can directly be exported the information of needs to serial ports 0, so that be presented on the hyper terminal by the printf function.
◆ IIC drives, and Inter-Integrated Circuit bus is a kind of twin wire universal serial bus by the exploitation of Philips company
Iic bus uses two lines: a serial data line (SDA) and a serial time clock line (SCL) are being connected to transmission information between the device of bus.Device can be counted as main frame or slave when carrying out data transmission.Main frame is the data transmission of initialization bus and the device that produces the clock signal that allows transmission.At this moment, any device that is addressed all is considered to slave.
IIC slave (ARM) operating process is as follows:
1. I/O mouth mode of operation is set, uses the IIC mouth;
2. the slave addresses of self is set;
3. configuration is certainly as the IIC slave mode;
4. interruption is set;
5. enable IIC and interrupt, wait for host service function;
6. judge bus state IISTAT, receive the address of slave self and read (writing) operational order, so that carry out Data Transmission Controlling;
The IIC host service function:
1. initialization CSL;
2. system's dominant frequency is set;
3. initialization IIC is provided with initial address;
4. carry out write operation;
5. carry out read operation;
6. whether success of decision operation result is successful then finish this operation and with mark position 0, unsuccessful then put 1.
The FPGA hardware design
Signalling methods between FPGA and the ARM has two kinds: communication of IIC mode and shared drive mode.
The 1FPGA functional description
In native system, the FPGA module is played the part of the SRAM SRAM peripheral hardware of arm processor by the AVALON/SRAM bridge, the image data that arm processor is sent is stored in the synchronous DRAM SDRAM, instruction promotes to show drawing array VGA (VideoGraphic Array) telltale according to arm processor, finishes functions such as the demonstration of multilayer aliasing, picture-in-picture demonstration, the line drawing that stipples.FPGA mainly contains four peripheral interfaces: sdram interface, VGA D/A interface, arm processor interface, configuration device interface.
The 2FPGA internal module is divided
As shown in Figure 3, the FPGA internal module mainly is divided into the soft core module of NIOS2, AVALON/SRAM interface module, SDRAM driver module, ram in slice module, configuration device interface module, VGA district dynamic model piece, couple together by the AVALON bus between each module, AVALON a kind ofly is connected a kind of simple bus architecture that go up in flakes programmable system with on-chip processor with peripheral hardware, details are as follows for the hierarchical relationship between the division of FPGA module and each module:
The explanation of 3FPGA modular design
◆ the soft core module of NIOS2
Enter in programmable SOC(system on a chip) SOPC (the System On Programmable Chip) environment, after directly in the storehouse, accessing, according to user's request and device resource situation parameter is set and gets final product.
◆ the AVALON/SRAM interface module
This module realizes communicating by letter between FPGA inner module and the outside arm processor.In the SOPC environment, generate by avalon master type with the new element navigational aids, handshake method is by asynchronous system in addition.Physical interface is as follows:
The arm_address A wire
The arm_data data line
Arm_be data byte enable line
Arm_wr writes enable line
Arm_rd reads enable line
Arm_ardy reads enable line
The arm_clk major clock
The arm_ce sheet selects enable line
◆ the SDRAM driver module
Enter in the SOPC environment, after directly in the storehouse, accessing, according to user's request and device resource situation parameter is set and gets final product.SDRAM store picture data and NIOS2 program code and data variable that sheet is outer.
◆ the ram in slice module
Enter in the SOPC environment, after directly in the storehouse, accessing, according to user's request and device resource situation parameter is set and gets final product.
◆ the configuration device interface module
Enter in the SOPC environment, directly in the storehouse, access the ASMI assembly and get final product.
◆ the VGA driver module
The VGA driver module is by verilog HDL language compilation, Verilog HDL is a kind of hardware description language, be that an a kind of textual form is described the structure of digital display circuit hardware and the language of behavior, with it can the presentation logic circuit diagram, logical expression, can also represent the logic function that digital logic system is finished.The soft nuclear of arm processor and NIOS carries out the register setting by the AVALON bus to it, need to select the picture and the pattern of demonstration, and the VGA driver module is finished and pushed away the screen sequential.
Each Verilog file function is as follows:
| Lcd_controller.v | System's top layer design document |
| Avalon_rd_dma_fifo.v | Realize by Avalon bus DMA read-only. |
| Avalon_slave_if.v | Realize the Avalon bus interface |
| Sp_palette_rom.v | 8 256 tone colour tables |
| Pixel_engine.v | The image processing design document generates the RGB data behind the visual aliasing |
| Vga_timing.v | Realize that VGA pushes away the screen sequential |
| DPath.v | Monochromatic multilayer aliasing is handled |
| Blender.v | Monochromatic individual layer aliasing is handled |
| Mult_6bit.v. | 6 * 6 multipliers |
| Mult_6bit_clk.v. | 6 * 6 synchronous multiplier |
| Adder_6bit.v | The 6+6 adder |
| Adder_6bit_cin.v | 6+6 full add musical instruments used in a Buddhist or Taoist mass |
| Lcd_dual_port_fifo.v | Twoport FIFO ((First Input First Output, First Input First Output) |
| Gray_count.v | Gray code counter |
The VGA driver module has following characteristic:
Support 5 layers of visual aliasing output.Wherein the 0th layer for data format is the background layer of RGB565, and the 1st layer for data format is the image layer of RGB565, and layer 2-4 is to call the drawing layer that data format is 8 palettes of RGB666.
1, supports picture-in-picture function.
2, variable-resolution VGA output.
3, have read-only direct memory access DMA (Direct Memory Access) Avalon bus master port, carry out high speed data transmission.Have the Avalon register from port, convenient and ppu communicates.
4 module workflows
As shown in Figure 4, after system reset, there is image data in outside arm processor by the AVALON/SRAM bridge assigned address of SDRAM, after NIOS2 treater in the sheet carried out reasonable disposition to the Avalon of VGA driver module from port register, the Avalon bus master port of VGA driver module started read-only DMA reads the assigned address of SDRAM by the AVALON bus image data.Behind buffering, aliasing, remove to drive the VGA telltale according to the VGA sequential.
5 performance figure
| The system start-up time | 5s |
| The data acquisition minimum interval | 0.01s |
| System task switching time | 0.005s |
| Data acquisition CPU frequency of operation | 200MHz |
| The lcd controller frequency of operation | 50MHz |
| The maximum resolution of supporting of LCD | 800*600dot |
| LCD refreshes frame number | 60fps |
| The speedometer range | 0-320km/h |
| The speed gage range | 0-10000rpm |
| The water thermometer range | Do not limit |
| The oil measurer range | Do not limit |
| Maximum power | 15W |
| Operating voltage | 8-40V |
Claims (4)
1, the hardware system structure of intellectualized full-graphics automobile instrument, form by microprocessor ARM and on-site programmable gate array FPGA, wherein ARM is used for data acquisition and system's control, FPGA is used for video processing and graphic describing shows, it is characterized in that: the signalling methods between FPGA and the ARM is communication of IIC mode or shared drive mode, the FPGA module is played the part of the SRAM SRAM external device of arm processor by the AVALON/SRAM bridge, the image data that arm processor is sent is stored in the synchronous DRAM SDRAM, instruction promotes to show drawing array VGA telltale according to arm processor, finishes the multilayer aliasing and shows, picture-in-picture shows or the line drawing function that stipples.
2, the hardware system structure of intellectualized full-graphics automobile instrument according to claim 1, it is characterized in that: described ARM is by hardware layer, the hardware driving layer, hardware abstraction layer, operating system layer, application layer is formed, wherein hardware layer is the hardware platform of whole embedded OS and application program operation, by concrete chip, module, electronic component constitutes, the hardware driving layer is used for these hardware resources of direct drive, the hardware driving layer comprises the expansion serial ports, IIC, main frame Peripheral Interface HPI and chip internal hardware resource, its role is to the hardware details of the system that hides, provide software interface hardware operation to upper layer module; Hardware abstraction layer encapsulates the register manipulation of hardware driving layer, provides the service of hardware being carried out after abstract to operating system layer and application layer by the hardware abstraction layer interface; When operating system layer or application layer use hardware abstraction layer API to design, as long as hardware abstraction layer API can realize on lower floor's hardware platform that the code of operating system layer and application layer just can be transplanted easily so; Operating system layer is by calling the interface of hardware abstraction layer, realize its function as the operation platform of the system platform of managing software and hardware resources and user's control algorithm, and the running and the behavior of application layer control system on the platform of operating system, to realize various concrete functions and application.
3, the hardware system structure of intellectualized full-graphics automobile instrument according to claim 1, it is characterized in that: described FPGA internal module is divided into the soft core module of NIOS2, AVALON/SRAM interface module, SDRAM driver module, ram in slice module, configuration device interface module, VGA driver module, is coupled together by the AVALON bus between each module.
4, realize the method for intellectualized full-graphics automobile instrument, carry out according to the following steps:
1) signals of vehicles collection: ARM comes in various signals of vehicles collections, and the signals of vehicles collection comprises that the AD of vehicle speed pulse collection, tacho-pulse collection, oil mass water temperature gathers, the on-off signal collection;
2) signal condition: with data processing algorithm to vehicle speed pulse, the rotational speed pulse signal of gather analyze, conditioning, optimization process;
3) signal is given FPGA by protocol transmission: the signal after handling according to self-defining host-host protocol, is transferred to FPGA by iic bus;
4) analytic signal: after FPGA receives signal, concrete signal content is parsed according to self-defining host-host protocol;
5) graphic describing comprises that pointer is drawn, icon is drawn: the image data that FPGA sends arm processor is stored in the synchronous DRAM SDRAM, instruction promotes the VGA telltale according to arm processor, finish the demonstration of multilayer aliasing, picture-in-picture demonstration or the line drawing function that stipples, processing through pointer bitmap compression storage algorithm and pointer rotation and vision optimization algorithm, with the icon display of representing the pointer of rotating speed, the speed of a motor vehicle and various switching values on VGA telltale or liquid crystal display, and realization and signals of vehicles accurately synchronously.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810047958A CN100586768C (en) | 2008-06-11 | 2008-06-11 | Hardware system structure of intellectualized full-graphics automobile instrument |
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| CN104134432B (en) * | 2014-08-04 | 2016-10-12 | 浪潮(北京)电子信息产业有限公司 | A kind of vehicle-mounted LCD control device and method |
| US10191738B1 (en) * | 2015-07-27 | 2019-01-29 | Invensense, Inc. | Systems and methods for interfacing a sensor and a processor |
| CN106339258B (en) * | 2016-08-10 | 2019-10-18 | 西安诺瓦星云科技股份有限公司 | The management method and device of programmable logic device and microprocessor shared drive |
| CN106597920B (en) * | 2016-11-16 | 2019-07-26 | 西安电子科技大学 | Control system based on NIOS embeded processor control HPI interface |
| CN106840255A (en) * | 2017-01-17 | 2017-06-13 | 南京蓝钰信息科技有限公司 | A kind of RS232 serial ports based on FPGA technology turns VGA image display devices |
| CN108508882A (en) * | 2017-02-28 | 2018-09-07 | 郑州宇通客车股份有限公司 | A kind of vehicle assistant drive control platform |
| CN107943602A (en) * | 2017-12-15 | 2018-04-20 | 北京数码视讯科技股份有限公司 | Hardware abstraction plateform system and equipment based on AVS2 codings |
| CN110138847A (en) * | 2019-04-30 | 2019-08-16 | 广东利通科技投资有限公司 | Wisdom traffic communication station and communication system |
| CN110677398A (en) * | 2019-09-20 | 2020-01-10 | 成都艾克赛特信息科技有限公司 | AC and GC integrated communication protocol, communication system and method for full liquid crystal instrument |
| CN110733417A (en) * | 2019-09-30 | 2020-01-31 | 惠州市德赛西威汽车电子股份有限公司 | vehicle-mounted Bluetooth communication overtime alarm method and system thereof |
| CN111221464B (en) * | 2019-12-24 | 2023-05-02 | 太原航空仪表有限公司 | Aviation instrument graphic processing module and method |
| CN111347892A (en) * | 2020-05-09 | 2020-06-30 | 盐城安心转运医疗科技有限公司 | Shared new energy medical vehicle |
| CN111833470A (en) * | 2020-06-11 | 2020-10-27 | 深圳市金溢科技股份有限公司 | Software architecture design method and system for vehicle-mounted unit |
| CN112085645B (en) * | 2020-09-07 | 2024-06-21 | 欧科佳（上海）汽车电子设备有限公司 | Image acceleration realization method based on embedded processor |
| CN112765018B (en) * | 2021-01-12 | 2022-09-13 | 武汉光庭信息技术股份有限公司 | Instrument and meter debugging system and method |
| CN114475246B (en) * | 2021-12-31 | 2024-03-26 | 浙江零跑科技股份有限公司 | Intelligent cabin instrument display system with display protection and display method |
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