CN101346037B - Multi-layer substrate and manufacturing method thereof - Google Patents
Multi-layer substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN101346037B CN101346037B CN200710136874XA CN200710136874A CN101346037B CN 101346037 B CN101346037 B CN 101346037B CN 200710136874X A CN200710136874X A CN 200710136874XA CN 200710136874 A CN200710136874 A CN 200710136874A CN 101346037 B CN101346037 B CN 101346037B
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- base plate
- multilager base
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a multilayer base board and the manufacturing method thereof. The method comprises: using a carrier plate and forming several dielectric layers and several metallic circuit layers on the carrier board. The dielectric layers which are sticky to each other are formed by coating, and the metallic circuit layers are embedded into corresponding dielectric layers respectively. Comparing with the current technology which must use film for hot pressing and jointing every different material layer, the manufacturing method in the invention has the advantages of less manufacturing processes, less material kind and no film using, improves the whole manufacturing quality good percent, satisfies multilayer base board mechanicalness matching and reduces manufacturing process cost. In addition, the multilayer base board having a thin dielectric layer of the invention can satisfy multilayer base board impedance matching, reduces crosstalk effect and keep signal integrity.
Description
[technical field]
The invention relates to a kind of multilager base plate and manufacture method thereof, and particularly relevant for a kind of soft multilager base plate and manufacture method thereof.
[background technology]
Please refer to Fig. 1, is prior art is made a multilager base plate with hot pressing, laminating type rough schematic.Prior art is mainly made multilager base plate with two-sided hot pressing, laminating type.At first, prior art provides the central layer 100 (core) that a top layer has copper foil layer 102, to copper foil layer 102 expose, processing procedure such as development forms copper foil layer 102 with pattern (the metallic circuit layer that uses as transmission signals).Then, coincide alternately again another film (prepreg) 104, form another central layer 100 and the another film 104 of metallic circuit, after this film 104 is repeatedly gone up outermost another copper foil layer 102, again multilager base plate is carried out high temperature hot pressing, to outermost copper foil layer 102, expose, processing procedure such as development to be to form the circuit patterns at outermost copper foil layer 102.Then, form a welding resisting layer 106 (solder mask) with coating method thereon again.
Above-mentioned prior art of making multilager base plate with hot pressing, laminating type, the unlike material interlayer all need have film 104 to fit mutually, and because the complexity of circuit design now, make various necessary coordinating operations, for example: boring, plating hole, etching, clean, various processing procedures such as grinding, melanism processing, and the necessary pre-treatment of aforementioned various processing procedures etc., make that existing processing procedure is complicated and need use multiple composite material, for example: central layer 100, film 104 and welding resisting layer 106 with copper foil layer 102.Therefore,, cause the reduction of the whole fine ratio of product of multilager base plate, more cause processing procedure quality and manufacturing cost wayward more owing to material is assorted not only easily because of the wherein failure of single processing procedure.
In addition, the trend toward miniaturization of electronic product is to be must developing of can not keeping off now, however the limit that the multilager base plate of aforementioned hot pressing, laminating type making but has its size to dwindle.With regard to prior art, central layer thickness is about 100 μ m, and film thickness is about 50 μ m, and therefore, the finished product thickness of 8 layer multi-layer substrates promptly is approximately about 600 μ m.And the material of dielectric layer in the prior art (it is defined as any material between two copper foil layers) is various, the material of central layer and film is composite material, and electrically (as: dielectric constant Dk), mechanicalness (as: thermal coefficient of expansion CTE) etc. all have the problem that coupling is difficult for.
And, when the thickness of the dielectric layer of prior art also will cause therebetween metallic circuit transmission signals, because of the distance of itself and adjacent metal circuit and suitable with the distance of reference potential layer (Reference Plane), even nearer (in theory, any metallic circuit and adjacent metal circuit are far away more, near more with the distance of reference potential layer is preferable), the transmission signals that then is subject to other metallic circuit disturbs, make the electric field of the metallic circuit transmission signals of mutual vicinity, electrically influence each other, cause signal integrity not good, as: crosstalking during high density band line (Stripline) transmitting high-frequency signal, the stray inductance of via (Via) and the high-frequency noise due to the electric capacity and reverse coupled are disturbed serious problems such as (Backward Coupling).
With regard to transmitting high-frequency signal, the purpose that the present invention makes the thin layer dielectric layer mainly contains 3: the loop area that (1) signal transmitting path and return flow path form is little, is not subject to other signal and disturbs.Crosstalking when (2) reducing high density band line transmitting high-frequency signal, and promote wiring density.(3) via shortens, and can reduce the high-frequency noise that its stray inductance and electric capacity cause.
Industry has when signal transmits mutually between different product when making multilager base plate, and product is used for the metallic circuit of transmission signals separately preferably can the consideration of same impedance that is so-called " impedance matching ".Reason is if the metallic circuit of different product has different impedances, when the signal of transmission suffers from the metallic circuit connecting interface of different impedances, can produce reflex components and incident composition, causes the destroy integrity of signal.Therefore, when making multilager base plate, all have a default impedance matching.
Please in the lump with reference to figure 2 and Fig. 3, Fig. 2 illustrates the profile that a metallic circuit is positioned at a thin dielectric layer.Fig. 3 illustrates in the multilager base plate of Fig. 2, is matched impedance value and the metallic circuit and the ground plane distance/metallic circuit width (H of the metallic circuit of ground connection with the adjacent metal
1/ W) graph of a relation.Metallic circuit 201 among Fig. 2 is positioned at a dielectric layer, and the dielectric coefficient of dielectric layer is assumed to be ε
r, metallic circuit 201 width are W, highly are T, are respectively H with the distance of contiguous up and down metal level (visual below contiguous metal level be ground connection)
2And H
1Fig. 3 is the matched impedance correlation values of metallic circuit 201 in the presentation graphs 2 then
With ratio H
1Relation between/W.Therefore, for cooperating aforementioned predefined matched impedance value and predetermined H
1/ H
2During value, H
1/ W must only have unique solution.
Therefore, be the littler multilager base plate of manufactured size, but still will satisfy under the prerequisite of preset matching impedance H
1Value is littler, that is medium thickness is thinner.
Please in the lump with reference to figure 4 and Fig. 5, Fig. 4 illustrates the profile that parallel number of metal circuit is positioned at a thin dielectric layer.When Fig. 5 illustrated multilager base plate designed among Fig. 4 and metallic circuit transmitting high-frequency signal, reverse coupled was disturbed in the signal cross-talk to metallic circuit and ground plane distance/metallic circuit thickness (H
1/ S) graph of a relation.Metallic circuit 401,402,403 among Fig. 4 is positioned at a dielectric layer, and the dielectric coefficient of dielectric layer is assumed to be ε
r, be example with metallic circuit 402: its width is W, and thickness is T, and line-spacing is S, is respectively H with the distance of contiguous up and down metal level (being considered as ground connection)
2And H
1C
10, C
20, C
30,-C
12,-C
13,-C
23Parasitic capacitance between the expression plain conductor.The signal that metallic circuit 401 is transmitted can disturb near its terminal aforementioned reverse coupled that produces metallic circuit 402, can following approximate formula represent:
V
21≈ b
21[V
0(t)-V
0(t-2 τ D)] (the 1st formula)
b
21≈ 0.25 (C
21/ C
22+ L
21/ L
11) (the 2nd formula)
V
0(t) be the signal voltage of plain conductor 401 terminal inputs, τ D represents the distance that signal has been walked, L on plain conductor 401
21And L
11The expression stray inductance.The 1st formula is represented the signal cross-talk of meeting generation and the typical value V that reverse coupled is disturbed
21Approximately with coefficient b
21Be directly proportional.Fig. 3 represents b
21With ratio H
1The relation that is directly proportional between/S.Therefore, be under the prerequisite of default value H as line-spacing S and live width W
1Value littler (being that medium thickness is thin more), b
21Littler, that is the influence of signal cross-talk and reverse coupled interference is also little, 402 transmission signals of metallic circuit are also just complete, about this crosstalks, reverse coupled is disturbed and the stray inductance of via and the part that electric capacity causes high-frequency noise, further at length discuss the collected works that are found in IBM J.RES.DEVEL OP.VOL.32NO.5SEPTEMBER 1988.
Generally speaking, medium thickness is thinner, can not only be under the requirement that meets the multilager base plate impedance matching, the influence that signal cross-talk when further reducing the multilager base plate transmitting high-frequency signal and reverse coupled are disturbed, simultaneously because dielectric layer is thin, via is shortened, reduce the high-frequency noise that its stray inductance and electric capacity cause.
Moreover, when making high density even soft multilager base plate, must consider emphatically further that also mechanicalness (as: thermal coefficient of expansion CTE), warpage, interior external carbuncle etc. are to the influence that multilager base plate produced and the restriction of thickness, and prior art kind layer material is totally different various, mechanical property coupling difficulty, even final product thickness to each other is excessive and influence soft character.
Therefore, it is all few than prior art to develop a no film, processing procedure number, material category, and can make the multilager base plate that has with the thin layer dielectric layer of the thickness of metallic circuit coupling, can solve the shortcoming of aforementioned prior art, improve whole workmanship of multilager base plate and yield, reduce the processing procedure cost.Simultaneously, also can satisfy the multilager base plate microminiaturization, when particularly soft multilager base plate is microminiaturized, keep signal integrity excellent electrical property demand.
[summary of the invention]
Main purpose of the present invention is to provide a kind of multilager base plate and manufacture method thereof, and its material category is few, and material is electrical, the mechanical property coupling, and processing procedure is simple, more is applicable to and makes soft multilager base plate.
Another object of the present invention is to provide a kind of multilager base plate and manufacture method thereof, its material category is few, and dielectric layer is thin, under the consideration prerequisite of impedance matching, the metallic circuit of multilager base plate is had keep the good characteristic of signal integrity.
For reaching aforementioned purpose of the present invention, multilager base plate of the present invention utilizes a support plate, forms some dielectric layer and number of metal line layer on this support plate.Dielectric layer coheres mutually, makes the metallic circuit layer distinctly be embedded in those corresponding dielectric layers.Dielectric layer of the present invention is to form with coating method, with the number of metal line layer of formation such as etching, electroforming or photoresistance stripping means, in order to transmission signals.And dielectric layer is carried out etching or other perforate processing procedure to make via, in order to link the adjacent metal line layer in the precalculated position.And the dielectric layer that is positioned at multi-layer substrate surface then can be used as welding resisting layer and uses after making via.All need there be film to fit mutually compared to prior art hot pressing, each interlayer of laminating type, the multilager base plate processing procedure number that the present invention makes is few, material is simple, and need not use film, can improve whole workmanship of multilager base plate and yield, reduce the processing procedure cost.
Manufacture method according to multilager base plate of the present invention, the medium thickness that forms also can significantly dwindle compared to prior art, be approximately about 600 μ m compared to the finished product thickness of making 8 layer multi-layer substrates with prior art, multilager base plate individual layer dielectric layer of the present invention can reach below the 10 μ m, the finished product thickness of 8 layer multi-layer substrates is 80～90 μ m approximately only, even littler.And, multilager base plate of the present invention is when size is dwindled, because the thin layer dielectric layer of made, can not only satisfy the consideration of multilager base plate impedance matching, signal cross-talk in the time of more reducing high density band line (Stripline) transmitting high-frequency signal, the integrality that keeps institute's transmission signals promotes wiring density.
For above and other objects of the present invention, feature and advantage can be become apparent, cooperate appended graphicly, be described in detail below:
[description of drawings]
Fig. 1 is prior art is made a multilager base plate with hot pressing, laminating type a rough schematic;
Fig. 2 illustrates the profile that a metallic circuit is positioned at a thin dielectric layer;
Fig. 3 illustrates in the multilager base plate of Fig. 2, is matched impedance value and the metallic circuit and the ground plane distance/metallic circuit width (H of the metallic circuit of ground connection with the adjacent metal
1/ W) graph of a relation;
Fig. 4 illustrates the profile that parallel number of metal circuit is positioned at a thin dielectric layer;
The middle reverse coupled of signal cross-talk (crosstalk) disturbed (Backward Coupling) to metallic circuit and ground plane distance/metallic circuit thickness (H when Fig. 5 illustrated multilager base plate designed among Fig. 4 and metallic circuit transmitting high-frequency signal
1/ S) graph of a relation; And
Fig. 6 A to 6D illustrates the flow chart of multilager base plate manufacture method of the present invention.
[embodiment]
Please refer to Fig. 6 A to Fig. 6 D, is the flow chart according to multilager base plate manufacture method of the present invention.Fig. 6 A represents to provide a support plate 600, and forms one first dielectric layer 602 on support plate 600.Fig. 6 B is illustrated on first dielectric layer 602 and forms a metallic circuit layer 604, and after it is carried out processing procedure that pattern makes, forms one second dielectric layer 606 again on these metallic circuits 604, and form a via 612 at second dielectric layer 606.Fig. 6 C is illustrated on second dielectric layer 606 and forms another metallic circuit layer 604, it is carried out processing procedure that pattern makes after, on this metallic circuit 604, form another second dielectric layer 606 and a via 614 again, constitute a multilager base plate.Fig. 6 D represents support plate 600 is separated with this multilager base plate, finishes the making of multilager base plate of the present invention.
Be positioned at first dielectric layer 602 of multi-layer substrate surface of the present invention, can be according to the needs of multilager base plate design, with support plate 600 with after this multilager base plate separates, form via 616,618, then first dielectric layer 602 can be used as welding resisting layer and uses.In addition, second dielectric layer 606 with via 614 also can be used as welding resisting layer and uses.Moreover, also can after forming first dielectric layer 602, support plate 600, behind the formation via 616,618, form the metallic circuit layer 604 of first dielectric layer, 602 tops more promptly in advance to 602 perforates of first dielectric layer.With support plate 600 with after this multilager base plate separates, first dielectric layer 602 can be used as welding resisting layer.
After the present invention formed first dielectric layer 602 and those second dielectric layers 606 with coating method, dry these dielectric layers made its sclerosis.For example be fit to coating process of the present invention: spin-coating method (spin coating), extrusion formula mould rubbing method (Extrusion Die Coating) and roller rubbing method (Roll Coating) etc.About 1～50 μ m of the wet-film thickness of spin-coating method, about 10～1000 μ m of the wet-film thickness of extrusion formula mould rubbing method, about 5～500 μ m of the wet-film thickness of roller rubbing method.Yet actual wet-film thickness mainly is the rerum natura (as: viscosity, surface tension etc.) and process parameter (as: rotating speed, extrusion amount, coating speed etc.) decision by the coating thing.But topmost drying and sclerosis processing procedure then will influence the final thickness of first dielectric layer 602 and these second dielectric layers 606.The solid content of first dielectric layer 602 and these second dielectric layers 606 will determine the thickness that it is final with the sclerosis shrinkage, and generally speaking final thickness only is 30～50% of a wet-film thickness.
Therefore, the present invention can pass through to select coating method, change the rerum natura of coating thing and the various parameters of adjustment coating process, drying and sclerosis processing procedure, forms the desired thickness of first dielectric layer 602 and these second dielectric layers 606 with decision.What deserves to be mentioned is, because the present invention can utilize two kinds of main materials to make multilager base plate basically, for example: first, second dielectric layer of the present invention can be polyimides (polyidmide) or benzocyclobutene (Bisbenzocyclobutene) etc., perhaps first, second dielectric layer also can be different materials, and the metallic circuit layer then can be copper or aluminium.So material category is few, the material mechanical characteristic is easy to coupling, and processing procedure is simple, compared to prior art, more is applicable to and makes soft multilager base plate.And can improve whole workmanship of multilager base plate and yield, reduce the processing procedure cost.
Moreover, the present invention forms these second dielectric layers 606 because of utilizing coating method, cover these metallic circuit layers 604, and make those metallic circuit layers 604 of the present invention be embedded in those second dielectric layers 606 of its correspondence, that is these metallic circuit layers 604 are embedded in these second dielectric layers 606 respectively.And thereby the material of first dielectric layer 602 and those second dielectric layers 606 can identically be cohered mutually, need not as prior art with hot pressing, when laminating type is made, the hot pressing of each layer, applying all need be used film, even can impose the processing that an interface adheres to reinforcement at first dielectric layer 602 and 606 of these second dielectric layers, for example: a plasma process is handled, and also further increases the adhesive strength between each dielectric layer.
Moreover, also because of forming these second dielectric layers 606 with coating method, the side of metallic circuit layer of the present invention be seamlessly with the second corresponding dielectric layer driving fit.In addition, for linking the adjacent metal line layer, also can make via 612,614,616,618 at first dielectric layer 602 and these second dielectric layers 606.
Therefore, as being example with 8 layer multi-layer substrates, aforementioned finished product thickness compared to prior art is approximately about 600 μ m, and the present invention can significantly dwindle the thickness of dielectric layer, and the finished product thickness that makes 8 layer multi-layer substrates is 80～90 μ m approximately only.
Under the consideration prerequisite of impedance matching, the present invention can make multilager base plate when high density band line (Stripline) transmitting high-frequency signal, reduce signal cross-talk (Crosstalk) and reverse coupled and disturb the influence of (BackwardCoupling) phenomenon, simultaneously owing to have thin dielectric layer, via (Via) is shortened, reduce the high-frequency noise that its stray inductance and electric capacity cause, and when promoting wiring density, it is good still to keep signal integrity.
Claims (20)
1. multilager base plate, comprise some dielectric layer and number of metal line layer, these dielectric layers and these metallic circuit layers are repeatedly put alternately, these dielectric layers cohere mutually, make those metallic circuit layers be embedded in those corresponding dielectric layers respectively, it is characterized in that: the material of these dielectric layers is identical.
2. multilager base plate as claimed in claim 1 is characterized in that: the material of these dielectric layers is a polyimides.
3. multilager base plate as claimed in claim 1 is characterized in that: the material of these dielectric layers is a benzocyclobutene.
4. multilager base plate as claimed in claim 1 is characterized in that: this multilager base plate also further comprises several vias, is arranged in these dielectric layers, in order to connect those metallic circuit layers.
5. multilager base plate as claimed in claim 4 is characterized in that: these dielectric layers that are positioned at this multi-layer substrate surface are to use as welding resisting layer.
6. the described multilager base plate of claim 1 is characterized in that: impose the processing that an interface adheres to reinforcement between these dielectric layers, to increase the adhesive strength between these dielectric layers.
7. the described multilager base plate of claim 6 is characterized in that: it is that a plasma process is handled that this interface adheres to intensive treatment.
8. multilager base plate as claimed in claim 1 is characterized in that: the side of these metallic circuit layers be seamlessly with those corresponding dielectric layer driving fits.
9. multilager base plate as claimed in claim 1 is characterized in that: the thickness of one of these dielectric layers is less than 100 μ m.
10. multilager base plate as claimed in claim 1 is characterized in that: these dielectric layers form with coating method.
11. a method of making multilager base plate, this method comprises the following steps:
A., one support plate is provided;
B. on this support plate, form one first dielectric layer with coating method;
C. dry this first dielectric layer makes this first dielectric layer sclerosis;
D. on this first dielectric layer, form a metallic circuit layer;
E. on this metallic circuit layer, form one second dielectric layer with coating method;
F. dry this second dielectric layer makes this second dielectric layer sclerosis; And
G. this multilager base plate is separated from this support plate.
12. method as claimed in claim 11, it is characterized in that: after step f, also comprise a step, wherein repeating step d is to step f, form these second dielectric layers and these metallic circuit layers repeatedly put alternately, these second dielectric layers cohere mutually, use so that these metallic circuit layers are embedded in these corresponding second dielectric layers respectively.
13. method as claimed in claim 12 is characterized in that: behind each step f, also comprise a step of making at least one via at this second dielectric layer, in order to connect these metallic circuit layers.
14. method as claimed in claim 12 is characterized in that: before each step e, comprise that also one imposes the step that an interface adheres to intensive treatment, to increase the adhesive strength between these second dielectric layers.
15. method as claimed in claim 14 is characterized in that: it is that a plasma process is handled that this interface adheres to intensive treatment.
16. method as claimed in claim 11 is characterized in that: before step e, comprise that also one imposes the step that an interface adheres to intensive treatment, to increase the adhesive strength between this first dielectric layer and this second dielectric layer.
17. method as claimed in claim 16 is characterized in that: it is that a plasma process is handled that this interface adheres to intensive treatment.
18. method as claimed in claim 11 is characterized in that: after step c, also comprise a step of making at least one via at this first dielectric layer, with so that this first dielectric layer as a welding resisting layer.
19. method as claimed in claim 11 is characterized in that: after step g, also comprise a step of making at least one via at this first dielectric layer, with so that this first dielectric layer as a welding resisting layer.
20. method as claimed in claim 11 is characterized in that: in step e, form this second dielectric layer on this metallic circuit layer with coating method so that the side of this metallic circuit layer seamlessly with this corresponding second dielectric layer driving fit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710136874XA CN101346037B (en) | 2007-07-11 | 2007-07-11 | Multi-layer substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710136874XA CN101346037B (en) | 2007-07-11 | 2007-07-11 | Multi-layer substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101346037A CN101346037A (en) | 2009-01-14 |
| CN101346037B true CN101346037B (en) | 2010-06-02 |
Family
ID=40247895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710136874XA Active CN101346037B (en) | 2007-07-11 | 2007-07-11 | Multi-layer substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101346037B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204244566U (en) * | 2014-11-26 | 2015-04-01 | 深圳市一博科技有限公司 | A kind of pcb board structure reducing Channel depletion |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1274256A (en) * | 1999-05-18 | 2000-11-22 | 三星电机株式会社 | Printed circuit board and its mfg. method |
| CN1131883C (en) * | 1999-10-13 | 2003-12-24 | 味之素株式会社 | Epoxy resin composition, adhesive film and preimpregnatel blank and multilayer printing circuit board |
-
2007
- 2007-07-11 CN CN200710136874XA patent/CN101346037B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1274256A (en) * | 1999-05-18 | 2000-11-22 | 三星电机株式会社 | Printed circuit board and its mfg. method |
| CN1131883C (en) * | 1999-10-13 | 2003-12-24 | 味之素株式会社 | Epoxy resin composition, adhesive film and preimpregnatel blank and multilayer printing circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101346037A (en) | 2009-01-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8277668B2 (en) | Methods of preparing printed circuit boards and packaging substrates of integrated circuit | |
| CA2160501C (en) | Laminar stackable circuit board structure and manufacture | |
| US9326377B2 (en) | Printed wiring board | |
| CN102186316B (en) | Method for manufacturing any-layer printed circuit board | |
| JP5607710B2 (en) | Printed circuit board and printed circuit board manufacturing method | |
| US20080148562A1 (en) | Method for manufacturing multilayer flexible printed circuit board | |
| TW202017451A (en) | Method of manufacturing circuit board | |
| CN113347808B (en) | Method for manufacturing multilayer circuit board with thick copper and ultra-fine circuit | |
| CN104902696A (en) | Method of manufacturing copper column on printed circuit board based on wire embedding structure | |
| US8266797B2 (en) | Method of manufacturing a multi-layer substrate | |
| KR20040061409A (en) | Two-sided PCB without via hole and the manufacturing method thereof | |
| TW201907771A (en) | Flexible circuit board and manufacturing method thereof | |
| CN102045964B (en) | Making method of circuit board | |
| TWI650049B (en) | Printed wiring board and manufacturing method for the same | |
| TWI578873B (en) | Manufacturing method of high-density multilayer board | |
| CN101346037B (en) | Multi-layer substrate and manufacturing method thereof | |
| US20140059852A1 (en) | Multi-layer printed circuit board comprising film and method for fabricating the same | |
| US20080271915A1 (en) | Method for making a circuit board and multi-layer substrate with plated through holes | |
| JP2015204309A (en) | Printed wiring board and method of manufacturing the same | |
| US6515236B2 (en) | Printed wiring board and manufacturing method of the printed wiring board | |
| CN107635349A (en) | circuit board and terminal device | |
| JP4161577B2 (en) | Electrical wiring board | |
| US20210337665A1 (en) | Multilayer printed circuit board and method for manufacturing the same | |
| JP3226494U (en) | Multilayer flexible circuit board and embedded circuit layer thereof | |
| US20030006007A1 (en) | Method of laminating copper foil onto a printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |