CN101335505B - Gain control circuit of wireless receiver - Google Patents
Gain control circuit of wireless receiver Download PDFInfo
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- CN101335505B CN101335505B CN2008101299814A CN200810129981A CN101335505B CN 101335505 B CN101335505 B CN 101335505B CN 2008101299814 A CN2008101299814 A CN 2008101299814A CN 200810129981 A CN200810129981 A CN 200810129981A CN 101335505 B CN101335505 B CN 101335505B
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Abstract
The invention relates to a gain control circuit of a wireless receiver, which comprises a plural class amplifier, an analog gain control circuit and a digital gain control circuit; wherein, an analog control voltage is generated by the analog gain control circuit and the gain of a backward-stage amplifier is regulated by the analog gain control circuit in an analog way; a plurality of gain curves operated between a first preset voltage and a second preset voltage of a forestage amplifier are established by the digital gain control circuit; when the analog control voltage exceeds the first preset voltage or the second preset voltage, the switch between the gain curves is carried out; therefore, the digital gain control can be added into the analog gain control for enhancing the degree of linearity on the gain regulating and reducing instantaneous reaction generated during the gain switching.
Description
Technical field
The present invention relates to a kind of gain control circuit of wireless receiver, in analog gain control, add digital gain control, can improve the linearity that gain is adjusted, and reduce the transient response that is produced when gain is switched.
Background technology
The gain control circuit of wireless receiver can change Amplifier Gain according to the size of input signal in order to reach the demand of high dynamic range.So when little input signal, gain control circuit will use the high-gain amplification input signal, otherwise, when big input signal, use low gain to dwindle input signal, be beneficial to demodulator demodulation subsequently whereby.
Existing gain control circuit can select to adopt analog gain control mode or digital gain control mode to adjust each gain stage Amplifier Gain.Adopt the gain control circuit switched amplifier gain lentamente of analog form, slowing down the generation of transient response, and avoid having influence on the signal quality of input signal.
Yet, adopt analog form control, when adjusting, gain must carry out mutual consideration, to avoid on gain is adjusted, producing mistake for the radio frequency specification of amplifiers at different levels.Therefore, the amplifier that the radio frequency specification is more rigorous, for example: low noise amplifier, adopt analog form to adjust amplifier gain and will enter the operating area of inelastic region easily, make the gain amplifier of input signal not reach the requirement of the linearity, and then wireless receiver can't operate in optimized operating state.
Adopt the gain control circuit of digital form for the linearity that improves amplifier gain, the radio frequency specification that when gain is adjusted, does not need to consider other gain stage amplifier, and can carry out each gain stage Amplifier Gain adjustment individually according to the radio frequency specification of each gain stage amplifier, whereby to obtain the wireless receiver of a preferable linearity.
Yet, the control of employing digital form, often once just gain is switched to desired gain size, so, in the process that increases or downgrade gain significantly, input signal will present a relatively fiercer transient response easily, and have influence on the signal quality of input signal, and can increase the degree of difficulty of demodulator demodulation input signal.Therefore, existing pure analog form of gain control circuit or pure digi-tal mode are regulated and control each gain stage Amplifier Gain and are all had its advantage and disadvantage.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of gain control circuit of wireless receiver, mainly adjust amplifier gain with the analog gain control mode, and in the more rigorous amplifier of radio frequency specification, add the digital gain control mode, to improve the linearity of amplifier gain when adjusting.
Another technical problem that the present invention will solve is to provide a kind of gain control circuit of wireless receiver, digital gain control circuit is formulated multistage layer gain curve, and each stratum's gain curve operates in the identical voltage section, can reduce the quantity that is provided with of comparator in the digital gain control circuit, to reduce the cost of hardware circuit.
The another technical problem that the present invention will solve is to provide a kind of gain control circuit of wireless receiver, digital gain control circuit is formulated multistage layer gain curve, and when gain is switched, selecting single order to follow single order switches, little by little to switch to suitable gain size, so can avoid once just gain being switched to desired gain size, and produce the transient response of a fierceness.
In order to solve the problems of the technologies described above, the invention provides a kind of gain control circuit of wireless receiver, its characteristics are that its structure includes: casacade multi-amplifier, include at least one pre-amplifier and a plurality of post-amplifier, these a plurality of post-amplifiers connect this pre-amplifier; One analog gain control circuit connects this a plurality of post-amplifiers, in order to producing an analog control voltage, and adjusts the gain of these a plurality of post-amplifiers with an analog form according to this analog control voltage; An and digital gain control circuit, connect this analog gain control circuit and this pre-amplifier, in order to receive this analog control voltage, and make the gain curve of multistage layer for this pre-amplifier, these a plurality of gain curves are operating between one first predeterminated voltage value and the one second predeterminated voltage value, when this analog control voltage exceeds voltage section between this first predeterminated voltage value and this second predeterminated voltage value, just can carry out the switching between the different gains curve.
Above-mentioned gain control circuit, its characteristics are that this analog control voltage switches to next stratum's gain curve when being higher than this second predeterminated voltage value, and this analog control voltage switches to stratum's gain curve when being lower than this first predeterminated voltage value.
Above-mentioned gain control circuit, its characteristics are, this digital gain control circuit includes: an analog-digital converter, in order to receive this analog control voltage and a reference voltage, and in this reference voltage, take out this first predeterminated voltage value and this second predeterminated voltage value, and set out a plurality of voltage quasi positions between this first predeterminated voltage value and this second predeterminated voltage value, this analog control voltage compares with each voltage quasi position respectively, produces a digital signal with correspondence; And a digitial controller, connect this analog-digital converter, receiving this digital signal, and carry out the switching of this gain curve according to this digital signal.
Above-mentioned gain control circuit, its characteristics are that this digitial controller will be made the gain curve of this multistage layer for this pre-amplifier, and switch to the gain curve of a last stratum or the gain curve of next stratum according to this digital signal with decision.
Above-mentioned gain control circuit, its characteristics are that this digitial controller is taken a sample to this digital signal that this analog-digital converter produced in each work period.
Above-mentioned gain control circuit, its characteristics are that this analog-digital converter includes: a plurality of first resistors connect in the mode of connecting, and form a load voltage on first resistors of series connection; One first voltage buffer connects one first contact of first resistor of this series connection, and produces this first predeterminated voltage value on this first contact; One second voltage buffer connects one second contact of first resistor of this series connection, and produces this second predeterminated voltage value on this second contact; A plurality of second resistors are connected the output of this first voltage buffer and this second voltage buffer with series system, and produce a plurality of voltage quasi positions; And a plurality of comparators, connect corresponding voltage quasi position and this analog control voltage respectively, and produce this digital signal by the comparative result of this voltage quasi position and this analog control voltage.
Above-mentioned gain control circuit, its characteristics are, are connected with a reference voltage and an earth terminal on first resistor of this series connection.
Above-mentioned gain control circuit, its characteristics are that this analog-digital converter is a flash type analog-digital converter.
Above-mentioned gain control circuit, its characteristics be, this analog gain control circuit is in order to receiving an index signal, and produce this analog control voltage according to this index signal.
Above-mentioned gain control circuit, its characteristics are that this index signal is produced by a signal indicator, and this signal indicator is incorporated in a fundamental frequency chip, an intermediate-frequency circuit or the zero intermediate frequency circuit.
The present invention also provides a kind of gain control circuit of wireless receiver, and its characteristics are that its primary structure includes: casacade multi-amplifier, include at least one pre-amplifier and a plurality of post-amplifier, and these a plurality of post-amplifiers connect this pre-amplifier; One analog gain control circuit connects this a plurality of post-amplifiers, in order to producing an analog control voltage, and adjusts the gain of these a plurality of post-amplifiers with an analog form according to this analog control voltage; An and digital gain control circuit, connect this analog gain control circuit and this pre-amplifier, in order to receive this analog control voltage, and make multistage layer gain curve for this pre-amplifier, these a plurality of gain curves all operate between one first predeterminated voltage value and the one second predeterminated voltage value, to include a plurality of voltage sections between this first predeterminated voltage value and this second predeterminated voltage value, each gain curve operates in respectively in the different voltage sections, when this analog control voltage exceeds the pairing voltage section of each gain curve, just carry out the switching of different gains curve, and the two adjacent operated voltage sections of gain curve there is section partly to overlap.
Above-mentioned gain control circuit, its characteristics are that described each voltage section includes one first critical voltage value and one second critical voltage value respectively.
Above-mentioned gain control circuit, its characteristics are, this analog control voltage switches to the gain curve of next stratum when being higher than pairing this second critical voltage value of this gain curve, and this analog control voltage switches to the gain curve of a stratum when being lower than pairing this first critical voltage value of this gain curve.
Above-mentioned gain control circuit, its characteristics are, this digital gain control circuit includes: an analog-digital converter, in order to receive this analog control voltage and a reference voltage, and in this reference voltage, take out this first predeterminated voltage value and this second predeterminated voltage value, and be set with a plurality of voltage quasi positions between this first predeterminated voltage value and this second predeterminated voltage value, this analog control voltage compares with each voltage quasi position respectively, produces a digital signal with correspondence; And a digitial controller, connect this analog-digital converter, receiving this digital signal, and carry out the switching of this gain curve according to this digital signal.
Above-mentioned gain control circuit, its characteristics are that this digitial controller will be made the gain curve of this multistage layer for this pre-amplifier, and switch to the gain curve of a last stratum or the gain curve of next stratum according to this digital signal with decision.
Above-mentioned gain control circuit, its characteristics are that this digital gain control circuit includes stratum's register, and this stratum's register is in order to write down the operated stratum of present gain curve.
Above-mentioned gain control circuit, its characteristics are that this analog-digital converter includes: a plurality of first resistors connect in the mode of connecting, and form a load voltage on first resistors of series connection; One first voltage buffer connects one first contact of first resistor of this series connection, and produces this first predeterminated voltage value on this first contact; One second voltage buffer connects one second contact of first resistor of this series connection, and produces this second predeterminated voltage value on this second contact; A plurality of second resistors are connected the output of this first voltage buffer and this second voltage buffer with series system, and produce a plurality of voltage quasi positions; And a plurality of comparators connect corresponding voltage quasi position and this analog control voltage respectively, and produce this digital signal by the comparative result of this voltage quasi position and this analog control voltage.
Above-mentioned gain control circuit, its characteristics are, are connected with a reference voltage and an earth terminal on first resistor of this series connection.
Above-mentioned gain control circuit, its characteristics are that this analog-digital converter is a flash type analog-digital converter.
Above-mentioned gain control circuit, its characteristics be, this analog gain control circuit is in order to receiving an index signal, and produce this analog control voltage according to this index signal.
Above-mentioned gain control circuit is characterized in that, this index signal is produced by a signal indicator, and this signal indicator is incorporated in a fundamental frequency chip, an intermediate-frequency circuit or the zero intermediate frequency circuit.
Technology effect of the present invention is:
1) mainly adjusts amplifier gain, and in the more rigorous amplifier of radio frequency specification, add the digital gain control mode, the linearity when improving the amplifier gain adjustment with the analog gain control mode.
2) digital gain control circuit is formulated multistage layer gain curve, and each stratum's gain curve operates in the identical voltage section, reduces the quantity that is provided with of comparator in the digital gain control circuit, thereby reduces the cost of hardware circuit.
3) digital gain control circuit is formulated multistage layer gain curve, and when gain is switched, select single order to follow single order and switch, little by little to switch to suitable gain size, so avoid once just gain being switched to desired gain size, and produce the transient response of a fierceness
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the block schematic diagram of gain control circuit one preferred embodiment of wireless receiver of the present invention;
Fig. 2 is the gain curve schematic diagram of digital gain control circuit of the present invention;
Fig. 3 is the block schematic diagram of digital gain control circuit of the present invention;
Fig. 4 is the circuit connection diagram of analog-digital converter of the present invention;
Fig. 5 is the block schematic diagram of the another embodiment of gain control circuit of wireless receiver of the present invention;
Fig. 6 is the gain curve schematic diagram of digital gain control circuit of the present invention;
Fig. 7 is for being the block schematic diagram of digital gain control circuit of the present invention;
Fig. 8 is the circuit connection diagram of analog-digital converter of the present invention.
Wherein, Reference numeral:
100 wireless receivers, 10 antennas
11 pre-amplifiers, 13 post-amplifiers
20 analog gain control circuits, 30 digital gain control circuits
31 analog-digital converters, 311 first resistors
312 first voltage buffers, 313 second resistors
314 second voltage buffers, 315 comparators
33 digitial controllers, 41 gain ladders
411 nodes, 413 nodes
43 gain ladders, 500 wireless receivers
50 digital gain control circuits, 51 analog-digital converters
511 first resistors, 512 first voltage buffers
513 second resistors, 514 second voltage buffers
515 comparators, 53 digitial controllers
55 stratum's registers, 551 stratum's data
61 gain ladders, 611 nodes
613 nodes, 63 gain ladders
700 fundamental frequency chips, 701 signal indicators
Embodiment
At first, see also Fig. 1 and Fig. 2, be respectively the block schematic diagram of gain control circuit one preferred embodiment of wireless receiver of the present invention and the gain curve schematic diagram of digital gain control circuit.As shown in the figure, wireless receiver 100 primary structures include casacade multi-amplifier 11/13, an analog gain control circuit 20 and a digital gain control circuit 30.
Amplifier includes at least one pre-amplifier 11 and a plurality of post-amplifier 13.Pre-amplifier 11 can be a low noise amplifier (LNA), then level amplifier 13 can be an intermediate frequency amplifier (IFA) and/or a power amplifier (PA), and post-amplifier 13 connects pre-amplifier 11, whereby, the action that amplifiers 11/13 at different levels will gain for the input signal that antenna 10 is received and adjust, wherein input signal can be a radio frequency or analog signal.
Analog gain control circuit 20 connects each post-amplifier 13, and in order to receive an index signal, wherein index signal is produced by a signal indicator 701, and signal indicator 701 can be incorporated in a fundamental frequency chip 700, an intermediate-frequency circuit or the zero intermediate frequency circuit.
Generally speaking, wireless receiver 100 can determine the fiducial value of a fixed amplitude, and signal indicator 701 will be according to this fiducial value, the gain amplifier of judging wireless receiver 100 is too high or too low, and produce the reverse index signal of size, with the adjustment that gains in the opposite direction of notice wireless receiver 100, and make input signal dwindle or be amplified to the amplitude size of this fiducial value.
Analog gain control circuit 20 is in order to receiving this index signal, and according to index signal to produce an analog control voltage (VAGC), wherein analog control voltage (VAGC) is adjusted the gain size of post-amplifier 13 with analog form.
Digital gain control circuit 30 connects simulation gain control circuit 20 and pre-amplifier 11, in order to receive the analog control voltage (VAGC) that analog gain control circuit 20 is produced, and make the gain curve of multistage layer for pre-amplifier 11, for example: Gain1～4, and be set with one first predeterminated voltage value V0 and one second predeterminated voltage value V4.
The gain curve of each stratum operates in overlapping between the first predeterminated voltage value V0 and the second predeterminated voltage value V4, as shown in Figure 2, when analog control voltage (VAGC) exceeds voltage section between the first predeterminated voltage value V0 and the second predeterminated voltage value V4, digital gain control circuit 30 just can carry out the change action between the different gains curve, adjusts the gain size of this pre-amplifier 11 whereby with digital form.
In embodiments of the present invention, with analog form as main gain adjustment, and in the gain section of wireless receiver 100 (for example: 80db) (for example: take out a bit of interval 12db) as the adjustment section of digital gain control.Carry out the adjustment of amplifier gain so as to analog form collocation digital form, can avoid only using analog form to adjust amplifier gain and enter the operating area of inelastic region easily, the linearity of adjusting with the gain that improves wireless receiver 100.
See also Fig. 2 and Fig. 3, be respectively the gain curve schematic diagram and the block schematic diagram of digital gain control circuit of the present invention.As shown in the figure, digital gain control circuit 30 includes an analog-digital converter 31 and a digitial controller 33, and wherein analog-digital converter 31 is in order to receive an analog control voltage (VAGC) and a reference voltage Vref and to export a digital signal D.
Analog-digital converter 31 takes out the first predeterminated voltage value V0 and the second predeterminated voltage value V4 in the reference voltage Vref that is received, and between the first predeterminated voltage value V0 and the second predeterminated voltage value V4, be set with a plurality of voltage quasi position V0, V1, V2, V3 and V4 ... Deng, analog control voltage (VAGC) compares with each voltage quasi position respectively, produces a digital signal D with correspondence.Wherein analog-digital converter 31 can be the analog-digital converter (Flash ADC) of a flash type.
Digitial controller 33 connects analog-digital converters 31, in order to receiving digital signals D, and carries out the change action of gain curve according to digital signal D.In addition, digitial controller 33 will be made the gain curve of this multistage layer for pre-amplifier 11, to determine to switch to the gain curve of a last stratum or next stratum according to digital signal D.
See also Fig. 2 and Fig. 4, be respectively the gain curve schematic diagram of digital gain control circuit of the present invention and the circuit connection diagram of analog-digital converter.As shown in the figure, analog-digital converter 31 includes a plurality of first resistors 311, one first voltage buffer 312, one second voltage buffer 314, many second resistors 313 and a plurality of comparator 315.
Each first resistor 311 is provided with in the mode of series connection, and forms a load voltage V on first resistor 311 of series connection
D, for example be connected with a reference voltage and an earth terminal on Chuan Lian first resistor 311.First voltage buffer 312 is connected to the first contact X1 on first resistor 311 of series connection, (for example: 0.99V) to receive the first predeterminated voltage value V0 that produced on the first contact X1.314 of second voltage buffers are connected to the second contact X2 on first resistor 311 of series connection, (for example: 1.18V) to receive the second predeterminated voltage value V4 that produced on the second contact X2.
Each second resistor 313 is provided with and is connected in the output of first voltage buffer 312 and second voltage buffer 314 in the mode of series connection, and produces a plurality of voltage quasi positions, for example: V0～V4.
And each comparator 315 connects corresponding voltage quasi position and analog control voltage (VAGC) respectively, and the voltage quasi position and the analog control voltage (VAGC) of correspondence compared, to export a comparison value respectively, for example: D
4～D
0, wherein with each comparison value D
4～D
0Form digital signal D.
In addition, between the first predeterminated voltage value V0 and the second predeterminated voltage value V4, a plurality of voltage quasi position V0, V1, V2, V3 and V4 will be arranged ... Deng, but the also accurate position of switching of representative simulation digital quantizer 31 of this voltage quasi position.
Present embodiment digital gain control mode has switch mode and a switch mode that up gains that down gains.Switch mode down gains: the gain curve that will switch to next stratum when analog control voltage (VAGC) is higher than the second predeterminated voltage value V4.Switch mode up gains: the gain curve that will switch to a last stratum when analog control voltage (VAGC) is lower than the first predeterminated voltage value V0.Therefore, down the gain switching reaches up gain switching with having different gain switching points respectively, to form a hesitation.
When the wireless receiver 100 of present embodiment receives a bigger input signal, signal indicator 701 will notify analog control voltage (VAGC) that analog gain control circuit 20 produced toward the direction adjustment that gains and diminish.
If analog control voltage (VAGC) is through the conversion of four voltage quasi positions (behind the V0 → V4), and when being higher than the second predeterminated voltage value V4, the state of the digital signal D that analog-digital converter 31 is exported will be (11111), and digitial controller 33 can directly down switch present gain curve according to digital signal (11111), for example in the present embodiment, digital gain control circuit 30 operates on the gain curve Gain1 at the beginning, and down switch to Gain2 by gain curve Gain1, make the gain of pre-amplifier 11 down adjust a gain ladder 41.
After gain was down switched suddenly, the signal indicator 701 of fundamental frequency chip 700 was controlled voltage (VAGC) with instruction simulation and is moved toward the direction that the gain ladder 41 of offsetting numeral changes.In other words, Gain1 → Gain2 representative reduces the action of gain, and then signal indicator 701 will move toward the direction that increases gain by instruction simulation control voltage (VAGC), to offset the change in gain amount of gain ladder 41.
After a work period, for example: the loop time of the gain controlling of wireless receiver 100, if the result that the digital signal D of 33 pairs of analog-digital converters of digitial controller, 31 outputs takes a sample still is (11111), the amount of downgrading of i.e. expression gain is not enough, and must continue to switch to next gain curve Gain2 → Gain3 of stratum.
When digital signal D is not (11111), for example: on the node 411 and relative digital signal is (11110), or switched to the gain curve of last stratum, for example: Gain4, digital gain control circuit 30 just can stop the action that to gain and down switch for pre-amplifier 11.
Because digital gain control circuit 30 designs of the present invention have the function of a sluggishness, therefore at analog control voltage (VAGC) during not less than the first predeterminated voltage value V0, digital gain control circuit 30 just can not increase switching for gain curve, avoiding digital gain constantly to switch, and cause the wireless receiver 100 can't receiving and transmitting signal.
On the contrary, when input signal changed a less input signal into, the analog control voltage (VAGC) that signal indicator 701 will notify analog gain control circuit 20 to be produced became big direction adjustment toward gain.
Suppose that digital gain control circuit 30 operates in gain curve Gain3, analog control voltage (VAGC) is through the conversion of four voltage quasi positions (V4 → when V0) being lower than the first predeterminated voltage value V0, the state of the digital signal D that analog-digital converter 31 is exported will be (00000), and digitial controller 33 can directly up switch to Gain2 with present gain curve Gain3 according to digital signal (00000), and a gain ladder 43 is up adjusted in the gain of pre-amplifier 11.
After gain was up switched suddenly, the signal indicator 701 of fundamental frequency chip 700 was controlled voltage (VAGC) with instruction simulation and is moved toward the direction that the gain ladder 43 of offsetting numeral changes.In other words, if Gain3 → Gain2 representative draws high the action of gain, then signal indicator 701 will move toward the direction that reduces gain by instruction simulation control voltage (VAGC), to offset the change in gain amount of gain ladder 43.
After a work period, if the result that the digital signal D of 33 pairs of analog-digital converters of digitial controller, 31 outputs takes a sample still is (00000), the amount of increasing of i.e. expression gain is not enough, and must continue to switch to a gain curve Gain2 → Gain1 of stratum.
When digital signal D is not (00000), for example: on the node 413 and relative digital signal is (11000), or switched to gain curve Gain1, digital gain control circuit 30 just can stop the action that to gain and up switch for pre-amplifier 11.
Because digital gain control circuit of the present invention 30 designs have the function of a sluggishness, therefore at analog control voltage (VAGC) during not greater than the second predeterminated voltage value V4, digital gain control circuit 30 just can not downgrade switching for gain curve.
Therefore, in digital gain control circuit 30, import a lag function, has different gain switching points respectively with making down gain switch and up gain to switch, and must carry out the conversion of four voltage quasi positions to each other, the action that digital control circuit 30 just can gain and switch, to avoid only establishing single gain switching point, analog control voltage (VAGC) drops on this gain switching point just, will therefore cause gain constantly to be switched up and down, and form the concussion of control loop.
And, the digital gain control circuit 30 of present embodiment operates in (between the first predeterminated voltage value V0 and the second predeterminated voltage value V4) in the identical voltage section with each the gain curve Gain1 of stratum～4, therefore, can reduce analog-digital converter 31 comparator 315 quantity is set, to reduce the cost of hardware circuit.
And, when present embodiment wireless receiver 100 switches at digital gain, single order is followed single order switch, little by little to switch to suitable gain curve, so can avoid once just gain being switched to desired gain size, and produce the transient response of a fierceness.
See also Fig. 5 and Fig. 6, be respectively the block schematic diagram of the another embodiment of gain control circuit of wireless receiver of the present invention and the gain curve schematic diagram of digital gain control circuit.As shown in the figure, the structural similarity of the wireless receiver 500 of present embodiment is in the wireless receiver 100 of Fig. 1 embodiment.Difference of them is: the gain curve of the multistage layer that the digital gain control circuit 30 of embodiment is formulated among Fig. 1 will operate in the identical voltage section (as shown in Figure 2), and the gain curve of the multistage layer that present embodiment digital gain control circuit 50 is formulated will operate in respectively in the different voltage sections, as shown in Figure 6.
Present embodiment digital gain control circuit 50 connects simulation gain control circuit 20 and pre-amplifier 11, in order to receive the analog control voltage (VAGC) that analog gain control circuit 20 is produced, and make the gain curve of multistage layer for pre-amplifier 11, for example: Gain1～4, and be set with one first predeterminated voltage value V0 and one second predeterminated voltage value V6.
To include a plurality of voltage sections between the first predeterminated voltage value V0 and the second predeterminated voltage value V6, each gain curve operates in respectively in the different voltage sections, for example: gain curve Gain1 operates in V0～V3, gain curve Gain2 operates in V1～V4, gain curve Gain3 operates in V2～V5, and gain curve Gain4 operates in V3～V6.
When analog control voltage (VAGC) exceeded the pairing voltage section of each gain curve, digital gain control circuit 50 just can carry out the change action between the different gains curve, so adjusted the gain size of this pre-amplifier 11 with digital form.
In addition, the two adjacent operated voltage sections of gain curve will have section partly to overlap each other, for example: the V1 of gain curve Gain1 and Gain2～V3 voltage section.
Moreover each voltage section includes one first critical voltage value and one second critical voltage value respectively, and for example: first critical voltage value in the operated voltage section of gain curve Gain1 is that the V0 and second critical voltage value are V3.
When analog control voltage (VAGC) is higher than pairing second critical voltage value of gain curve, switch to the gain curve of next stratum, and analog control voltage (VAGC) switches to the gain curve of a stratum when being lower than pairing first critical voltage value of gain curve.
See also Fig. 6 and Fig. 7, be respectively the gain curve schematic diagram and the block schematic diagram of digital gain control circuit of the present invention.As shown in the figure, digital gain control circuit 50 includes an analog-digital converter 51 and a digitial controller 53, and wherein analog-digital converter 51 is in order to receive an analog control voltage (VAGC) and a reference voltage Vref and to export a digital signal D.
Analog-digital converter 51 takes out the first predeterminated voltage value V0 and the second predeterminated voltage value V6 in the reference voltage Vref that is received, and between the first predeterminated voltage value V0 and the second predeterminated voltage value V6, be set with a plurality of voltage quasi position V0, V1, V2, V3, V4, V5 and V6 ... Deng, analog control voltage (VAGC) compares with each voltage quasi position respectively, produces a digital signal D with correspondence.Wherein analog-digital converter 51 can be the analog-digital converter (Flash ADC) of a flash type.
See also Fig. 6 and Fig. 8, be respectively the gain curve schematic diagram of digital gain control circuit of the present invention and the circuit connection diagram of analog-digital converter.As shown in the figure, analog-digital converter 51 includes a plurality of first resistors 511, one first voltage buffer 512, one second voltage buffer 514, a plurality of second resistor 513 and a plurality of comparator 515.
Each first resistor 511 is provided with in the mode of series connection, and to form a load voltage V on first resistor 511 of series connection
D, for example be connected with a reference voltage and an earth terminal on first resistor 511 of series connection.First voltage buffer 512 is connected to the first contact X1 on first resistor 511 of series connection, (for example: 0.99V) to receive the first predeterminated voltage value V0 that produced on the first contact X1.514 of second voltage buffers are connected to one second contact X2 on first resistor 511 of series connection, (for example: 1.275V) to receive the second predeterminated voltage value V6 that produced on the second contact X2.
Each second resistor 513 is provided with and is connected between the output of first voltage buffer 512 and second voltage buffer 514 in the mode of series connection, and dividing potential drop produces a plurality of voltage quasi positions, for example: V0～V6.
And each comparator 515 connects corresponding voltage quasi position and analog control voltage (VAGC) respectively, and the voltage quasi position and the analog control voltage (VAGC) of correspondence compared, to export a comparison value respectively, for example: D
6～D
0, wherein with each comparison value D
6～D
0Form digital signal D.
And each gain curve will have a change in gain at the intersegmental slope of operated voltage zone, for example: gain curve Gain1 is in the intersegmental 3db change in gain that has of V0～V3 voltage zone, and the height of the gain between adjacent gain curve has a gain ladder 61/63 with drop, for example: 3db or 5db.
In addition, between the first predeterminated voltage value V0 and the second predeterminated voltage value V6, will be set with a plurality of voltage quasi position V0, V1, V2, V3, V4, V5 and V6 ... Deng, but the also accurate position of switching of representative simulation digital quantizer 51 of this voltage quasi position.
Digital gain control mode of the present invention will have switch mode and a switch mode that up gains that down gains.Switch mode down gains: the gain curve that will switch to next stratum when analog control voltage (VAGC) is higher than the second limit voltage value of the operated voltage section of each gain curve.And the switch mode that up gains: the gain curve that when analog control voltage (VAGC) is lower than the first limit voltage value of the operated voltage section of each gain curve, will switch to a last stratum.
At this, be example with gain curve Gain2, when analog control voltage (VAGC) when being higher than V4, switch to gain curve Gain3, and, will switch to gain curve Gain1 when analog control voltage (VAGC) when being lower than V1.So, the down gain of each gain curve is switched and the switching that up gains has different gain switching points respectively, to form a hesitation between adjacent gain curve.
When the wireless receiver 500 of present embodiment receives a bigger input signal, signal indicator 701 will notify analog control voltage (VAGC) that analog gain control circuit 20 produced toward the direction adjustment that gains and diminish.
If, analog control voltage (VAGC) is through the conversion of three voltage quasi positions (when V0 → V3) is higher than the pairing second limit voltage value V3 of gain curve Gain1, the state of the digital signal D that analog-digital converter 51 is exported will become (1111000), and digitial controller 53 can directly down switch present gain curve according to digital signal (1111000), for example in the present embodiment, digital gain control circuit 50 operates on the gain curve Gain1 at the beginning, and down switch to Gain2 by gain curve Gain1, so that a gain ladder 61 is down adjusted in the gain of pre-amplifier 11.
After gain is down switched suddenly, the signal indicator 701 of fundamental frequency chip 700 is controlled voltage (VAGC) with instruction simulation and is moved toward the direction of offsetting 61 variations of gain ladder, in other words, Gain1 → Gain2 representative reduces the action of gain, then signal indicator 701 will move toward the direction that increases gain by instruction simulation control voltage (VAGC), to offset the change in gain amount of gain ladder 61.
In the next work period, when if analog control voltage (VAGC) still continues to be higher than toward the direction adjustment that diminishes of gain the pairing second limit voltage value V4 of gain curve Gain2, the amount of downgrading of i.e. expression gain is not enough, and the digital signal D (1111100) that digitial controller 53 will be exported according to analog-digital converter 51 continues to switch to next gain curve Gain2 → Gain3 of stratum.
Otherwise, analog control voltage (VAGC) tends towards stability and drops between voltage section V1～V4 of gain curve Gain2, for example: node 611, or switched to the gain curve of last stratum, for example: Gain4, digital gain control circuit 50 will stop the action that to gain down and to switch for pre-amplifier 11.
Because digital gain control circuit 50 designs of the present invention have the function of a sluggishness, therefore at analog control voltage (VAGC) during not less than the pairing first limit voltage value of gain curve at present, digitial controller 53 of the present invention just can not increase switching for gain curve.
Otherwise when input signal changed a less input signal into, the analog control voltage (VAGC) that signal indicator 701 will notify analog gain control circuit 20 to be produced became big direction adjustment toward gain.
Suppose that digital gain control circuit 50 operates in gain curve Gain3, and analog control voltage (VAGC) moves with the direction that increases gain and when being lower than the pairing first limit voltage value V2 of gain curve Gain3, the state of the digital signal D that analog-digital converter 51 is exported will be (1100000), and digitial controller 53 can directly up switch to Gain2 with present gain curve Gain3 according to digital signal (1100000), and a gain ladder 63 is up adjusted in the gain of pre-amplifier 11.
And after gain up switches suddenly, the signal indicator 701 of fundamental frequency chip 700 instruction simulation control voltage (VAGC) at once moves toward the direction that counteracting gain ladder 53 changes, in other words, Gain3 → Gain2 representative draws high the action of gain, then signal indicator 701 will move toward the direction that reduces gain by instruction simulation control voltage (VAGC), to offset the change in gain amount of gain ladder 63.
In the next work period, if analog control voltage (VAGC) still continues to become big direction adjustment and when being lower than the pairing first limit voltage value V1 of gain curve Gain2 toward gain, the amount of increasing of i.e. expression gain is not enough, and the digital signal D (1000000) that digitial controller 53 will be exported according to analog-digital converter 51 continues to switch to next gain curve Gain2 → Gain1 of stratum.
Otherwise, analog control voltage (VAGC) tends towards stability and drops between the intersegmental V1～V4 of voltage zone of gain curve Gain2, for example: node 613, or having switched to the gain curve Gain1 of first stratum, digital gain control circuit 50 will stop action that to proceed to gain and up switch for pre-amplifier 11.
In like manner, because digital gain control circuit 50 designs of the present invention have a lag function, therefore at analog control voltage (VAGC) during not greater than the pairing second limit voltage value of gain curve at present, digitial controller 53 of the present invention just can not downgrade switching for gain curve.
Therefore, in digital gain control circuit 50, import a lag function, to make each gain curve have the gain switching point that different down gains is switched and up gained and switch respectively, and must carry out conversion to each other through three voltage quasi positions, the action that digital control circuit 50 just can gain and switch, to avoid only establishing single gain switching point, analog control voltage (VAGC) drops on this gain switching point just, will therefore cause gain constantly to be switched up and down, and form the concussion of control loop.
Same, the wireless receiver 500 of present embodiment will be selected single order to follow single order and switch when digital gain switches, little by little to switch to suitable gain curve, so avoiding once just gain being switched to desired gain size, and produce the transient response of a fierceness.
Moreover, please consult Fig. 7 once again, present embodiment digital gain control circuit 50 constantly switches back and forth in order to prevent digital gain, and carries out correct change action for gain curve, will have additional stratum's register 55 in circuit 50.
Stratum's register 55 connects digitial controller 53, and include single order layer data 551, these stratum's data 551 are in order to putting down in writing the operated stratum of present gain curve, and stratum's register 55 can be the member that an accumulator, an accumulation subtraction apparatus and/or a buffer are combined into.
Because each gain curve of present embodiment operates in different voltage sections respectively, and has different switching points respectively, if digitial controller 53 do not know the stratum that present gain curve is operated, switching point that may misquotation is switched for gain curve.
With digital signal D (1111000) is example, the switching that gain curve Gain2 need not gain, so, gain curve Gain1 meets the condition (the second critical voltage value V3) that down gain is switched, if the not switching that promptly gains of engagement layer data 551 of digitial controller 53 this moment, the judgement that will make the mistake.
Therefore, setting by stratum's register 55, digitial controller 53 can be learnt the stratum that present gain curve is operated by stratum's data 551 of stratum's register 55, and the action of collocation digital signal D to determine whether to gain and switch, avoid whereby not writing down stratum's data 551, and the gain that leads to errors is switched.
The above, it only is preferred embodiment of the present invention, be not to be used for limiting scope of the invention process, promptly all equalizations of doing according to the described shape of the present patent application claim, structure, feature and spirit change and modify, and all should be included in the claim of the present invention.
Claims (19)
1. the gain control circuit of a wireless receiver is characterized in that, its structure includes:
Casacade multi-amplifier includes at least one pre-amplifier and a plurality of post-amplifier, and these a plurality of post-amplifiers connect this pre-amplifier;
One analog gain control circuit connects this a plurality of post-amplifiers, in order to producing an analog control voltage, and adjusts the gain of these a plurality of post-amplifiers with an analog form according to this analog control voltage; And
One digital gain control circuit, connect this analog gain control circuit and this pre-amplifier, in order to receive this analog control voltage, and make the gain curve of multistage layer for this pre-amplifier, the gain curve of this multistage layer is operating between one first predeterminated voltage value and the one second predeterminated voltage value, when this analog control voltage exceeds voltage section between this first predeterminated voltage value and this second predeterminated voltage value, just can carry out the switching between the different gains curve;
Wherein, this digital gain control circuit includes:
One analog-digital converter, in order to receive this analog control voltage and a reference voltage, and in this reference voltage, take out this first predeterminated voltage value and this second predeterminated voltage value, and between this first predeterminated voltage value and this second predeterminated voltage value, set out a plurality of voltage quasi positions, this analog control voltage compares with each voltage quasi position respectively, produces a digital signal with correspondence; And
One digitial controller connects this analog-digital converter, receiving this digital signal, and carries out the switching of this gain curve according to this digital signal.
2. gain control circuit according to claim 1, it is characterized in that, this analog control voltage switches to next stratum's gain curve when being higher than this second predeterminated voltage value, and this analog control voltage switches to stratum's gain curve when being lower than this first predeterminated voltage value.
3. gain control circuit according to claim 1, it is characterized in that, this digitial controller will be made the gain curve of this multistage layer for this pre-amplifier, and switch to the gain curve of a last stratum or the gain curve of next stratum according to this digital signal with decision.
4. gain control circuit according to claim 1 is characterized in that this digitial controller is taken a sample to this digital signal that this analog-digital converter produced in each work period.
5. gain control circuit according to claim 1 is characterized in that, this analog-digital converter includes:
A plurality of first resistors connect in the mode of connecting, and form a load voltage on first resistor of series connection;
One first voltage buffer connects one first contact of first resistor of this series connection, and produces this first predeterminated voltage value on this first contact;
One second voltage buffer connects one second contact of first resistor of this series connection, and produces this second predeterminated voltage value on this second contact;
A plurality of second resistors are connected the output of this first voltage buffer and this second voltage buffer with series system, and produce a plurality of voltage quasi positions; And
A plurality of comparators connect corresponding voltage quasi position and this analog control voltage respectively, and produce this digital signal by the comparative result of this voltage quasi position and this analog control voltage.
6. gain control circuit according to claim 5 is characterized in that, is connected with a reference voltage and an earth terminal on first resistor of this series connection.
7. gain control circuit according to claim 1 is characterized in that, this analog-digital converter is a flash type analog-digital converter.
8. gain control circuit according to claim 1 is characterized in that, this analog gain control circuit is in order to receiving an index signal, and produces this analog control voltage according to this index signal.
9. gain control circuit according to claim 8 is characterized in that this index signal is produced by a signal indicator, and this signal indicator is incorporated in a fundamental frequency chip, an intermediate-frequency circuit or the zero intermediate frequency circuit.
10. the gain control circuit of a wireless receiver is characterized in that, its primary structure includes:
Casacade multi-amplifier includes at least one pre-amplifier and a plurality of post-amplifier, and these a plurality of post-amplifiers connect this pre-amplifier;
One analog gain control circuit connects this a plurality of post-amplifiers, in order to producing an analog control voltage, and adjusts the gain of these a plurality of post-amplifiers with an analog form according to this analog control voltage; And
One digital gain control circuit, connect this analog gain control circuit and this pre-amplifier, in order to receive this analog control voltage, and make multistage layer gain curve for this pre-amplifier, this multistage layer gain curve all operates between one first predeterminated voltage value and the one second predeterminated voltage value, to include a plurality of voltage sections between this first predeterminated voltage value and this second predeterminated voltage value, each gain curve operates in respectively in the different voltage sections, when this analog control voltage exceeds the pairing voltage section of each gain curve, just carry out the switching of different gains curve, and the two adjacent operated voltage sections of gain curve there is section partly to overlap;
Wherein, this digital gain control circuit includes:
One analog-digital converter, in order to receive this analog control voltage and a reference voltage, and in this reference voltage, take out this first predeterminated voltage value and this second predeterminated voltage value, and between this first predeterminated voltage value and this second predeterminated voltage value, be set with a plurality of voltage quasi positions, this analog control voltage compares with each voltage quasi position respectively, produces a digital signal with correspondence; And
One digitial controller connects this analog-digital converter, receiving this digital signal, and carries out the switching of this gain curve according to this digital signal.
11. gain control circuit according to claim 10 is characterized in that, described each voltage section includes one first critical voltage value and one second critical voltage value respectively.
12. gain control circuit according to claim 11, it is characterized in that, this analog control voltage switches to the gain curve of next stratum when being higher than pairing this second critical voltage value of this gain curve, and this analog control voltage switches to the gain curve of a stratum when being lower than pairing this first critical voltage value of this gain curve.
13. gain control circuit according to claim 10, it is characterized in that, this digitial controller will be made the gain curve of this multistage layer for this pre-amplifier, and switch to the gain curve of a last stratum or the gain curve of next stratum according to this digital signal with decision.
14. gain control circuit according to claim 10 is characterized in that, this digital gain control circuit includes stratum's register, and this stratum's register is in order to write down the operated stratum of present gain curve.
15. gain control circuit according to claim 10 is characterized in that, this analog-digital converter includes:
A plurality of first resistors connect in the mode of connecting, and form a load voltage on first resistor of series connection;
One first voltage buffer connects one first contact of first resistor of this series connection, and produces this first predeterminated voltage value on this first contact;
One second voltage buffer connects one second contact of first resistor of this series connection, and produces this second predeterminated voltage value on this second contact;
A plurality of second resistors are connected the output of this first voltage buffer and this second voltage buffer with series system, and produce a plurality of voltage quasi positions; And
A plurality of comparators connect corresponding voltage quasi position and this analog control voltage respectively, and produce this digital signal by the comparative result of this voltage quasi position and this analog control voltage.
16. gain control circuit according to claim 15 is characterized in that, is connected with a reference voltage and an earth terminal on first resistor of this series connection.
17. gain control circuit according to claim 10 is characterized in that, this analog-digital converter is a flash type analog-digital converter.
18. gain control circuit according to claim 10 is characterized in that, this analog gain control circuit is in order to receiving an index signal, and produces this analog control voltage according to this index signal.
19. gain control circuit according to claim 18 is characterized in that, this index signal is produced by a signal indicator, and this signal indicator is incorporated in a fundamental frequency chip, an intermediate-frequency circuit or the zero intermediate frequency circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101299814A CN101335505B (en) | 2008-07-30 | 2008-07-30 | Gain control circuit of wireless receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101299814A CN101335505B (en) | 2008-07-30 | 2008-07-30 | Gain control circuit of wireless receiver |
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| CN101335505A CN101335505A (en) | 2008-12-31 |
| CN101335505B true CN101335505B (en) | 2010-08-18 |
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| CN101882918B (en) * | 2009-05-07 | 2014-01-08 | 财团法人工业技术研究院 | Automatic gain control method and device |
| CN102638234B (en) * | 2011-11-18 | 2014-12-31 | 珠海派诺科技股份有限公司 | Signal intensity judging method and quick gain switching method |
| CN103384144A (en) * | 2012-05-02 | 2013-11-06 | 中国科学院微电子研究所 | Switching circuit for analog control VGA and digital control VGA |
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Address after: Taiwan, Hsinchu, China Patentee after: Dafa Technology Co.,Ltd. Address before: Taiwan, Hsinchu, China Patentee before: AIROHA TECHNOLOGY CORP. |