CN101334969B - Grid driving circuit and electric power control circuit - Google Patents
Grid driving circuit and electric power control circuit Download PDFInfo
- Publication number
- CN101334969B CN101334969B CN2007101274865A CN200710127486A CN101334969B CN 101334969 B CN101334969 B CN 101334969B CN 2007101274865 A CN2007101274865 A CN 2007101274865A CN 200710127486 A CN200710127486 A CN 200710127486A CN 101334969 B CN101334969 B CN 101334969B
- Authority
- CN
- China
- Prior art keywords
- npn
- gate driver
- couples
- order
- enabling signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a gate driving circuit and a power control circuit. The gate driving circuit comprises a gate driver and the power control circuit. The gate driver is utilized to receive an starting signal and output a plurality of scanning signals in sequence. The power control circuit comprises a delay circuit, a potential converter and a switch element. The delay switch is utilized to receive the starting signal and after putting off the starting signal for a preset time, the delayed starting signal is output. The potential converter is utilized to receive and adjust the voltage level of the delayed starting signal and accordingly output a starting voltage. The switch element delays the first power which is initially provided to the gate driver for the preset time according to the starting voltage and then transmits the first power to the gate driver. The power control circuit provided is easy to integrate with the gate driver into the gate driving circuit or carry out chip-based design with the gate driver.
Description
Technical field
The invention relates to a kind of gate driver circuit, and particularly relevant for a kind of power control circuit that can protect gate driver circuit.
Background technology
As everyone knows, gate driver circuit (Gate driving circuit) is one of critical elements of Thin Film Transistor-LCD (TFT-LCD), and it is in order to be responsible for opening and closing the thin film transistor (TFT) (TFT) of each row pixel in the liquid crystal display panel of thin film transistor.And in order to avoid gate driver circuit moment to be burnt, the power supply that the existing practice can input to part gate driver circuit carry out after certain input timing postpones, to reach the purpose of protection gate driver circuit.
Fig. 1 illustrates the system block diagrams into existing protection gate driver circuit.Please refer to Fig. 1, power supply unit 11 is in order to export the first power vd DG and second source VEEG.Wherein, the first power vd DG is a voltage potential required when the thin film transistor (TFT) conducting of each row pixel in the gate driver circuit 13 control TFT display panels to be provided, second source VEEG then be in order to thin film transistor (TFT) that each row pixel in the gate driver circuit 13 control TFT display panels is provided by the time required voltage potential.Delay circuit 12 is coupled between power supply unit 11 and the gate driver circuit 13, and it is by resistance R
1～R
4, transistor Q
1With Q
2, and capacitor C is formed.This delay circuit 12 mainly is in order to after the first power vd DG is postponed certain input timing, offers gate driver circuit 13 again and uses.
Fig. 2 illustrates and is the received power supply sequential chart of the gate driver circuit 13 of Fig. 1.Please merge with reference to Fig. 1 and Fig. 2, when power supply unit 11 is exported the first power vd DG and second source VEEG simultaneously, delay circuit can directly provide second source VEEG to use (that is second source VEEG does not do delay) to gate driver circuit 13 12 this moments, and this second source VEEG can be via resistance R
1With R
2Dividing potential drop after, so that capacitor C is charged up to transistor Q
1Till the conducting.Then, as transistor Q
1During conducting, it can cause transistor Q
2Also conducting thereupon, the first power vd DG like this just can offer gate driver circuit 13 and use.
So according to as can be known above-mentioned, gate driver circuit 13 received power supply orders will receive second source VEEG earlier, then receive the first power vd DG again, and existing is exactly to adopt delay circuit 12 to avoid time ratio second source VEEG that the first power vd DG is supplied to gate driver circuit 13 early, burnt so can prevent 13 moments of gate driver circuit.
Yet, though the delay first power vd DG that the delay circuit 12 that Fig. 1 disclosed can be successful, to avoid gate driver circuit 13 can not burnt moment, but the extra delay circuit of setting up 12 not only can make cost of manufacture increase, and, just can seriously weaken competitiveness of product if when being integrated in delay circuit 12 in the gate driver circuit 13.
In addition, the research staff of this technical field also develops many delay circuits that are different from above-mentioned delay circuit 12.For instance, in U.S.'s bulletin case number the 6th, 373, the technology of a kind of " Power supply apparatus of an LCD and voltage sequence control method " is proposed in No. 479 patent cases, this patent case is that transistor and resistance are set between gate driver circuit and power supply device, so reaches gate driver circuit 13 and can not burnt moment.The technology of a kind of " Power sequence apparatus for device driving circuit and itsmethod " is proposed in numbers the 7th, 015, No. 904 patent cases of U.S.'s bulletin case in addition.In addition, in the technology of U.S. Patent Application Publication case number No. 20060092883 proposition a kind of " Power sequence apparatus and driving method thereof ".
Yet; the technology contents that is disclosed in these patent cases all is to be devoted to how to protect gate driver circuit; but it can't make that also the circuit volume reaches minimization, and some also need provide extra power supply unit or power supply, so that cost of manufacture can promote more.Moreover the most important is, the above-mentioned technology contents that discloses neither being fit to is integrated into gate driver circuit or carries out the chip design with gate drivers with gate drivers (gate driver).
Summary of the invention
Purpose of the present invention just provides a kind of power control circuit, in order to the protection gate driver circuit, and simultaneously can dwindle the circuit volume, and does not need the power supply unit or the power supply that provide extra.
Another object of the present invention just provides a kind of gate driver circuit, it is by being integrated in the power control circuit of the invention described above and gate drivers in it or carrying out the chip design, so can reach all advantages of the power control circuit of the invention described above.
Based on above-mentioned purpose, the present invention proposes a kind of power control circuit, it is in order to the control gate driver circuit, this gate driver circuit is exported a plurality of sweep signals in regular turn according to the enabling signal that is input to power control circuit, and power control circuit comprises delay circuit, electric potential transducer, and on-off element.Wherein, delay circuit receives enabling signal, and with output delay enabling signal behind one section Preset Time of its delay.Electric potential transducer couples delay circuit, exports trigger voltage in order to the voltage potential of reception and adjustment delay enable signal.The control end of on-off element couples the output terminal of electric potential transducer, the input end of on-off element is in order to receive first power supply, the output terminal of on-off element then is coupled to gate driver circuit, and this on-off element determines that according to trigger voltage its input end and its output terminal are conducting or cut-off state.
From another viewpoint, the present invention proposes a kind of gate driver circuit, comprises gate drivers and power control circuit.Wherein, gate drivers according to be input to-enabling signal of power control circuit exports a plurality of sweep signals in regular turn.Power control circuit comprises delay circuit, electric potential transducer, and on-off element.Delay circuit is in order to receiving enabling signal, and it is postponed output delay enabling signal behind one section Preset Time.Electric potential transducer couples delay circuit, exports trigger voltage in order to the voltage potential of reception and adjustment delay enable signal.The control end of on-off element couples the output terminal of electric potential transducer, the input end of on-off element is in order to receive first power supply, the output terminal of on-off element then is coupled to gate drivers, and this on-off element determines that according to trigger voltage its input end and its output terminal are conducting or cut-off state.
In power control circuit of the present invention, delay circuit can comprise the D flip-flop of phase inverter and negative edge flip-over type.Wherein, phase inverter is in order to anti-phase with the enabling signal that is received and postpone to export enabling signal behind the above-mentioned Preset Time.The data input pin of the D flip-flop of negative edge flip-over type is in order to receiving enabling signal, and its input end of clock couples phase inverter, the D flip-flop of this negative edge flip-over type according to postpone Preset Time later enabling signal and the output delay enabling signal.
In power control circuit of the present invention, delay circuit also can comprise the D flip-flop of positive edge flip-over type, its input end is in order to receive working power, and its input end of clock is in order to receive enabling signal, the D flip-flop of this positive edge flip-over type is according to enabling signal, and postpones output delay enabling signal behind one section Preset Time.
In power control circuit of the present invention, on-off element can comprise P transistor npn npn, N transistor npn npn, and phase inverter.Wherein, the control end of N transistor npn npn and the input end of phase inverter couple a end that the control end of output terminal, the P transistor npn npn of electric potential transducer couples the output terminal of phase inverter, P transistor npn npn and N transistor npn npn in order to receive first power supply, and the other end of P transistor npn npn and N transistor npn npn then is coupled to gate driver circuit.
In power control circuit of the present invention, on-off element also can comprise P transistor npn npn, N transistor npn npn, and phase inverter.Wherein, the control end of N transistor npn npn and the input end of phase inverter couple a end that the control end of output terminal, the P transistor npn npn of electric potential transducer couples the output terminal of phase inverter, P transistor npn npn and N transistor npn npn in order to receive first power supply, and the other end of P transistor npn npn and N transistor npn npn then is coupled to gate drivers.
In power control circuit of the present invention, on-off element also can be P transistor npn npn or N transistor npn npn, and its control end couples the output terminal of electric potential transducer, and the one end is in order to receive first power supply, and its other end then couples gate driver circuit.
Power control circuit provided by the present invention is because utilize delay circuit to receive enabling signal, and utilize electric potential transducer to adjust the voltage potential of the delay enable signal that delay circuit exports, then the trigger voltage that utilizes on-off element to export according to electric potential transducer again determines its conducting state, supplies first power supply so again and uses for gate driver circuit or gate drivers.Therefore; power control circuit provided by the present invention not only can be protected gate driver circuit or gate drivers; and can dwindle the circuit volume simultaneously; and do not need the power supply unit or the power supply that provide extra, so be easy to be integrated into gate driver circuit or carry out the chip design with gate drivers with gate drivers.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 illustrates the system block diagrams into existing protection gate driver circuit.
Fig. 2 illustrates and is the received power supply sequential chart of the gate driver circuit of Fig. 1.
Fig. 3 illustrates the calcspar into the gate driver circuit of one embodiment of the invention.
Fig. 4 illustrates the internal circuit calcspar into the power control circuit of Fig. 3.
Fig. 5 illustrates the circuit diagram into the power control circuit of Fig. 4.
Fig. 6 illustrates the power supply sequential chart into the power control circuit of Fig. 5.
Fig. 7 illustrates the circuit diagram into the power control circuit of another embodiment of the present invention.
Fig. 8 illustrates the power supply signal sequential chart into the power control circuit of Fig. 7.
Embodiment
Fig. 3 illustrates the calcspar into the gate driver circuit of one embodiment of the invention.Please refer to Fig. 3, gate driver circuit 30 comprises power control circuit 301 and gate drivers 302.In the present embodiment, the first power vd DG, second source VEEG, working power VDDD that gate driver circuit 30 is exported in order to reception external power source supply (not illustrating), and enabling signal STV.Wherein, working power VDDD is in order to provide gate driver circuit 30 work required operating voltage, and enabling signal STV is the trigger pip in order to the sweep signal of being exported as article one sweep trace of gate drivers 302, so that gate drivers 302 output scanning signal (scan signal) in regular turn, and power control circuit 301 can be independent of outside the gate driver circuit 30.
In addition, the function of the first power vd DG and second source VEEG has been illustrated in the prior art, and the first power vd DG, second source VEEG, working power VDDD that above-mentioned external power source supply is exported, and enabling signal STV, those skilled in the art should know, so also no longer given unnecessary details at this.
Fig. 4 illustrates the internal circuit calcspar into the power control circuit 301 of Fig. 3.Please merge with reference to Fig. 3 and Fig. 4, power control circuit 301 comprises delay circuit 41, electric potential transducer 42, and on-off element 43.Wherein, delay circuit 41 postpones to export a delay enable signal DS behind one section Preset Time in order to the enabling signal STV that will be received.Electric potential transducer 42 is in order to the voltage potential of the delay enable signal DS that receives and adjust delay circuit 41 and exported, and with its output with as trigger voltage A, wherein the voltage potential of this trigger voltage A can be near the voltage potential of the first power vd DG, and its detailed reason describes in detail after holding again.
On-off element 43 has input end, output terminal and control end, wherein the control end of on-off element 43 couples the output terminal of electric potential transducer 42, the input end of on-off element 43 is in order to receive the first power vd DG that the said external power supply unit is exported, and the output terminal of on-off element 43 then is coupled to gate drivers 302.In the present embodiment, on-off element 43 can be according to trigger voltage A, and determines between its input end and its output terminal to be conducting or to end.Thus, power control circuit 301 can postpone the first power vd DG according to enabling signal STV to be provided to the time of gate drivers 302, to reach the purpose of protection gate driver circuit 30.
And, below will propose a kind of practical circuit diagram that can reach the technology effect of above-mentioned power control circuit 301 further and give technician's reference in field of the present invention, but be not limited thereto in order to set forth spirit of the present invention in further detail.
Fig. 5 illustrates the circuit diagram into the power control circuit 301 of Fig. 4.Please merge with reference to Fig. 4 and Fig. 5, in the present embodiment, delay circuit 41 is formed with the phase inverter 511 and the D flip-flop 512 of negative edge flip-over type, and on-off element 43 then is with N transistor npn npn 531, P transistor npn npn 532, and phase inverter 533 is formed.Wherein, as these interelement relations of coupling illustrate as Fig. 5, so also no longer given unnecessary details at this.
Fig. 6 illustrates the power supply sequential chart into the power control circuit 301 of Fig. 5.Please merge with reference to Fig. 3～Fig. 6, in the present embodiment, when the input end of the data input pin (D) of D flip-flop 512 and phase inverter 511 received enabling signal STV, phase inverter 511 was can be with enabling signal STV anti-phase and postpone to export to the input end of clock (CLK) of D flip-flop 512.In Fig. 6, the received enabling signal STV of the data input pin of D flip-flop 512 is expressed as STV (D), and the received inverted enable signal STV of the input end of clock of D flip-flop 512 is expressed as
(CLK).
As mentioned above, D flip-flop 512 is because adopt the mechanism of negative edge triggering, so work as inverted enable signal
When (CLK) reducing to electronegative potential by noble potential is vertical, the data output end of D flip-flop 512 (Q) will be exported the enabling signal STV (D) of noble potential, also is the delay enable signal DS that delay circuit 41 is exported.Then, electric potential transducer 42 can receive this delay enable signal DS, and its voltage potential is adjusted to voltage potential near the first power vd DG, that is the trigger voltage A that exported of electric potential transducer 42, the input end of on-off element 43 and the voltage difference between output terminal reduced whereby.
For instance, suppose that the first power vd DG is 18V, and the thermal voltage of on-off element 43 is minimum, so trigger voltage A then can be set at 18V, so that trigger voltage A after opening on-off element 43, causes the exportable voltage near 18V of output terminal of on-off element 43.
Afterwards, when the input end of phase inverter 533 receives trigger voltage A, output terminal at phase inverter 533 can obtain an anti-phase trigger voltage B, and if trigger voltage A is when being noble potential, N transistor npn npn can be unlocked for 531 this moments (that is the 531ON that is indicated at the time of Fig. 6 t2).In addition, this moment, anti-phase trigger voltage B must be electronegative potential, so P transistor npn npn 532 also can be unlocked at this moment (that is the 532ON that is indicated at the time of Fig. 6 t2).In addition, when N transistor npn npn 531 and P transistor npn npn 532 were opened simultaneously, on behalf of on-off element 43, it be the state of conducting (that is the 43ON that is indicated) in Fig. 6.
In the present embodiment, the circuit structure of on-off element 43 is a kind of complementary switch, and so the reason of design is for the input end that will reduce on-off element 43 and the voltage difference between output terminal.So after on-off element 43 conductings (that is at the time of Fig. 6 t2), power control circuit 301 just can offer the first power vd DG gate drivers 302 and use, so promptly reach the purpose that the first power vd DG is postponed output, and the time T that is indicated among its time delay such as Fig. 6
d).Whereby, the received power supplys order of gate drivers 302 will receive second source VEEG earlier, then receives the first power vd DG again, so can prevent 30 moments of gate driver circuit to be burnt.
In addition, it will be further appreciated that those skilled in the art should be as can be known, on-off element 43 is also single only to be realized with a P transistor npn npn or a N transistor npn npn.For instance, when if on-off element 43 only selects for use a N transistor npn npn to realize, the user is as long as couple the control end of N transistor npn npn 531 output terminal of electric potential transducer 42, and a termination of utilizing N transistor npn npn 531 receives the first power vd DG, and the other end of N transistor npn npn 531 is coupled to gate drivers 302.Thus, when trigger voltage A was noble potential, N transistor npn npn 531 can be unlocked at this moment, and the first power vd DG is offered gate drivers 302 uses.
In addition, when if on-off element 43 only selects for use a P transistor npn npn to realize, the user is as long as couple the control end of P transistor npn npn 532 output terminal of electric potential transducer 42, and a termination of utilizing P transistor npn npn 532 receives the first power vd DG, and the other end of P transistor npn npn 532 is coupled to gate drivers 302.Thus, when trigger voltage A was electronegative potential, P transistor npn npn 532 can be unlocked at this moment, and the first power vd DG is offered gate drivers 302 uses.
In addition, delay circuit 41 also has the selections in a lot of designs, for example phase inverter 511 can be replaced with delayer, behind the D flip-flop 512 of the positive edge flip-over type of so arranging in pairs or groups again, can realize the effect identical with the delay circuit 41 of the foregoing description.Moreover, also more can utilize counter to come the Preset Time of the control lag first power vd DG.Because each tame manufacturer is all different with the design of on-off element 43 for delay circuit 41, therefore application of the present invention should be not restricted to the possible kenel of this kind.In other words, so long as utilize delay circuit 41 that the enabling signal STV that is received is postponed with behind the output delay enabling signal DS, the conducting of gauge tap element 43 or cut-off state have been to have met spiritual place of the present invention just to supply the operation workflow that the first power vd DG uses for gate drivers 302 again.
Next, below will enumerate another embodiment of the present invention again, so that the technician in field of the present invention can implement the present invention easily.Fig. 7 illustrates the circuit diagram into the power control circuit 701 of another embodiment of the present invention.Please be simultaneously with reference to Fig. 5 and Fig. 7, the power control circuit 301 that power control circuit 701 and Fig. 5 that Fig. 7 disclosed disclosed maximum different be in: power control circuit 701 only uses the D flip-flop 71 of a positive edge flip-over type can realize the effect of the delay circuit 41 of Fig. 5.Wherein, the data input pin of D flip-flop 71 (D) is in order to receiving above-mentioned working power VDDD, that is the VDDD that Fig. 8 indicated (D), and the input end of clock of D flip-flop 71 (CLK end) is in order to receive enabling signal STV.
Fig. 8 illustrates the power supply signal sequential chart into the power control circuit 701 of Fig. 7.Please merge with reference to Fig. 3, Fig. 7 and Fig. 8, at time t1, above-mentioned external power source supply can be exported the first power vd DG, second source VEEG, enabling signal STV simultaneously, and working power VDDD.Wherein, second source VEEG can be directly inputted into gate drivers 302.Then, at time t2, the data input pin of D flip-flop 71 and input end of clock the voltage potential of the working power VDDD that receives respectively and enabling signal STV when being all noble potential, on-off element 73 is meeting its input end of conducting and output terminal, and the first power vd DG is postponed the back use, and this section is the time T of Fig. 8 time delay to offer gate drivers 302
dMoreover all the other operational details of present embodiment are all similar with the described by way of example of Fig. 5, so also no longer given unnecessary details at this.
In sum, power control circuit provided by the present invention is because adopt delay circuit that the enabling signal that is received is postponed with after the output delay enabling signal, the voltage potential that utilizes electric potential transducer to receive again and adjust delay enable signal is with as trigger voltage, and the gauge tap element is conducting or cut-off state according to this, so uses to gate drivers to supply first power supply.Therefore; power control circuit provided by the present invention not only can be protected gate driver circuit; and can dwindle the circuit volume simultaneously; and do not need the power supply unit or the power supply that provide extra, so be easy to be integrated into gate driver circuit or carry out the chip design with gate drivers with gate drivers.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (12)
1. power control circuit, in order to control a gate driver circuit, this gate driver circuit is exported a plurality of sweep signals in regular turn according to an enabling signal that is input to power control circuit, it is characterized in that this power control circuit comprises:
One delay circuit receives this enabling signal, and it is postponed to export a delay enable signal behind the Preset Time;
One electric potential transducer couples this delay circuit, in order to receive and to adjust the voltage potential of this delay enable signal and export a trigger voltage; And
One on-off element, its control end couples the output terminal of this electric potential transducer, and its input end is in order to receive one first power supply, and its output terminal then is coupled to this gate driver circuit, this on-off element is according to this trigger voltage, and determines that its input end and its output terminal are conducting or cut-off state.
2. power control circuit as claimed in claim 1 is characterized in that, this delay circuit comprises:
One phase inverter, in order to receiving this enabling signal, and with its anti-phase with postpone this enabling signal of output behind this Preset Time; And
The D flip-flop of one negative edge flip-over type, its data input pin receives this enabling signal, and its input end of clock couples this phase inverter, and the D flip-flop of this negative edge flip-over type is exported this delay enable signal according to this enabling signal that postpones behind this Preset Time.
3. power control circuit as claimed in claim 1 is characterized in that, this delay circuit comprises:
The D flip-flop of one positive edge flip-over type, its data input pin is in order to receive a working power, its input end of clock is in order to receiving this enabling signal, and the D flip-flop of this positive edge flip-over type is according to this enabling signal, and postpones this delay enable signal of output behind this Preset Time.
4. power control circuit as claimed in claim 1 is characterized in that, this on-off element comprises:
One P transistor npn npn;
One N transistor npn npn; And
One phase inverter,
Wherein, the control end of this N transistor npn npn and the input end of this phase inverter couple the output terminal of this electric potential transducer, the control end of this P transistor npn npn couples the output terminal of this phase inverter, one end of this P transistor npn npn and this N transistor npn npn is in order to receive this first power supply, and the other end of this P transistor npn npn and this N transistor npn npn then couples this gate driver circuit.
5. power control circuit as claimed in claim 1 is characterized in that, this on-off element is a P transistor npn npn, and its control end couples the output terminal of this electric potential transducer, and the one end is in order to receive this first power supply, and its other end then couples this gate driver circuit.
6. power control circuit as claimed in claim 1 is characterized in that, this on-off element is a N transistor npn npn, and its control end couples the output terminal of this electric potential transducer, and the one end is in order to receive this first power supply, and its other end then couples this gate driver circuit.
7. a gate driver circuit is characterized in that, comprising:
One gate drivers, it exports a plurality of sweep signals in regular turn according to an enabling signal that is input to a power control circuit; And
Described power control circuit comprises:
One delay circuit in order to receiving this enabling signal, and postpones output one delay enable signal behind the Preset Time with it;
One electric potential transducer couples this delay circuit, in order to receive and to adjust the voltage potential of this delay enable signal and export a trigger voltage; And
One on-off element, its control end couples the output terminal of this electric potential transducer, and its input end is in order to receive one first power supply, and its output terminal then is coupled to this gate drivers, this on-off element is according to this trigger voltage, and determines that its input end and its output terminal are conducting or cut-off state.
8. gate driver circuit as claimed in claim 7 is characterized in that, this delay circuit comprises:
One phase inverter, in order to receiving this enabling signal, and with its anti-phase with postpone this enabling signal of output behind this Preset Time; And
The D flip-flop of one negative edge flip-over type, its data input pin are in order to receiving this enabling signal, and its input end of clock couples this phase inverter, and the D flip-flop of this negative edge flip-over type is exported this delay enable signal according to this enabling signal that postpones behind this Preset Time.
9. gate driver circuit as claimed in claim 7 is characterized in that, this delay circuit comprises:
The D flip-flop of one positive edge flip-over type, its data input pin is in order to receive a working power, and its input end of clock is in order to receiving this enabling signal, and the D flip-flop of this positive edge flip-over type is according to this enabling signal, and postpones this delay enable signal of output behind this Preset Time.
10. gate driver circuit as claimed in claim 7 is characterized in that, this on-off element comprises:
One P transistor npn npn;
One N transistor npn npn; And
One phase inverter,
Wherein, the control end of this N transistor npn npn and the input end of this phase inverter couple the output terminal of this electric potential transducer, the control end of this P transistor npn npn couples the output terminal of this phase inverter, one end of this P transistor npn npn and this N transistor npn npn is in order to receive this first power supply, and the other end of this P transistor npn npn and this N transistor npn npn then couples this gate drivers.
11. gate driver circuit as claimed in claim 7 is characterized in that, this on-off element is a P transistor npn npn, and its control end couples the output terminal of this electric potential transducer, and the one termination is received this first power supply, and its other end then couples this gate drivers.
12. gate driver circuit as claimed in claim 7 is characterized in that, this on-off element is a N transistor npn npn, and its control end couples the output terminal of this electric potential transducer, and the one termination is received this first power supply, and its other end then couples this gate drivers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101274865A CN101334969B (en) | 2007-06-28 | 2007-06-28 | Grid driving circuit and electric power control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101274865A CN101334969B (en) | 2007-06-28 | 2007-06-28 | Grid driving circuit and electric power control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101334969A CN101334969A (en) | 2008-12-31 |
| CN101334969B true CN101334969B (en) | 2010-06-09 |
Family
ID=40197541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101274865A Expired - Fee Related CN101334969B (en) | 2007-06-28 | 2007-06-28 | Grid driving circuit and electric power control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101334969B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101533598B (en) * | 2009-03-26 | 2011-01-19 | 华映光电股份有限公司 | A source electrode driven integrated circuit framework of display |
| CN102074197B (en) * | 2011-01-21 | 2013-01-09 | 昆山工研院新型平板显示技术中心有限公司 | Driving method for active matrix organic light emitting display |
| TWI525993B (en) * | 2014-05-05 | 2016-03-11 | 瑞鼎科技股份有限公司 | Driving circuit for generating voltage control signals |
| CN107103871B (en) * | 2017-06-30 | 2019-11-22 | 京东方科技集团股份有限公司 | The power supply circuit and method of supplying power to of display device and display screen |
| CN107564449B (en) * | 2017-09-13 | 2020-12-01 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
| KR102431503B1 (en) * | 2017-10-18 | 2022-08-10 | 엘지전자 주식회사 | Image display apparatus |
| US10964282B2 (en) * | 2018-06-12 | 2021-03-30 | Sharp Kabushiki Kaisha | Power supply circuit and display device |
| CN108877719B (en) * | 2018-07-25 | 2021-01-05 | 惠科股份有限公司 | Power supply device and display device |
| CN109410859B (en) * | 2018-11-21 | 2021-04-02 | 惠科股份有限公司 | Display device, driving method and display |
| CN109509454B (en) * | 2018-12-24 | 2021-10-01 | 惠科股份有限公司 | Driving device, circuit driving method and display panel |
| CN109616042B (en) * | 2019-02-14 | 2022-02-11 | 京东方科技集团股份有限公司 | Pixel circuit, driving method thereof and display device |
| CN110176220B (en) * | 2019-06-24 | 2021-09-07 | 上海天马微电子有限公司 | Time sequence control circuit, time sequence control method, display panel and display device |
| CN114189151B (en) * | 2020-09-15 | 2024-02-06 | 圣邦微电子（北京）股份有限公司 | DC-DC boost converter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414670B1 (en) * | 1998-08-24 | 2002-07-02 | Lg Semicon Co., Ltd. | Gate driving circuit in liquid crystal display |
| CN1928975A (en) * | 2005-09-06 | 2007-03-14 | 中华映管股份有限公司 | Driving device |
-
2007
- 2007-06-28 CN CN2007101274865A patent/CN101334969B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414670B1 (en) * | 1998-08-24 | 2002-07-02 | Lg Semicon Co., Ltd. | Gate driving circuit in liquid crystal display |
| CN1928975A (en) * | 2005-09-06 | 2007-03-14 | 中华映管股份有限公司 | Driving device |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2003-215630A 2003.07.30 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101334969A (en) | 2008-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101334969B (en) | Grid driving circuit and electric power control circuit | |
| KR101542506B1 (en) | liquid crystal display | |
| CN101326587B (en) | Shift register circuit and display drive device | |
| KR100788391B1 (en) | Circuit for bi-directional driving liquid crystal display panel | |
| CN102426826B (en) | The control method of display controller, display device, display system and display device | |
| US7532174B2 (en) | Programmable drivers for display devices | |
| EP2498260A1 (en) | Shift register and the scanning signal line driving circuit provided there with, and display device | |
| EP2498245A1 (en) | Liquid crystal display device and driving method therefor | |
| US20130069930A1 (en) | Shift register, scanning signal line drive circuit, and display device | |
| US20150187313A1 (en) | Display device and method of initializing gate shift register of the same | |
| CN106057143A (en) | Shifting register and operation method thereof, grid driving circuit and display device | |
| CN101577104A (en) | Gate driver and associated method for a double gate liquid crystal display | |
| CN101135787A (en) | LCD device capable of sharing electric charge to reduce consumption of energy | |
| KR101205543B1 (en) | Display device and method of driving the same | |
| US20100020053A1 (en) | Display module and driving method thereof | |
| KR101749755B1 (en) | Gate shift register and display device using the same | |
| WO2014048007A1 (en) | Driver circuit, liquid crystal display device, and driving method | |
| CN101339338B (en) | Electric charge sharing mode LCD device, source drive device and electric charge sharing method | |
| US7038643B2 (en) | Bi-directional driving circuit for liquid crystal display device | |
| CN106601207A (en) | Control circuit, source control circuit, driving method, and display device | |
| US20130127797A1 (en) | Gate driving circuit and gate driving method thereof | |
| US11328682B2 (en) | Display device capable of high-speed charging/discharging and switching scanning order of gate bus lines | |
| US7965271B2 (en) | Liquid crystal display driving circuit and method thereof | |
| US20060284663A1 (en) | Timing control circuit and method | |
| CN109389926B (en) | Shift register, grid drive circuit and array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100609 Termination date: 20200628 |