CN101334960A - Display device - Google Patents

Abstract

The invention provides a display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.

Description

Display device

The application is that application number is 200510125921.1, and the applying date is on November 25th, 2005, application artificial " Sanyo Electric Co., Ltd ", and denomination of invention is divided an application for the Chinese patent application of " display device ".

Technical field

The present invention relates to a kind of display device, especially about having the display device of shift cache circuit.

Background technology

In the past, the inverter circuit of ohmic load type was known.This inverter circuit for example be disclosed in the bank open country just firm " basis of semiconductor element ", Japanese Ohm company publishes on April 25th, 1985, pp.184-187.In addition, in the past, also known about the shift cache circuit of the inverter circuit that comprises above-mentioned ohmic load type.Shift cache circuit for example is used to the circuit that gate line and drain line with liquid crystal indicator and organic electroluminescence display device are driven.

Figure 18 is the circuit diagram that shows the shift cache circuit that comprises traditional ohmic load type inverter circuit.With reference to Figure 18, traditional shift cache circuit 1000a is made of the 1st 1001a of circuit part and the 2nd 1002a of circuit part.In addition, the 2nd section shift cache circuit 1000b is made of the 1st 1001b of circuit part and the 2nd 1002b of circuit part.

Constitute the 1st 1001a of circuit part of the 1st section shift cache circuit 1000a, comprise n channel transistor NT 201 and NT 202, capacitor C 201 and resistance R 201.Below, in the explanation of conventional art, n channel transistor NT 201 and NT 202 are hereinafter referred to as transistor NT 201 and NT 202.The source electrode of transistor NT 201 is connected in node ND201, and is transfused to for drain electrode commencing signal ST is arranged.Grid for this transistor NT 201 is supplied with frequency signal CLK1.In addition, the source electrode of transistor NT 202 is connected in minus side current potential VSS, and drain electrode simultaneously is connected in node ND202.In addition, a side's of capacitor C 201 electrode is connected in node ND201, and the opposing party's electrode is connected in minus side current potential VSS.In addition, square end of resistance R 201 is connected in positive side current potential VDD, and the opposing party's terminal is connected in node ND202.In addition, constitute inverter circuit by transistor NT 202 and resistance R 201.

In addition, constitute the 2nd 1002a of circuit part of the 1st section shift cache circuit 1000a, comprise n channel transistor NT 203 and resistance R 202.Below, in the explanation of prior art, n channel transistor NT 203 is called as transistor NT 203.The source electrode of transistor NT 203 is connected in minus side current potential VSS, and drain electrode is connected in node ND203.In addition, square end of resistance R 202 is connected in positive side current potential VDD, and the opposing party's terminal is connected in node ND203.In addition, constitute inverter circuit by transistor NT 203 and resistance R 202.

In addition, the 2nd section later shift cache circuit also possesses the circuit identical with above-mentioned the 1st section shift cache circuit 1000a and constitutes.The 1st circuit part of the shift cache circuit of back segment is constituted as the output node of the shift cache circuit that is connected in leading portion.In addition, the grid for the transistor NT 201 of the 1st circuit part that is configured in the odd number section is supplied with above-mentioned frequency signal CLK1, and the grid for the transistor NT 201 of the 1st circuit part that is configured in the even number section is supplied with frequency signal CLK2.

Figure 19 is the oscillogram that is used for illustrating the action of traditional shift cache circuit shown in Figure 180.Next with reference to Figure 18 and Figure 19, the action of traditional shift cache circuit is described.

At first, commencing signal ST becomes the H current potential.Afterwards, frequency signal CLK1 becomes the H current potential.At this moment, in the 1st section shift cache circuit 1000a, transistor NT 201 becomes conducting state, and the current potential of node ND201 rises to the H current potential, so transistor NT 202 becomes conducting state.Whereby, make transistor NT 203 become off state owing to the current potential of node ND202 drops to the L current potential, therefore, the current potential of node ND203 rises to the H current potential, and the output signal SR1 of H current potential is from the 1st section shift cache circuit 1000a output.Frequency signal CLK1 become the H current potential during, the current potential of H current potential is accumulated in capacitor C 201.

Then, frequency signal CLK1 becomes the L current potential.At this moment, the transistor NT 201 of the 1st section shift cache circuit 1000a becomes off state.Afterwards, commencing signal ST becomes the L current potential.At this, in the 1st section shift cache circuit 1000a, even transistor NT 201 becomes off state, also the current potential that is stored in the H current potential of capacitor C 201 owing to the current potential of node ND201 remains on the H current potential, so transistor NT 202 remains on conducting state.Therefore, because the current potential of node ND202 can not rise to the H current potential, so transistor NT203 remains on off state.Whereby, the output signal SR1 of H current potential is continued output from the 1st section shift cache circuit 1000a.

Then, frequency signal CLK2 becomes the H current potential.Whereby, the output signal SR1 of the H current potential of the 1st section shift cache circuit 1000a is input to the 2nd section shift cache circuit 1000b, therefore carries out and above-mentioned the 1st section identical action of shift cache circuit 1000a.Whereby, the output signal SR2 of H current potential is output from the 2nd section shift cache circuit 1000b.

Afterwards, frequency signal CLK1 becomes the H current potential once again.At this moment, in the 1st section shift cache circuit 1000a, transistor NT 201 becomes conducting state, and the current potential of node ND201 drops to the L current potential.Therefore, transistor NT 202 becomes off state, and the current potential of node ND202 rises to the H current potential, and makes transistor NT 203 become conducting state.Whereby, because the current potential of node ND203 drops to the L current potential from the H current potential, so the output signal SR1 of L current potential is from the 1st section shift cache circuit 1000a output.By above-mentioned action, from the shift cache circuit of each section, in regular turn the output signal of the H current potential of output timing after via displacement (SR1, SR2, SR3 ...).

Yet, in traditional shift cache circuit shown in Figure 180, in the 1st section shift cache circuit 1000a, when exporting the output signal SR1 of H current potential, because transistor NT 202 remains on conducting state, thereby produce the problem that perforation electric current circulates between VDD and VSS via resistance R 201 and transistor NT 202.In addition, when the output signal SR1 of output L current potential,, thereby produce the problem that perforation electric current circulates between VDD and VSS via resistance R 202 and transistor NT 203 because transistor NT 203 remains on conducting state.So, produce perforation electric current and often be the problem that circulates between VDD and the VSS.In addition, because the shift cache circuit after the 2nd section also possesses and above-mentioned the 1st section identical formation of shift cache circuit 1000a, therefore also produce the problem that perforation electric current circulates between VDD and VSS.Therefore, when the circuit that above-mentioned traditional shift cache circuit is used in order to the gate line that drives liquid crystal indicator and organic electroluminescence display device and drain line, will cause the problem points of the power consumption increase of liquid crystal indicator and organic electroluminescence display device.

In addition, in traditional shift cache circuit shown in Figure 180, as shown in figure 19, because during the H current potential of the output signal of the last period of the shift cache circuit 1000a of each section and 1000b output, with overlap during the H current potential of the output signal of next section, therefore, export the gate line of display device in output signal so, and when driving the gate line of each section in regular turn, can cause repeating driving the problem of the gate line of the gate line of the last period and next section.For head it off, also can consider the output signal every one section shift cache circuit that will can not overlap during the H current potential, input to the gate line of each section.Yet, in the case,, must possess the problem that hop count is the shift cache circuit of 2 times of gate line numbers and can produce in order to drive the gate line of each section in regular turn.Thereby the problem points that constitutes of the circuit that causes being difficult to simplify the display device that comprises shift cache circuit.

Summary of the invention

Propose the present invention in order to address the above problem, one of purpose of the present invention is to provide a kind of display device that possesses the shift cache circuit that can suppress the power consumption increase.

Another object of the present invention is to provide a kind of display device that circuit constitutes of simplifying.

In order to reach above-mentioned purpose, the display device of the present invention the 1st aspect possesses shift cache circuit, this shift cache circuit comprises: shift cache circuit portion, possess the 1st circuit part and the 2nd circuit part, the 1st circuit part has the 1st transistor that is connected in the 1st current potential side, and be connected in the frequency signal line and respond the 1st signal and the 2nd transistor of conducting, the 2nd circuit part has the response frequency signal and the 3rd transistor of conducting, be connected in the 4th transistor of above-mentioned the 1st current potential side, be connected in the 5th transistor between the above-mentioned the 3rd transistorized grid and above-mentioned the 1st current potential, and be connected between the above-mentioned the 3rd transistorized grid and the said frequencies signal wire, and respond the 2nd signal and conducting, whereby with the said frequencies signal provision to the 6th transistor of above-mentioned the 3rd transistorized grid, and the 2nd signal can obtain not with input have above-mentioned the 1st signal above-mentioned the 2nd transistorized conducting state during equitant conducting state during; Direction of scanning commutation circuit portion is used for the switched scan direction; And input signal commutation circuit portion, be used for switching above-mentioned the 1st signal and the 2nd signal, the corresponding above-mentioned direction of scanning of the 1st signal and the 2nd signal, and be supplied to the above-mentioned the 2nd transistorized grid and the above-mentioned the 6th transistorized grid separately.

As mentioned above, in this display device aspect the 1st, be provided with response the 1st signal and the 2nd transistor of conducting, and respond the 2nd signal and conducting, whereby frequency signal is supplied to the 6th transistor of the 3rd transistorized grid, the 2nd signal can obtain not with input have the 1st signal the 2nd transistorized conducting state during equitant conducting state during, whereby, for example constitute when response the 1st signal and the 2nd transistor of conducting are conducting state, make the 5th transistor become conducting state, then can not cause the 5th transistor AND gate to respond the 2nd signal and the 6th transistor of conducting is in the situation of conducting state simultaneously, therefore can suppress perforation electric current via the 5th transistor AND gate the 6th transistor, and between the 1st current potential and frequency signal line, circulate.At this moment, if constituting at the 5th transistor makes the 4th transistor become conducting state during for conducting, then can not cause by responding the 2nd signal the 6th transistor of conducting make frequency signal be supplied to grid the 3rd transistor, be in the situation of conducting state simultaneously with the 4th transistor, therefore can suppress perforation electric current and circulate via the 3rd transistor AND gate the 4th transistor.In addition, if constitute when response the 1st signal and the 2nd transistor of conducting become conducting state, make the 1st transistor become off state, then can not cause the 1st transistor AND gate the 2nd transistor to be in the situation of conducting state simultaneously, therefore can suppress perforation electric current and between the 1st current potential and frequency signal line, circulate via the 1st transistor AND gate the 2nd transistor.Therefore so, the generation of the perforation electric current of shift cache circuit portion can be suppressed, the increase of power consumption of the display device of shift cache circuit can be suppressed to comprise.In addition, be provided for switching the input signal commutation circuit portion of the 1st signal and the 2nd signal, and the corresponding direction of scanning of the 1st signal and the 2nd signal, and be provided to the 2nd transistor and the 6th transistor respectively, whereby, even under the situation of switched scan direction, also controlled being made as makes the 2nd transient response the 1st signal and conducting, and makes the 6th transient response the 2nd signal and conducting.Whereby, same as described above, if constitute when the 2nd transistor is conducting state, make the 1st transistor become off state, and when the 2nd transistor is conducting state, make the 4th transistor and the 5th transistor become conducting state, even then under the situation of switched scan direction, also same as described above, can suppress the generation of the perforation electric current of shift cache circuit portion.The result can suppress to have the increase of power consumption of the display device of bilateral scanning function.

The display device of the present invention the 2nd aspect possesses shift cache circuit, and this shift cache circuit comprises: the transistor by the 1st conduction type is constituted, and exports the 1st shift cache circuit portion of the 1st shift signal; Transistor by the 1st conduction type is constituted, and exports the 2nd shift signal, and is configured in the 2nd shift cache circuit portion of next section of above-mentioned the 1st shift cache circuit portion; And it is synthetic that above-mentioned the 1st shift signal and the 2nd shift signal are carried out logic, and the logic synthesis circuit portion of output displacement output signal.

As mentioned above, in this display device aspect the 2nd, to comprise the 1st shift cache circuit portion that exports the 1st shift signal, export the 2nd shift signal and be configured in the 2nd shift cache circuit portion of next section of the 1st shift cache circuit portion, it is synthetic that the 1st shift signal and the 2nd shift signal are carried out logic, and the mode of the logic synthesis circuit portion of output displacement output signal, constitute shift cache circuit, whereby, can adopt the 1st shift signal of the 1st shift cache circuit portion, and the 2nd shift signal of the 2nd shift cache circuit portion of next section, and from the logic synthesis circuit portion of shift cache circuit, export specific displacement output signal, and can adopt the 2nd shift signal of the 2nd shift cache circuit portion, and the shift signal of the shift cache circuit portion of next section of the 2nd shift cache circuit portion, and from the logic synthesis circuit portion of shift cache circuit, the displacement output signal of next section that output timing can be not overlapping with respect to above-mentioned specific displacement output signal.Whereby, in shift cache circuit portion in order to 2 sections parts that specific displacement output signal is exported, and in order to output timing can be not overlapping with respect to specific output signal the shift cache circuit portion of 2 sections parts of displacement output signal of next section in, can share the shift cache circuit portion of 1 section part.Therefore, can reduce the hop count of the shift cache circuit portion that constitutes shift cache circuit, therefore, the circuit that can simplify the display device that comprises shift cache circuit constitutes.In addition, transistor with the 1st conduction type constitutes the 1st shift cache circuit portion and the 2nd shift cache circuit portion, whereby, than the situation that constitutes the 1st shift cache circuit portion and the 2nd shift cache circuit portion with 2 kinds of transistors of the 1st conduction type and the 2nd conduction type, when forming the 1st shift cache circuit portion and the 2nd shift cache circuit portion, can reduce the number of times of ion implantation step and the number of ion implantation mask.Whereby, can suppress the complicated of technology, and suppress the increase of manufacturing cost.

Description of drawings

Fig. 1 is the planimetric map that shows the liquid crystal indicator of the 1st embodiment of the present invention;

Fig. 2 is the circuit diagram of V internal drive of the liquid crystal indicator of the 1st embodiment shown in Figure 1;

Fig. 3 is the voltage oscillogram of action of V driver that is used for illustrating the liquid crystal indicator of the 1st embodiment of the present invention;

Fig. 4 is the planimetric map that shows the liquid crystal indicator of the 2nd embodiment of the present invention;

Fig. 5 is the circuit diagram of V internal drive of the liquid crystal indicator of the 2nd embodiment shown in Figure 4;

Fig. 6 is the voltage oscillogram of action of V driver that is used for illustrating the liquid crystal indicator of the 2nd embodiment of the present invention;

Fig. 7 is the circuit diagram of V internal drive of the liquid crystal indicator of the 3rd embodiment of the present invention;

Fig. 8 is the voltage oscillogram of action of V driver that is used for illustrating the liquid crystal indicator of the 3rd embodiment of the present invention;

Fig. 9 is the circuit diagram of V internal drive of the liquid crystal indicator of the 4th embodiment of the present invention;

Figure 10 is the voltage oscillogram of action of V driver that is used for illustrating the liquid crystal indicator of the 4th embodiment of the present invention;

Figure 11 is the circuit diagram of V internal drive of the liquid crystal indicator of the 5th embodiment of the present invention;

Figure 12 is the voltage oscillogram of action of V driver that is used for illustrating the liquid crystal indicator of the 5th embodiment of the present invention;

Figure 13 is the circuit diagram of V internal drive of the liquid crystal indicator of the 6th embodiment of the present invention;

Figure 14 is the voltage oscillogram of action of V driver that is used for illustrating the liquid crystal indicator of the 6th embodiment of the present invention;

Figure 15 is the circuit diagram of the inside of the transversal switch of liquid crystal indicator of the 7th embodiment of the present invention and H driver;

Figure 16 is the planimetric map that shows the organic electroluminescence display device of the present invention the 8th embodiment;

Figure 17 is the planimetric map that shows the organic electroluminescence display device of the present invention the 9th embodiment;

Figure 18 is the circuit diagram that comprises the shift cache circuit of traditional resistor support type inverter circuit;

Figure 19 is the oscillogram that is used for illustrating the action of traditional shift cache circuit shown in Figure 180.

The main element symbol description

1,1b, 1c substrate 2,6,6a display part

3 transversal switches (HSW), 4 H drivers

5,5a V driver 10 drive IC

11 signal generating circuits, 12 power circuits

20,60, 60a pixel 21,61,62 n channel transistors

22 pixel electrodes, 23 counter electrodes

24 liquid crystal, 25 auxiliary capacitors

51、52、53、54、55、501、502、503、504、505、

511、512、513、514、515、521、522、523、524、

525、531、532、533、534、535、541、542、543、

544,545,1001b, 1002b shift cache circuit portion

51a、52a、53a、54a、55a、501a、502a、503a、504a、

505a、511a、512a、513a、514a、515a、521a、522a、

523a、524a、525a、53?1a、532a、533a、534a、535a、

541a, 542a, 543a, 544a, 545a, 1001a the 1st circuit part

51b、52b、53b、54b、55b、501b、502b、503b、504b、

505b、511b、512b、513b、514b、515b、521b、522b、

523b、524b、525b、531b、532b、533b、534b、535b、

541b, 542b, 543b, 544b, 545b, 1002b the 2nd circuit part

60,600,610,620,630,640 direction of scanning commutation circuit portions

61a, 62a p channel transistor 63,63a auxiliary capacitor

64, 64a anode 65,65a negative electrode

66,66a organic electroluminescent element

70,700,710,720,730,740 input signal commutation circuit portions

81、82、83、801、802、803、811、812、813、821、822、823、831、

832,833,841,842,843 logic synthesis circuit portions

81a、82a、83a、801a、802a、803a、811a、812a、

813a、821a、822a、823a、831a、832a、833a、841a、

842a, 843a current potential permanent circuit portion

910,920,930 circuit parts

C1、C2、C11、C12、C21、C22、C31、C32、C41、C42、C81、C91、

C101, C111 electric capacity

C81, C91, C101 the 1st electric capacity

CKV frequency signal CKV1, CKV2 frequency signal line

CSV direction of scanning switching signal

Dummy, Gate1, Gate2 output signal

ENB, ENB1, ENB2 enable signal

NT1、NT11、NT21、NT31、NT41、PT1、PT11、PT21、PT31、PT41

The 1st transistor

NT2、NT12、NT22、NT32、NT42、PT2、PT12、PT22、PT32、PT42

The 2nd transistor

NT3、NT13、NT23、NT33、NT43、PT3、PT13、PT23、PT33、PT43

The 1st diode

NT4、NT14、NT24、NT34、NT44、PT4、PT14、PT24、PT34、PT44

The 3rd transistor

NT5、NT15、NT25、NT35、NT45、PT5、PT15、PT25、PT35、PT45

The 4th transistor

NT6、NT16、NT26、NT36、NT46、PT6、PT16、PT26、PT36、PT46

The 5th transistor

NT7、NT17、NT27、NT37、NT47、PT7、PT17、PT27、PT37、PT47

The 6th transistor

NT8、NT18、NT28、NT38、NT48、PT8、PT18、PT28、PT38、PT48

The 2nd diode

NT51 to NT60, NT81 to NT86, NT91 to NT96, NT101 to NT106 n

Channel transistor

NT61、NT63、NT65、NT67、NT69、PT61、PT63、PT65、PT67、PT69

The 7th transistor

NT71、NT73、NT75、NT77、NT79、PT71、PT73、PT75、PT77、PT79

The 8th transistor

NT72、NT74、NT76、NT78、NT80、PT72、PT74、PT76、PT78、PT80

The 9th transistor

NT62、NT64、NT66、NT68、NT70、PT62、PT64、PT66、PT68、PT70

The 10th transistor

ND1, ND2, ND3, ND4, ND5, ND6 node

SR1 to SR5 shift signal SR11 to the SR15 output signal that is shifted

STV commencing signal VBB minus side current potential

The positive side current potential of VDD Video vision signal

XCSV inversion scanning direction line switching signal

The XENB enable signal that reverses

Embodiment

Followingly embodiments of the invention are described with reference to accompanying drawing.

(the 1st embodiment)

At first, in this 1st embodiment, display part 2 is set on substrate 1 with reference to Fig. 1.At this display part 2, with the rectangular pixel 20 that disposes.In Fig. 1,, only illustrate 1 pixel 20 in order to simplify accompanying drawing.Each pixel 20 by: n channel transistor 21 (hereinafter referred to as transistor 21), pixel electrode 22, and common counter electrode 23, liquid crystal 24 and the auxiliary capacitor 25 of double team between pixel electrode 22 and counter electrode 23 of each pixel 20 of pixel electrode 22 subtends configuration constitute.The source electrode of transistor 21 is connected in pixel electrode 22 and auxiliary capacitor 25, and drain electrode then is connected in drain line.The grid of this transistor 21 is connected in gate line.

In addition, in mode, the transversal switch (HSW) 3 and the H driver 4 of the drain line that is used for driving (scanning) display part 2 is set on substrate 1 along one side of display part 2.In addition, in mode, the V driver 5 of the gate line that is used for driving (scanning) display part 2 is set on substrate 1 along the another side of display part 2.About the transversal switch 3 of Fig. 1,, in fact dispose the switch of the quantity of respective number of pixels though only show 2 switches.In addition, about H driver 4 and the V driver 5 of Fig. 1,, in fact dispose the shift cache circuit portion of the quantity of respective number of pixels though only shown 2 shift cache circuit portions respectively.

In addition, the outer setting at substrate 1 has drive IC 10.This drive IC 10 possesses signal generating circuit 11 and power circuit 12.Be supplied with from drive IC 10 toward H driver 4: vision signal Video, commencing signal STV, direction of scanning switching signal CSV, frequency signal CKV, enable signal ENB, positive side current potential VDD and minus side current potential VBB.In addition, be supplied with from drive IC 10 toward the V driver: commencing signal STV, direction of scanning switching signal CSV, frequency signal CKV, enable signal ENB, positive side current potential VDD and minus side current potential VBB.

In addition, with reference to Fig. 2, in the 1st embodiment, be provided with: the shift cache circuit portion 51 to 55 of multistage in the inside of V driver 5; Direction of scanning commutation circuit portion 60; Input signal commutation circuit portion 70; And the logic synthesis circuit portion 81 to 83 of multistage.In Fig. 2, in order to simplify drawing, only illustrate the shift cache circuit portion 51 to 55 of 5 sections parts, and the logic synthesis circuit portion 81 to 83 of 3 sections parts, but the shift cache circuit portion and the logic synthesis circuit portion that in fact dispose the quantity of respective number of pixels.

The 1st section shift cache circuit portion 51 is made of the 1st 51a of circuit part and the 2nd 51b of circuit part.The 1st 51a of circuit part comprises: n channel transistor NT 1 and NT 2; Form the n channel transistor NT 3 that diode connects; And capacitor C 1.In addition, the 2nd 51b of circuit part comprises: n channel transistor NT 4, NT 5, NT 6 and NT 7; Form the n channel transistor NT 8 that diode connects; And capacitor C 2.Below respectively n channel transistor NT 1 to NT 8 is called transistor NT 1 to NT 8.

Herein, in the 1st embodiment, be arranged on the TFT (Thin Film Transistor, thin film transistor (TFT)) that the transistor NT 1 to NT 8 of the 1st section shift cache circuit portion 51 formed by n type MOS transistor (imitate transistor npn npn) and constitute.In addition, in the 1st embodiment, transistor NT 1, NT 2, NT 6, NT 7 and NT 8 possess 2 gate electrodes of mutual electric connection.

In addition, in the 1st 51a of circuit part, the source electrode of transistor NT 1 is connected in minus side current potential VBB, and drain electrode simultaneously then is connected in node ND1.In addition, side's electrode of capacitor C 1 is connected in minus side current potential VBB, and the opposing party's electrode then is connected in node ND1 simultaneously.

Herein, in the 1st embodiment, the source electrode of transistor NT 2 is connected in node ND1 via transistor NT 3, and drain electrode is connected in frequency signal line (CKV1).

In addition, in the 2nd 51b of circuit part, the source electrode of transistor NT 4 is connected in node ND3, and drain electrode simultaneously then is connected in positive side current potential VDD.The grid of this transistor NT 4 is connected in node ND2.In addition, the source electrode of transistor NT 5 is connected in minus side current potential VBB, and drain electrode simultaneously then is connected in node ND3.The grid of this transistor NT 5 is connected in the node ND1 of the 1st 51a of circuit part.In addition, the source electrode of transistor NT 6 is connected in minus side current potential VBB, and drain electrode simultaneously then is connected in node ND2.The grid of this transistor NT 6 is connected in the node ND1 of the 1st 51a of circuit part.，

Herein, in the 1st embodiment, transistor NT 6 is set to: when transistor NT 5 is conducting state, make transistor NT 4 become off state.In addition, in the 1st embodiment, the source electrode of transistor NT 7 is connected in node ND2 via transistor NT 8, and drain electrode is connected in frequency signal line (CKV1).In addition, in the 1st embodiment, capacitor C 2 is connected between the grid and source electrode of transistor NT 4.

In addition, the shift cache circuit portion 52 to 55 after the 2nd section possesses the circuit identical with above-mentioned the 1st section shift cache circuit portion 51 and constitutes.Particularly, the shift cache circuit portion 52 to 55 after the 2nd section is constituted by having the 1st 52a to 55a of circuit part that the circuit identical with the 1st 51a of circuit part of the 1st section shift cache circuit portion 51 constitute and having the 2nd 52b to 55b of circuit part that the circuit identical with the 2nd 51b of circuit part constitute respectively.

The 2nd section shift cache circuit portion 52 comprises: corresponding to the n channel transistor NT 11 to NT 18 of the transistor NT 1 to NT 8 of the 1st section shift cache circuit portion 51; And corresponding to capacitor C 11 and the C 12 of capacitor C 1 and C 2.Below respectively n channel transistor NT 11 to NT 18 is called transistor NT 11 to NT 18.

In addition, the 3rd section shift cache circuit portion 53 comprises: corresponding to the n channel transistor NT 21 of the transistor NT 1 to NT 8 of the 1st section shift cache circuit portion 51 to NT28; And corresponding to capacitor C 21 and the C 22 of capacitor C 1 and C2.Below respectively n channel transistor NT 21 to NT 28 is called transistor NT 21 to NT 28.

In addition, the 4th section shift cache circuit portion 54 comprises: corresponding to the n channel transistor NT 31 of the transistor NT 1 to NT 8 of the 1st section shift cache circuit portion 51 to NT38; And corresponding to capacitor C 31 and the C 32 of capacitor C 1 and C 2.Below respectively n channel transistor NT 31 to NT 38 is called transistor NT 31 to NT 38.

In addition, the 5th section shift cache circuit portion 55 comprises: corresponding to the n channel transistor NT 41 of the transistor NT 1 to NT 8 of the 1st section shift cache circuit portion 51 to NT48; And corresponding to capacitor C 41 and the C 42 of capacitor C 1 and C 2.Below respectively n channel transistor NT 41 to NT 48 is called transistor NT 41 to NT 48.

Afterwards, the transistor NT 12 of the 2nd section shift cache circuit portion 52 and NT 17, and the transistor NT 32 of the 4th section shift cache circuit portion 54 and NT 37 are connected in frequency signal line (CKV2).In addition, the transistor NT 22 of the 3rd section shift cache circuit portion 53 and NT 27, and the transistor NT 42 of the 5th section shift cache circuit portion 55 and NT 47 are connected in frequency signal line (CKV1).That is,, be connected with frequency signal line (CKV1) and frequency signal line (CKV2) alternately every one section in shift cache circuit portion 51 to 55.

In addition, direction of scanning commutation circuit portion 60 comprises n channel transistor NT 51 to NT 60.Below respectively n channel transistor NT 51 to NT 60 is called transistor NT 51 to NT 60.

At this, in the 1st embodiment, constitute the transistor NT 51 to NT 60 of direction of scanning commutation circuit portion 60, the TFT that is formed by n type MOS transistor constitutes.

In addition, transistor NT 51 to NT 55 is connected to each other a side of source/drain and the opposing party of source/drain according to this in proper order.In addition,, be connected with direction of scanning line switching signal (CSV), at the grid of transistor NT 52 and NT 54, be connected with inversion scanning direction line switching signal (XCSV) simultaneously at the grid of transistor NT 51, NT 53, NT 55.That is, the grid at transistor NT 51 to NT 55 is connected with direction of scanning line switching signal (CSV) and inversion scanning direction line switching signal (XCSV) alternately every one.

In addition, transistor NT 56 to NT 60 is connected to each other a side of source/drain and the opposing party of source/drain according to this in proper order.At the grid of transistor NT 56, NT 58, NT 60, be connected with inversion scanning direction line switching signal (XCSV), at the grid of transistor NT 57 and NT 59, be connected with direction of scanning line switching signal (CSV) simultaneously.That is, the grid at transistor NT 56 to NT 60 is connected with inversion scanning direction line switching signal (XCSV) and direction of scanning line switching signal (CSV) alternately every one.

For forward the time, control makes direction of scanning line switching signal CSV become H current potential (VDD), and inversion scanning direction line switching signal XCSV becomes L current potential (VBB) in the direction of scanning.Therefore, for forward the time, control makes transistor NT 51, NT 53, NT 55, NT 57, NT 59 become conducting state in the direction of scanning, and transistor NT 52, NT 54, NT 56, NT 58, NT 60 become off state.In addition, when being reverse in the direction of scanning, control makes direction of scanning line switching signal CSV become L current potential (VBB), and inversion scanning direction line switching signal XCSV becomes H current potential (VDD).Therefore, when being reverse in the direction of scanning, control makes transistor NT51, NT 53, NT 55, NT 57, NT 59 become off state, and transistor NT 52, NT 54, NT 56, NT 58, NT 60 become conducting state.

In addition, the grid of the transistor NT 1 of the 1st section shift cache circuit portion 51, be connected in the opposing party (side of the source/drain of transistor NT 52) of source/drain of the transistor NT 51 of direction of scanning commutation circuit portion 60, and the node ND3 of the 1st section shift cache circuit portion 51 is connected in the opposing party (side of the source/drain of transistor NT 57) of source/drain of the transistor NT 56 of direction of scanning commutation circuit portion 60.

In addition, the grid of the transistor NT 11 of the 2nd section shift cache circuit portion 52, be connected in the opposing party (side of the source/drain of transistor NT 58) of source/drain of the transistor NT 57 of direction of scanning commutation circuit portion 60, and the node ND3 of the 2nd section shift cache circuit portion 52 is connected in the opposing party (side of the source/drain of transistor NT 53) of source/drain of the transistor NT 52 of direction of scanning commutation circuit portion 60.

In addition, the grid of the transistor NT 21 of the 3rd section shift cache circuit portion 53, be connected in the opposing party (side of the source/drain of transistor NT 54) of source/drain of the transistor NT 53 of direction of scanning commutation circuit portion 60, and the node ND3 of the 3rd section shift cache circuit portion 53 is connected in the opposing party (side of the source/drain of transistor NT 59) of source/drain of the transistor NT 58 of direction of scanning commutation circuit portion 60.

In addition, the grid of the transistor NT 31 of the 4th section shift cache circuit portion 54, be connected in the opposing party (side of the source/drain of transistor NT 60) of source/drain of the transistor NT 59 of direction of scanning commutation circuit portion 60, and the node ND3 of the 4th section shift cache circuit portion 54 is connected in the opposing party (side of the source/drain of transistor NT 55) of source/drain of the transistor NT 54 of direction of scanning commutation circuit portion 60.

In addition, the grid of the transistor NT 41 of the 5th section shift cache circuit portion 55, be connected in the opposing party of source/drain of the transistor NT 55 of direction of scanning commutation circuit portion 60, and the node ND3 of the 5th section shift cache circuit portion 55 is connected in the opposing party of source/drain of the transistor NT 60 of direction of scanning commutation circuit portion 60.

By in the above described manner the shift cache circuit portion 51 to 55 of each section being connected with direction of scanning commutation circuit portion 60, and controlled being made as, corresponding direction of scanning will be the displacement output signal (SR11 to SR15) of the last period to the direction of scanning, input to the 1st circuit part of the shift cache circuit portion of predetermined section.Yet at the 1st 51a of circuit part of first section shift cache circuit portion 51, input has commencing signal STV.

In addition, input signal commutation circuit portion 70 comprises n channel transistor NT 61 to NT 80.Below respectively n channel transistor NT 61 to NT 80 is called transistor NT 61 to NT 80.

At this, in the 1st embodiment, constitute the transistor NT 61 to NT 80 of input signal commutation circuit portion 70, the TFT that is formed by n type MOS transistor constitutes.

In addition, in the 1st embodiment, grid is connected in the n channel transistor of direction of scanning line switching signal (CSV), is connected in the n channel transistor of inversion scanning direction line switching signal (XCSV) with grid, respectively is provided with 2 in each section.Particularly, be provided with at the 1st section: grid is connected in the transistor NT 61 and the NT 62 of direction of scanning line switching signal (CSV); And grid is connected in the transistor NT 71 and the NT 72 of inversion scanning direction line switching signal (XCSV).One side of the source/drain of transistor NT 61 and NT 71 is connected in the grid of transistor NT 2 of the 1st section shift cache circuit portion 51.The opposing party of the source/drain of transistor NT 61 is connected in the node ND2 of the 2nd section shift cache circuit portion 52, and the opposing party of the source/drain of transistor NT 71, is connected in positive side current potential VDD.In addition, a side of the source/drain of transistor NT 62 and NT 72 is connected in the grid of transistor NT 7 of the 1st section shift cache circuit portion 51.The opposing party of the source/drain of transistor NT 62, be connected in the opposing party (side of the source/drain of transistor NT 52) of source/drain of transistor NT 51 of the direction of scanning commutation circuit portion 60 that is supplied with commencing signal (STV) and the grid of transistor NT 1, the opposing party of the source/drain of transistor NT 72 is connected in the node ND2 of the 2nd section shift cache circuit portion 52.

In addition, the 2nd section is provided with: grid is connected in the transistor NT 63 and the NT 64 of direction of scanning line switching signal (CSV), and grid is connected in the transistor NT 73 and the NT 74 of inversion scanning direction line switching signal (XCSV).One side of the source/drain of transistor NT 63 and NT 73 is connected in the grid of transistor NT 12 of the 2nd section shift cache circuit portion 52.The opposing party of the source/drain of transistor NT 63 is connected in the node ND2 of the 3rd section shift cache circuit portion 53, and the opposing party of the source/drain of transistor NT 73, is connected in the node ND2 of the 1st section shift cache circuit portion 51.In addition, a side of the source/drain of transistor NT 64 and NT 74 is connected in the grid of transistor NT 17 of the 2nd section shift cache circuit portion 52.The opposing party of the source/drain of transistor NT 64 is connected in the node ND2 of the 1st section shift cache circuit portion 51, and the opposing party of the source/drain of transistor NT 74 is connected in the node ND2 of the 3rd section shift cache circuit portion 53.

In addition, be provided with at the 3rd section: grid is connected in the transistor NT 65 and the NT 66 of direction of scanning line switching signal (CSV), and grid is connected in the transistor NT 75 and the NT 76 of inversion scanning direction line switching signal (XCSV).One side of the source/drain of transistor NT 65 and NT 75 is connected in the grid of transistor NT 22 of the 3rd section shift cache circuit portion 53.The opposing party of the source/drain of transistor NT 65 is connected in the node ND2 of the 4th section shift cache circuit portion 54, and the opposing party of the source/drain of transistor NT 75, is connected in the node ND2 of the 2nd section shift cache circuit portion 52.In addition, a side of the source/drain of transistor NT 66 and NT 76 is connected in the grid of transistor NT 27 of the 3rd section shift cache circuit portion 53.The opposing party of the source/drain of transistor NT 66 is connected in the node ND2 of the 2nd section shift cache circuit portion 52, and the opposing party of the source/drain of transistor NT 76 is connected in the node ND2 of the 4th section shift cache circuit portion 54.

In addition, be provided with at the 4th section: grid is connected in the transistor NT 67 and the NT 68 of direction of scanning line switching signal (CSV), and grid is connected in the transistor NT 77 and the NT 78 of inversion scanning direction line switching signal (XCSV).One side of the source/drain of transistor NT 67 and NT 77 is connected in the grid of transistor NT 32 of the 4th section shift cache circuit portion 54.The opposing party of the source/drain of transistor NT 67 is connected in the node ND2 of the 5th section shift cache circuit portion 55, and the opposing party of the source/drain of transistor NT 77, is connected in the node ND2 of the 3rd section shift cache circuit portion 53.In addition, a side of the source/drain of transistor NT 68 and NT 78 is connected in the grid of transistor NT 37 of the 4th section shift cache circuit portion 54.The opposing party of the source/drain of transistor NT 68 is connected in the node ND2 of the 3rd section shift cache circuit portion 53, and the opposing party of the source/drain of transistor NT 78 is connected in the node ND2 of the 5th section shift cache circuit portion 55.

In addition, be provided with at the 5th section: grid is connected in the transistor NT 69 and the NT 70 of direction of scanning line switching signal (CSV), and grid is connected in the transistor NT 79 and the NT 80 of inversion scanning direction line switching signal (XCSV).One side of the source/drain of transistor NT 69 and NT 79 is connected in the grid of transistor NT 42 of the 5th section shift cache circuit portion 55.The opposing party of the source/drain of transistor NT 69 is connected in the node ND2 of the 6th section the shift cache circuit portion that does not show among the figure, and the opposing party of the source/drain of transistor NT 79 is connected in the node ND2 of the 4th section shift cache circuit portion 54.In addition, a side of the source/drain of transistor NT 70 and NT 80 is connected in the grid of transistor NT 47 of the 5th section shift cache circuit portion 55.The opposing party of the source/drain of transistor NT 70 is connected in the node ND2 of the 4th section shift cache circuit portion 54, and the opposing party of the source/drain of transistor NT 80 is connected in the node ND2 of the 6th section the shift cache circuit portion that does not show among the figure.

The transistor NT 61 to NT 80 that will constitute input signal commutation circuit portion 70 is by the way constituted, may command makes, for forward the time, make transistor NT 61 to NT 70 become conducting state, and transistor NT 71 to NT 80 become off state in the direction of scanning.In addition, by the shift cache circuit portion 51 to 55 and input signal commutation circuit portion 70 that connects each section in the above described manner, may command makes, corresponding direction of scanning will be the displacement output signal (SR1 to SR5) of next section with respect to the direction of scanning, input to the 1st circuit part of the shift cache circuit portion of predetermined section, and will be the displacement output signal (SR1 to SR5) of the last period with respect to the direction of scanning, input to the 2nd circuit part of the shift cache circuit portion of predetermined section.Yet at the 1st 51a of circuit part of first section shift cache circuit portion 51, input has commencing signal STV.

In addition, logic synthesis circuit portion 81 to 83 is connected to dummy gate electrode line (Dummy), and the gate line (Gate2) of the 1st section gate line (Gate1) and the 2nd section.This logic synthesis circuit portion 81 to 83 is constituted as, the shift signal that the shift cache circuit portion of pairing predetermined section is exported respectively, and the shift signal exported of the shift cache circuit portion of next section of this predetermined section to give logic synthetic, and shift signal is exported to the gate line of each section.

The logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy) comprises n channel transistor NT 81 to NT 84, forms n channel transistor NT 85 and NT 86 and capacitor C 81 that diode connects.Below respectively n channel transistor NT 81 to NT 86 is called transistor NT 81 to NT 86.In addition, by transistor NT 83 to NT 86 and capacitor C 81, constitute the current potential permanent circuit 81a of portion.The current potential permanent circuit 81a of portion is used in the displacement output signal of L current potential when logic synthesis circuit portion 81 exports dummy gate electrode line (Dummy) to, fix this displacement output signal the L current potential current potential and be provided with.

At this, in the 1st embodiment, constitute the transistor NT 81 to NT 86 of logic synthesis circuit portion 81, the TFT that is formed by n type MOS transistor constitutes.

In addition, the drain electrode of transistor NT 81 is connected in enable signal (ENB), and source electrode is connected in the drain electrode of transistor NT 82.The source electrode of transistor NT 82 is connected in node ND4 (dummy gate electrode line).The grid of transistor NT 81 is connected in, and output has the node ND2 of shift signal SR2 of the 2nd section shift cache circuit portion 52, and the grid of transistor NT 82 is connected in, and output has the node ND2 of shift signal SR3 of the 3rd section shift cache circuit portion 53.

In addition, the source electrode of transistor NT 83 is connected in minus side current potential VBB, and drain electrode is connected in node ND4 (dummy gate electrode line).The grid of this transistor NT 83 is connected in node ND5.In addition, the source electrode of transistor NT 84 is connected in minus side current potential VBB, and drain electrode is connected in node ND5.The grid of this transistor NT 84 is connected in node ND4 (dummy gate electrode line).In addition, side's electrode of capacitor C 81 is connected in minus side current potential VBB, and the opposing party's electrode then is connected in node ND5.In addition, node ND5 is via transistor NT 85, and be connected in the node ND3 that exports the shift signal SR11 that the 1st section shift cache circuit portion 51 is arranged, and via transistor NT86, and be connected in the node ND3 that exports the shift signal SR14 that the 4th section shift cache circuit portion 54 is arranged.

In addition, be connected in the logic synthesis circuit portion 82 of the 1st section gate line (Gate1), have the circuit identical and constitute with the logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy).Particularly, the logic synthesis circuit portion 82 that is connected in the 1st section gate line (Gate1) possesses: corresponding to the n channel transistor NT 91 to NT 96 of the transistor NT81 to NT 86 of the logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy), and corresponding to the capacitor C 91 of capacitor C 81.Below respectively n channel transistor NT 91 to NT 96 is called transistor NT 91 to NT 96.In addition, the current potential permanent circuit 82a of portion corresponding to the current potential permanent circuit 81a of portion of the logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy) is made of transistor NT 93 to NT 96 and capacitor C 91.

In being connected in the 1st section the logic synthesis circuit portion 82 of gate line (Gate1), the grid of transistor NT 91 is connected in the node ND2 that exports the shift signal SR3 that the 3rd section shift cache circuit portion 53 is arranged, and the grid of transistor NT 92 is connected in the node ND2 that exports the shift signal SR4 that the 4th section shift cache circuit portion 54 is arranged.In addition, node ND5 is via transistor NT 95, and be connected in the node ND3 that exports the shift signal SR12 that the 2nd section shift cache circuit portion 52 is arranged, and via transistor NT 96, and be connected in the node ND3 that exports the shift signal SR15 that the 5th section shift cache circuit portion 55 is arranged.

In addition, be connected in the logic synthesis circuit portion 83 of the 2nd section gate line (Gate2), have the circuit identical and constitute with the logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy).Particularly, the logic synthesis circuit portion 83 that is connected in the 2nd section gate line (Gate2) possesses: corresponding to the n channel transistor NT 101 to NT 106 of the transistor NT81 to NT 86 of the logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy), and corresponding to the capacitor C 101 of capacitor C 81.Below respectively n channel transistor NT 101 to NT 106 is called transistor NT 101 to NT 106.In addition, the current potential permanent circuit 83a of portion corresponding to the current potential permanent circuit 81a of portion of the logic synthesis circuit portion 81 that is connected in dummy gate electrode line (Dummy) is made of transistor NT 103 to NT 106 and capacitor C 101.

In being connected in the 2nd section the logic synthesis circuit portion 83 of gate line (Gate2), the grid of transistor NT 101 is connected in the node ND2 that exports the shift signal SR4 that the 4th section shift cache circuit portion 54 is arranged, and the grid of transistor NT 102 is connected in the node ND2 that exports the shift signal SR5 that the 5th section shift cache circuit portion 55 is arranged.In addition, node ND5 is via transistor NT 105, and be connected in the node ND3 that exports the shift signal SR13 that the 3rd section shift cache circuit portion 53 is arranged, and via transistor NT 106, and be connected in the node ND3 that output has the displacement output signal of the shift cache circuit portion that does not show among the figure.

Next with reference to Fig. 2 and Fig. 3, the action of V driver of the liquid crystal indicator of the 1st embodiment is described.

At first explanation along the forward direction of Fig. 2, exports the output signal of this sequential after displacement to the situation (forward Sao Miao situation) of the gate line of each section in regular turn.Under this situation that forward scans, direction of scanning line switching signal CSV remains on the H current potential, and inversion scanning direction line switching signal XCSV remains on the L current potential.Whereby, in the middle of direction of scanning commutation circuit portion 60, direction of scanning line switching signal CSV is input into transistor NT 51, NT 53, NT55, NT 57, the NT 59 of grid, remain on conducting state, inversion scanning direction line switching signal XCSV is input into transistor NT 52, NT 54, NT 56, NT 58, the NT 60 of grid, remains on off state.In addition, in input signal commutation circuit portion 70, direction of scanning line switching signal CSV is input into the transistor NT 61 to NT 70 of grid, remains on conducting state, inversion scanning direction line switching signal XCSV is input into the transistor NT 71 to NT 80 of grid, remains on off state.In addition, in the early stage under the state, the shift signal of being exported from the node ND2 of the shift cache circuit portion 51 to 55 of each section (SR1 to SR5), and, become the L current potential from the displacement output signal (SR11 to SR15) that node ND3 is exported.In addition, export the output signal Dummy of gate line of dummy gate electrode line and each section and Gate1 and Gate2 to from the node ND4 of logic synthesis circuit portion 81 to 83 and all become the L current potential.Under this state, as shown in Figure 3, make commencing signal STV rise to the H current potential.Whereby, because the commencing signal STV of H current potential is via the transistor NT 51 of the conducting state of direction of scanning commutation circuit portion 60, and input to the grid of transistor NT 1 of the 1st section shift cache circuit portion 51, so transistor NT 1 becomes conducting state.Afterwards, be input into the frequency signal CKV1 of the drain electrode of the 1st section the transistor NT 2 of shift cache circuit portion 51 and NT 7, rise to H current potential (VDD).

At this moment, in the 1st embodiment, the shift signal SR2 of the L current potential of being exported from the 2nd section shift cache circuit portion 52 via the transistor NT 61 of the conducting state of input signal commutation circuit portion 70, and inputs to the grid of transistor NT 2 of the 1st section shift cache circuit portion 51.Whereby, this transistor NT 2 becomes off state.Therefore, even transistor NT 1 is a conducting state, but perforation electric current can not circulate between frequency signal line (CKV1) and minus side current potential VBB via transistor NT 1 and NT 2.

In addition, because being conducting state and transistor NT 2, the transistor NT 1 of the 1st section shift cache circuit portion 51 is off state, therefore can be via transistor NT 1, the current potential from minus side current potential VBB supplies the L current potential makes the potential drop of node ND1 be low to moderate the L current potential whereby.Whereby, grid transistor NT 5 and the NT 6 of node ND1 that be connected in the 1st section shift cache circuit portion 51 promptly becomes off state.

In addition, the commencing signal STV of H current potential is also via the transistor NT 51 of the conducting state of direction of scanning commutation circuit portion 60, and the transistor NT 62 of the conducting state of input signal commutation circuit portion 70, and input to the grid of transistor NT 7 of the 1st section shift cache circuit portion 51.Whereby, make transistor NT 7 become conducting state.

At this moment, in the 1st embodiment, even transistor NT 7 is a conducting state, but because transistor NT 6 be an off state, so perforation electric current can not circulate between frequency signal line (CKV1) and minus side current potential VBB via transistor NT 6 and NT 7.

In addition, the frequency signal CKV1 that can make the H current potential is via transistor NT 7 and NT 8 and import, and whereby, the current potential of the node ND2 of the 1st section shift cache circuit portion 51 rises to the H current potential.Whereby, make transistor NT 4 become conducting state, and the current potential of H current potential (VDD) is provided to node ND3 via transistor NT 4 from positive side current potential VDD.

At this moment, in the 1st embodiment, even transistor NT 4 is a conducting state, but because transistor NT 5 be an off state, thus perforation electric current can be via transistor NT 4 and NT 5 circulation just between side current potential VDD and the minus side current potential VBB.

In addition, the current potential that makes H current potential (VDD) is supplied to node ND3 via transistor NT 4 from positive side current potential VDD, whereby, makes the current potential of node ND3 rise to the VDD side.At this moment, the current potential of the node ND2 of the 1st section shift cache circuit portion 51 is a mode of keeping voltage between the gate-to-source of node ND4 with capacitor C 2, is accompanied by the rising of current potential of node ND3 and boot (boot) rises whereby.Therefore, the current potential of node ND2 rises to than VDD also till the current potential of the amount of the above predetermined voltage (V α) of high threshold voltage (Vt).Therefore, from the node ND2 of the 1st section shift cache circuit portion 51, output has the shift signal SR1 of the H current potential of the above current potential (VDD+V α) of VDD+Vt.In addition, meanwhile, from the node ND3 of the 1st section shift cache circuit portion 51, the displacement output signal SR11 of output H current potential (VDD).

Afterwards, the displacement output signal SR11 of the H current potential (VDD) of the 1st section shift cache circuit portion 51 via the transistor NT85 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line, and inputs to the grid of transistor NT 83.Whereby, make transistor NT 83 become conducting state.At this moment, grid at the transistor NT 81 of logic synthesis circuit portion 81, from the shift signal SR2 of the input L of the 2nd section shift cache circuit portion 52 current potentials, and at the grid of transistor NT82, from the shift signal SR3 of the 3rd section shift cache circuit portion 53 input L current potentials.Whereby, the transistor NT 81 of logic synthesis circuit portion 81 and transistor NT 82 all become off state.Therefore, supply the current potential of L current potential (VBB) via transistor NT 83, can make the output signal Dummy of L current potential (VBB) whereby,, continue to export to the dummy gate electrode line from the node ND4 of logic synthesis circuit portion 81 from minus side current potential VBB.

In addition, the displacement output signal SR11 of the H current potential (VDD) of the 1st section shift cache circuit portion 51, via the transistor NT 57 of the conducting state of direction of scanning commutation circuit portion 60, and input to the grid of transistor NT 11 of the 2nd section shift cache circuit portion 52.Whereby, transistor NT 11 becomes conducting state.In addition, the shift signal SR1 of the current potential of the H current potential of the 1st section shift cache circuit portion 51 (VDD+V α), via the transistor NT 64 of the conducting state of input signal commutation circuit portion 70, and input to the grid of transistor NT 17 of the 2nd section shift cache circuit portion 52.Whereby, this transistor NT 17 becomes conducting state.In addition, at the grid of the transistor NT 12 of the 2nd section shift cache circuit portion 52, input has the shift signal SR3 of the L current potential of being exported from the node ND2 of the 3rd section shift cache circuit portion 53.Whereby, make transistor NT 12 become off state.Afterwards, input to the current potential of frequency signal CKV2 of the drain electrode of the 2nd section the transistor NT 12 of shift cache circuit portion 52 and transistor NT 17, rise to H current potential (VDD).

At this moment, shift signal SR1 rises to the current potential (VDD+V α) of the amount of the above predetermined voltage (V α) of high threshold voltage (Vt) also than VDD.When the grid of transistor NT 17 of shift cache circuit portion 52 that this shift signal SR1 is inputed to the 2nd section, the grid potential of transistor NT 64 equals the current potential (VDD) of direction of scanning line switching signal CSV, therefore, the grid voltage of transistor NT 17 is charged to VDD-Vt.In addition, because frequency signal CKV2 rises to H current potential (VDD), therefore the grid voltage at transistor NT 17 is keeping under the state of voltage between gate-to-source the difference of the current potential of rise again VDD and VBB.Therefore, the current potential of the node ND2 of the 2nd section shift cache circuit portion 52 can't reduce the amount of the threshold voltage (Vt) of transistor NT 17, and rises to the current potential of H current potential (VDD).

Afterwards, in the 2nd section shift cache circuit portion 52, the action of also carrying out with above-mentioned the 1st section shift cache circuit portion 51 is identical action.That is, from the node ND2 of the 2nd section shift cache circuit portion 52, output has the shift signal SR2 of the H current potential of the above current potential (VDD+V α) of VDD+Vt.In addition, meanwhile, from the node ND3 of the 2nd section shift cache circuit portion 52, the displacement output signal SR12 of output H current potential (VDD).

In addition, (the shift signal SR2 of VDD+V α＞VDD+Vt) is imported into the grid of the transistor NT 81 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line to the H current potential of the 2nd section shift cache circuit portion 52.In addition, (the direction of scanning switching signal CSV that the shift signal SR2 of VDD+V α＞VDD+Vt) is input into VDD inputs to grid and the transistor NT 61 of conducting and the drain electrode of NT 66 to the H current potential.Whereby, because the source potential of transistor NT 61 and NT 66 becomes (VDD-Vt), therefore, current potential (VDD-Vt) is input into the grid of transistor NT 2 of the 1st section shift cache circuit portion 51, and the transistor NT 27 of the 3rd section shift cache circuit portion 53.In addition, the displacement output signal SR12 of the H current potential (VDD) of the 2nd section shift cache circuit portion 52, transistor NT 53 via the conducting state of direction of scanning commutation circuit portion 60, and be input to the grid of transistor NT 21 of the 3rd section shift cache circuit portion 53, and via the transistor NT 95 of the logic synthesis circuit portion 82 that is connected with the 1st section gate line, and be input to the grid of transistor NT 93.

In addition, the transistor NT 81 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line because the shift signal SR2 of H current potential (VDD+V α) is input into grid, and becomes conducting state.At this moment, the transistor NT 82 of logic synthesis circuit portion 81 remains on off state, and transistor NT 83 remains on conducting state.Therefore, because the current potential of the L current potential of being supplied from minus side current potential VBB via transistor NT 83 (VBB) makes the current potential of the node ND4 of logic synthesis circuit portion 81 remain in L current potential (VBB).Therefore, the output signal Dummy of L current potential (VBB) continues the node ND4 from logic synthesis circuit portion 81, exports the dummy gate electrode line to.

In addition, the transistor NT 2 of the 1st section shift cache circuit portion 51 because current potential (VDD-Vt) is input to grid from transistor NT 61, and becomes conducting state.In addition, when shift signal SR2 rose to H current potential (VDD+V α), the frequency signal CKV1 system that inputs to the drain electrode of transistor NT 2 and NT 7 was reduced to the L current potential.At this moment, the current potential of the node ND1 of the 1st section shift cache circuit portion 51 remains in the L current potential.Whereby, make the transistor NT 5 and the NT 6 of the 1st section shift cache circuit portion 51 become off state.

In addition, because frequency signal CKV1 is reduced to the L current potential, make the grid voltage of transistor NT 7 become the L current potential, so transistor NT 7 become off state.Whereby, because the current potential of the node ND2 of the 1st section shift cache circuit portion 51 remains on H current potential (VDD+V α), therefore, the shift signal SR1 of H current potential (VDD+V α) continues to export from node ND2.In addition, because the current potential of the node ND2 of the 1st section shift cache circuit portion 51 remains on H current potential (VDD+V α), and make transistor NT 4 remain on conducting state, therefore, the displacement output signal SR11 of H current potential (VDD) continues the node ND3 output from the 1st section shift cache circuit portion 51.

In addition, the transistor NT 27 of the 3rd section shift cache circuit portion because current potential (VDD-Vt) is input to grid, and becomes conducting state, and transistor NT 21 is because the displacement output signal SR12 of H current potential (VDD) is input to grid, and becomes conducting state.At this moment, at the grid of the transistor NT 22 of the 3rd section shift cache circuit portion, input has the shift signal SR4 of L current potential of the 4th section shift cache circuit portion 54.Therefore, transistor NT22 becomes off state.

Afterwards,, make the transistor NT 1 and the NT 7 of the 1st section shift cache circuit portion 51 become off state, and transistor NT 5 and NT 6 also remain on off state because the current potential of commencing signal STV drops to the L current potential.Whereby, make the current potential of node ND2 of the 1st section shift cache circuit portion 51 remain on H current potential (VDD+V α), and the current potential of node ND3 remain on H current potential (VDD).Therefore, in the 1st section shift cache circuit portion 51, the shift signal SR1 of H current potential (VDD+V α) continues the output from node ND2, and the displacement output signal SR11 of H current potential (VDD) continues to export from node ND3.

Afterwards, input to the current potential of frequency signal CKV1 of the drain electrode of the 3rd section the transistor NT 22 of shift cache circuit portion 53 and transistor NT 27, rise to the H current potential.Whereby, in the 3rd section shift cache circuit portion 53, also carry out the identical action of action with above-mentioned the 1st section shift cache circuit portion 51.Promptly, from the node ND2 of the 3rd section shift cache circuit portion 53, output has the shift signal SR3 of the H current potential of the above current potential (VDD+V α) of VDD+Vt, and from the node ND3 of the 3rd section shift cache circuit portion 53, the displacement output signal SR13 of output H current potential (VDD).

In addition, (the shift signal SR3 of VDD+V α＞VDD+Vt) is input to the transistor NT 82 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line and the grid of the transistor NT 91 of the logic synthesis circuit portion 82 that is connected with the 1st section gate line to the H current potential of the 3rd section shift cache circuit portion 53.In addition, the shift signal SR3 of H current potential is input into the drain electrode of transistor NT 63 of the conducting state of input signal commutation circuit portion 70, and is input into the drain electrode of transistor NT 68 of the conducting state of input signal commutation circuit portion 70.In addition, the displacement output signal SR13 of the H current potential (VDD) of the 3rd section shift cache circuit portion 53, transistor NT 59 via the conducting state of direction of scanning commutation circuit portion 60, and be input to the grid of transistor NT 31 of the 4th section shift cache circuit portion 54, and via the transistor NT 105 of the logic synthesis circuit portion 83 that is connected with the 2nd section gate line, and be input to the grid of transistor NT 103.

In addition, in the 1st embodiment, with logic synthesis circuit portion 81 that the dummy gate electrode line is connected in, be input into respectively the shift signal SR2 of grid of transistor NT 81 and NT 82 and SR3 both, all become H current potential (VDD+V α), and transistor NT 81 and NT 82 all become conducting state.Whereby, from enable signal line (ENB) via transistor NT 81 and NT 82 supply enable signal ENB.This enable signal ENB is that both all become under the time point of H current potential at shift signal SR1 and SR2, becomes the L current potential, after a little during after, current potential can switch to the H current potential from the L current potential.Whereby, because the current potential of the node ND4 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line rises to the H current potential, therefore, the output signal Dummy of H current potential exports the dummy gate electrode line to from logic synthesis circuit portion 81.That is, enable signal ENB is during the L current potential, and the current potential of output signal Dummy is forced to remain on the L current potential, and the current potential that is accompanied by enable signal ENB rises to the H current potential from the L current potential, and the current potential of output signal Dummy also rises to the H current potential.

At this moment, the current potential (current potential of output signal Dummy) that is accompanied by the node ND4 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line rises to the H current potential, and the transistor NT 84 that grid is connected in node ND4 becomes conducting state.Whereby, because the current potential of L current potential is supplied to the grid of transistor NT 83 via transistor NT 84 from minus side current potential VBB, so transistor NT83 becomes off state.Therefore, even all become under the situation of conducting state at transistor NT 81 and NT 82, because transistor NT 83 is an off state, therefore the equipotential layer of the node ND4 of the logic synthesis circuit portion 81 that is connected with the dummy gate electrode line as mentioned above rises.In addition, also can suppress perforation electric current via transistor NT 81, NT 82 and NT 83, and between enable signal line (ENB) and minus side current potential VBB, circulate.

In addition, in the 1st embodiment, with logic synthesis circuit portion 81 that the dummy gate electrode line is connected in, it is grid at transistor NT 81 and NT 82, input has also the shift signal SR2 and the SR3 of the H current potential of the current potential (VDD+V α) of the amount of the above predetermined voltage (V α) of high threshold voltage (Vt) than VDD respectively, and therefore the current potential that can suppress to be occurred among the node ND4 of logic synthesis circuit portion 81 becomes the current potential that reduces the threshold voltage (Vt) of transistor NT 81 and NT 82 from VDD.Therefore can suppress to export to the decline of current potential of output signal Dummy of the H current potential of dummy gate electrode line from logic synthesis circuit portion 81.

In addition, with logic synthesis circuit portion 82 that the 1st section gate line is connected in, the shift signal SR3 of the H current potential of the 3rd section shift cache circuit portion 53 (VDD+V α), be input to the grid of transistor NT 91, and the shift signal SR4 of the L current potential of the 4th section shift cache circuit portion 54 is input to the grid of transistor NT 92.In addition, the displacement output signal SR12 of the H current potential (VDD) of the 2nd section shift cache circuit portion 52 is input to the grid of transistor NT 93.Whereby, with logic synthesis circuit portion 82 that the 1st section gate line is connected in, transistor NT 91 and NT 93 all become conducting state, and transistor NT 92 becomes off state.Therefore, with logic synthesis circuit portion 82 that the 1st section gate line is connected in, the current potential by the L current potential (VBB) supplied from minus side current potential VBB via transistor NT 93 makes the current potential of node ND4 remain on L current potential (VBB).Whereby, the output signal Gate1 of L current potential (VBB) continues the node ND4 from logic synthesis circuit portion 82, exports the 1st section gate line to.

In addition, (the shift signal SR3 of VDD+V α＞VDD+Vt) is input into that direction of scanning switching signal CSV with VDD inputs to grid to the H current potential and the drain electrode of the transistor NT 63 of conducting whereby, becomes the source potential of transistor NT63 (VDD-Vt).Therefore, current potential (VDD-Vt) is input into the grid of transistor NT 12 of the 2nd section shift cache circuit portion 52.Therefore transistor NT 12 becomes conducting state.At this moment, the current potential of frequency signal CKV1 is the H current potential, and the current potential of frequency signal CKV2 is the L current potential.At this moment, because the current potential of the node ND1 of the 2nd section shift cache circuit portion 52 remains on the L current potential, so transistor NT 15 and NT 16 all remain on off state.In addition, the grid voltage of transistor NT 18 becomes the L current potential because of frequency signal CKV2, so transistor NT 18 remains on off state.Therefore, the current potential of the node ND2 of the 2nd section shift cache circuit portion 52 remains on H current potential (VDD+V α).Whereby, the shift signal SR2 of H current potential (VDD+V α) continues shift cache circuit portion 52 outputs from the 2nd section.In addition, in the 2nd section shift cache circuit portion 52, transistor NT 16 remains on off state, and whereby, the current potential of node ND2 remains on H current potential (VDD).Whereby, the displacement output signal SR12 of H current potential (VDD) continues shift cache circuit portion 52 outputs from the 2nd section.

In addition, in the 1st section shift cache circuit portion 51, current potential (VDD-Vt) continues to make transistor NT 2 remain on conducting state whereby from having the transistor NT 61 of the shift signal SR2 of H current potential (VDD+V α) to input to grid in the drain electrode input.Under this state, frequency signal CKV1 rises to H current potential (VDD) from L current potential (VBB), therefore in transistor NT 2, the mos capacitance by transistor NT 2 keeps voltage between gate-to-source, and grid potential is from the current potential difference of (VDD-Vt) rising VDD and VBB.Whereby, the current potential of the node ND1 of the 1st section shift cache circuit portion 51 can't reduce the amount of the threshold voltage (Vt) of transistor NT 2, and rises to the current potential of H current potential (VDD).

Afterwards, because the current potential of the node ND1 of the 1st section shift cache circuit portion 51 rises to the H current potential, thereby make transistor NT 5 and NT 6 become conducting state.At this moment, because transistor NT 7 is an off state, therefore via the current potential of transistor NT 6 from minus side current potential VBB supply L current potential (VBB), and the current potential of the node ND2 of the 1st section shift cache circuit portion 51 drops to the L current potential.Whereby, the current potential of the shift signal SR1 that is exported from the 1st section shift cache circuit portion 51 drops to the L current potential.In addition, because the current potential of the node ND2 of the 1st section shift cache circuit portion 51 drops to the L current potential, so transistor NT 4 is an off state.Whereby, in the 1st section shift cache circuit portion 51, via the current potential of transistor NT 5 from minus side current potential VBB supply L current potential, so the current potential of node ND3 drops to the L current potential.Therefore, the current potential of the displacement output signal SR11 that is exported from the 1st section shift cache circuit portion 51 drops to the L current potential.In addition, when the current potential of the node ND1 of the 1st section shift cache circuit portion 51 rises to the H current potential, because the charging of capacitor C 1, make the current potential of node ND1, till transistor NT 1 becomes conducting state, all remain on the H current potential.Whereby, till transistor NT 1 became conducting state next time, transistor NT 5 and NT 6 all remained on conducting state.

Before the current potential of above-mentioned shift signal SR1 dropped to the L current potential, the current potential of enable signal ENB dropped to the L current potential from the H current potential.Whereby, with logic synthesis circuit portion 81 that the dummy gate electrode line is connected in, owing to the current potential of L current potential is supplied via transistor NT 81 and NT 82, so the current potential of node ND4 can drop to the L current potential.Therefore, the current potential from logic synthesis circuit portion 81 exports the output signal Dummy of dummy gate electrode line to is reduced to the L current potential.

In the 4th section shift cache circuit portion 54, current potential (VDD-Vt) is from having the transistor NT 68 of the shift signal SR3 of H current potential (VDD+V α) to input to the grid of transistor NT 37 in the drain electrode input.In addition, the displacement output signal SR13 of H current potential (VDD) inputs to the grid of transistor NT 31.In addition, the shift signal SR5 of L current potential inputs to the grid of transistor NT 32 from the 5th section shift cache circuit portion 55.Under this state, be input into the current potential of frequency signal CKV2 of the drain electrode of transistor NT 32 and NT 37, rise to the H current potential.Whereby, in the 4th section shift cache circuit portion 54, also carry out the identical action of action with above-mentioned the 1st section shift cache circuit portion 51.Promptly, node ND2 from the 4th section shift cache circuit portion 54, output has the shift signal SR4 of the H current potential of the above current potential (VDD+V α) of VDD+Vt, and from the node ND3 of the 4th section shift cache circuit portion 54, the displacement output signal SR14 of output H current potential (VDD).

In addition, in the 1st embodiment, with logic synthesis circuit portion 81 that the dummy gate electrode line is connected in, the displacement output signal SR14 of H current potential (VDD) exports the grid of transistor NT 83 to via transistor NT 86.Whereby, make transistor NT 83 become conducting state.Because via the current potential of transistor NT 83 from minus side current potential VBB supply L current potential, therefore, the current potential of node ND4 is fixed on the L current potential.Therefore the current potential that exports the output signal Dummy of dummy gate electrode line to from logic synthesis circuit portion 81 is fixed on the L current potential.When the displacement output signal SR14 of H current potential (VDD) is input into the grid of transistor NT 83, make capacitor C 81 chargings.Whereby, next time via the transistor NT 84 of conducting state till the current potential of minus side current potential VBB supply L current potential, the current potential of node ND5 (grid potential of transistor NT 83) remains on the H current potential.Therefore, till transistor NT 84 became conducting state next time, transistor NT83 remained on conducting state, therefore exported the current potential of the output signal Dummy of dummy gate electrode line to from logic synthesis circuit portion 81, remained on the state that is fixed in the L current potential.

In addition, with logic synthesis circuit portion 82 that the 1st section gate line is connected in, the shift signal SR3 of H current potential (VDD+V α) is input into the grid of transistor NT 91, and the shift signal SR4 of H current potential (VDD+V α) is input into the grid of transistor NT 92.Whereby, because transistor NT 91 and NT 92 all become conducting state, therefore, supply enable signal ENB from enable signal line (ENB) via transistor NT 91 and NT 92.Both all become the time point of H current potential to this enable signal ENB at shift signal SR1 and SR2, become the L current potential, after a little during after, current potential switches to the H current potential from the L current potential.Whereby, because the current potential of the node ND4 of the logic synthesis circuit portion 82 that is connected with the 1st section gate line rises to the H current potential, therefore, the output signal Gate1 of H current potential exports the 1st section gate line to from logic synthesis circuit portion 81.That is, enable signal ENB is during the L current potential, and the current potential of output signal Gate1 is mandatory to remain on the L current potential, and is accompanied by enable signal ENB and rises to the H current potential from the L current potential, and the current potential of output signal Gate1 also rises to the H current potential.Therefore, when enable signal ENB is the L current potential, export the output signal Dummy of dummy gate electrode line to from logic synthesis circuit portion 81, therefore the also mandatory L current potential that remains on can suppress output signal Dummy drops to the L current potential from the H current potential sequential, overlapping from the timing sequence generating that the L current potential rises to the H current potential with output signal Gate1.Thereby can suppress because output signal Dummy drops to the sequential of L current potential and output signal Gate1 rises to the H current potential from the L current potential the overlapping noise that causes of timing sequence generating from the H current potential.

Afterwards, in the 5th section shift cache circuit portion 55, also carry out same action with above-mentioned the 1st section to the 4th section shift cache circuit portion 51 to 54.In addition, with logic synthesis circuit portion 83 that the 2nd section gate line is connected in, also carry out with respectively with above-mentioned dummy gate electrode line and the 1st section logic synthesis circuit portion 81 and the 82 identical actions that gate line is connected.Promptly, from the 55 output shift signal SR5 of the 5th section shift cache circuit portion, and shift signal SR3 and SR4 are input to the logic synthesis circuit portion 83 that is connected with the 2nd section gate line, and because enable signal ENB becomes the H current potential, therefore, the output signal Gate2 of H current potential exports the 2nd section gate line to from logic synthesis circuit portion 83.

As mentioned above, in the 1st embodiment, the shift signal SR1 to SR5 of H current potential can produce displacement from shift cache circuit portion 51 to 55 sequential of being exported of each section.Whereby, be the shift signal (the 1st signal) of next section of predetermined section with respect to the direction of scanning, and be the shift signal (the 2nd signal) of the last period of predetermined section, can't become the H current potential simultaneously with respect to the direction of scanning.

So, each section gate line of the liquid crystal indicator of the 1st embodiment is driven (scanning) in regular turn.In addition, above-mentioned action is repeated to the end of scan of last gate line.Afterwards, since the 1st section shift cache circuit portion 51, repeat above-mentioned action once more.

Then, along the reverse direction of Fig. 2, with the output signal of sequential after displacement, export under the situation (situation of reverse scanning) of the gate line of each section in regular turn, direction of scanning line switching signal CSV remains on the L current potential, and inversion scanning direction line switching signal XCSV remains on the H current potential.Whereby, in direction of scanning commutation circuit portion 60, direction of scanning line switching signal CSV is input into transistor NT 51, NT 53, NT 55, NT 57, the NT 59 of its grid, remain on off state, inversion scanning direction line switching signal XCSV is input into transistor NT 52, NT 54, NT 56, NT 58, the NT 60 of its grid, remains on conducting state.In addition, in input signal commutation circuit portion 70, direction of scanning line switching signal CSV is input into the transistor NT 61 to NT 70 of its grid, remains on off state, inversion scanning direction line switching signal XCSV is input into the transistor NT 71 to NT 80 of its grid, remains on conducting state.In addition, when reverse scanning, along the reverse direction of Fig. 2 shift cache circuit portion at each section, and with logic synthesis circuit portion that the gate line of each section is connected in, carry out and above-mentioned action identical when forward scanning.At this moment, from being the shift cache circuit portion of next section of predetermined section with respect to the direction of scanning, input shift signal (the 1st signal) is to the situation of the shift cache circuit portion of predetermined section, and from being the shift cache circuit portion of the last period of predetermined section with respect to the direction of scanning, input shift signal (the 2nd signal) and displacement output signal to the situation of the shift cache circuit portion of predetermined section, be transistor NT 52 via the conducting state of above-mentioned direction of scanning commutation circuit portion 60, NT 54, NT 56, NT 58, NT 60, and the transistor NT 71 to NT 80 of the conducting state of input signal commutation circuit portion 70 carries out.

In the 1st embodiment, as mentioned above, it is the shift signal (the 1st signal) of next section of predetermined section and transistor (the transistor NT 2 of conducting with respect to the direction of scanning that response is set, NT 12, NT 22, NT 32 and NT 42), and response is the shift signal (the 2nd signal) of the last period of predetermined section and transistor (the transistor NT 7 of conducting with respect to the direction of scanning, NT 17, NT 27, NT 37 and NT 47), whereby, make shift signal (the 1st signal) and shift signal (the 2nd signal) the H current potential during can not overlap, therefore, transistor (the transistor NT 2 of conducting in response to shift signal (the 1st signal), NT 12, NT 22, NT 32 and NT 42), and in response to shift signal (the 2nd signal) transistor (the transistor NT 7 of conducting, NT 17, NT 27, NT 37 and NT 47), can't become conducting state simultaneously.In the case, if the direction of scanning is the words of forward direction, for example in the shift cache circuit portion 52 of the 2nd section (predetermined section), the transistor NT 12 of conducting becomes conducting state because in response to the shift signal SR3 (the 2nd signal) of the 3rd section (next section), and make transistor NT 16 become conducting state, and therefore, transistor NT 16, with the transistor NT 17 of conducting can't become conducting state simultaneously in response to the shift signal SR1 (the 1st signal) of the 1st section (the last period).Whereby, can suppress perforation electric current circulation between minus side current potential VBB and frequency signal line (CKV2) via transistor NT 16 and NT 17.

In addition, because the transistor NT 17 of conducting becomes conducting state in response to the shift signal SR1 (the 1st signal) of the 1st section (the last period), therefore, transistor NT 14 becomes conducting state, and the transistor NT 12 of conducting becomes conducting state because in response to the shift signal SR3 (the 2nd signal) of the 3rd section (next section), and make transistor NT 15 become conducting state, therefore, transistor NT 14 and NT 15 can't become conducting state simultaneously.Whereby, can suppress perforation electric current via transistor NT 14 and NT 15 and between minus side current potential VBB and positive lateral electrode VDD, circulate.In addition, because transistor NT 11 conducting in response to the shift signal SR11 of the 1st section (the last period), therefore, transistor NT 11 is with the transistor NT 12 of conducting can't become conducting state simultaneously in response to the shift signal SR3 of the 3rd section (next section).Whereby, can suppress perforation electric current via transistor NT 11 and NT 12, and circulation between minus side current potential VBB and frequency signal line (CKV2).In addition, in the 1st section shift cache circuit portion 51, and in the shift cache circuit portion 53 to 55 after the 3rd section, also identical with the 2nd section shift cache circuit portion 52, can suppress the circulation of perforation electric current.

In addition, in the 1st embodiment, setting is used for corresponding direction of scanning is supplied to transistor NT 2 respectively, NT 12, NT 22, NT 32 and NT 42, and transistor NT 7, NT17, NT 27, the input signal commutation circuit portion 70 that the shift signal of NT 37 and NT 47 (be the shift signal (the 1st signal) of next section of predetermined section and be the shift signal (the 2nd signal) of the last period of predetermined section with respect to the direction of scanning with respect to the direction of scanning) is switched, whereby, even under the situation of switched scan direction, also can suppress the generation of the perforation electric current of shift cache circuit portion 51 to 55.Whereby, in the 1st embodiment, can suppress to have the increase of current sinking of the display device of bilateral scanning function.

In addition, in the 1st embodiment, be to be the shift signal (the 1st signal) of next section of predetermined section and the mode of conducting is come transistor formed NT 2 with respect to the direction of scanning with response, NT 12, NT 22, NT 32 and NT 42, and be the shift signal (the 2nd signal) of the last period of predetermined section and the mode of conducting is come transistor formed NT 7 with respect to the direction of scanning with response, NT 17, NT27, NT 37 and NT 47, whereby, make with respect to the direction of scanning is the shift signal (the 1st signal) of next section of predetermined section, and the response with respect to the direction of scanning be the last period of predetermined section shift signal (the 2nd signal) the H current potential during can not overlap, therefore, at transistor (the transistor NT 2 of conducting in response to shift signal (the 1st signal), NT 12, NT 22, NT 32 and NT 42) when becoming conducting state, can be easily with transistor (the transistor NT 7 of conducting in response to shift signal (the 2nd signal), NT 17, NT 27, NT 37 and NT 47) be controlled to be off state.In addition, at the transistor (transistor NT7, NT 17, NT 27, NT 37 and NT 47) of conducting when becoming conducting state in response to shift signal (the 2nd signal), can be easily with the transistor (transistor NT 2, NT 12, NT 22, NT 32 and NT 42) of conducting is controlled to be off state in response to shift signal (the 1st signal).

In addition, in the 1st embodiment, between the gate-to-source of transistor NT 4, NT 14, NT 24, NT 34 and NT 44, connect capacitor C 2, C 12, C 22, C 32 and C 42 respectively, whereby, for example in the 2nd section shift cache circuit portion 52, in the mode of voltage between the gate-to-source of keeping the transistor NT 14 that is connected with capacitor C 12, be accompanied by the rising or the decline of the source potential of transistor NT 14, make the rising or the decline of the grid potential of transistor NT 14.Whereby, can positively transistor NT 14 be remained on conducting state.

In addition, in the 1st embodiment, to be included in the transistor NT 51 of institute's conducting under the scan condition forward, NT 53, NT 55, NT 57 and NT 59, and the transistor NT 52 of institute's conducting under the situation of reverse scanning, NT 54, NT 56, the mode of NT 58 and NT 60 constitutes input signal commutation circuit portion 70, and via the transistor (NT 51 to 60) that constitutes input signal commutation circuit portion 70, shift signal (SR1 to SR5) is inputed to shift cache circuit portion (51 to 55), whereby, can easily be controlled to be, make with respect to the direction of scanning and be input into the 1st circuit part (51a to 55a), and to make with respect to the direction of scanning be that the shift signal (the 2nd signal) of the last period is input into the 2nd circuit part (51b to 55b) for the shift signal (the 1st signal) of next section.

In addition, in the 1st embodiment, the transistor that constitutes V driver 5 is made to become the transistor of identical conduction type (n type), whereby, when forming the transistor of V driver 5, can prevent that the number of times of ion implantation step and the number of ion implantation mask from increasing.Whereby, can prevent the complicated of technology, and suppress the increase of manufacturing cost.

In addition, in the 1st embodiment, in the 1st section shift cache circuit portion 51, transistor formed NT 1, NT 2, NT 6, NT 7 and NT 8 are for possessing 2 grids of mutual electric connection, whereby, can pass through 2 grids, will be applied to the voltage of transistor NT 1, NT 2, NT 6, NT 7 and NT 8, be dispensed between the source electrode-drain electrode corresponding to each grid.In the case, the voltage that is applied between can the source electrode-drain electrode corresponding to each grid with transistor NT 1, NT 2, NT 6, NT 7 and NT 8 reduces, and therefore can suppress to result from the deterioration of the characteristic that big voltage that transistor NT 1, NT 2, NT 6, NT 7 and NT 8 applied caused.In addition, in the shift cache circuit portion 52 to 55 after the 2nd section, also can obtain same effect.Whereby, can suppress to comprise the reduction of scan characteristic of the display device of shift cache circuit portion 51 to 55.

In addition, in the 1st embodiment, in the 1st section shift cache circuit portion 51, between the grid and transistor NT 2 of transistor NT 6, be provided with and form the transistor NT 3 that diode connects, and between the grid and transistor NT 7 of transistor NT 4, be provided with and form the transistor NT 8 that diode connects, whereby, can pass through transistor NT 3, interdict the noise that when transistor NT 6 is conducting or shutoff, is produced and be conveyed to transistor NT 2, and can pass through transistor NT 8, interdict the noise that when transistor NT 4 is conducting or shutoff, is produced and be conveyed to transistor NT 7.In addition, in the shift cache circuit portion 52 to 55 after the 2nd section, also can obtain same effect.

In addition, in the 1st embodiment, to comprise the shift cache circuit portion 52 to 55 of the last period of exporting shift signal SR2 to SR5, and the shift cache circuit portion 53 to 55 of next section of output shift signal SR3 to SR5, and it is synthetic that the shift signal of the shift signal of the last period and next section is carried out logic, and with output signal Dummy, Gate1, the mode of the logic synthesis circuit portion 81 to 83 that Gate2 is exported, constitute the shift cache circuit of V driver 5, whereby, for example can be to the shift signal SR2 of the 2nd section shift cache circuit portion 52, and the shift signal SR3 of the 3rd section shift cache circuit portion 53 to carry out logic synthetic, and from the 81 output displacement output signal Dummy of logic synthesis circuit portion, and shift signal SR3 to the 3rd section shift cache circuit portion 53, and the shift signal SR4 of the 4th section shift cache circuit portion 54 to carry out logic synthetic, and can be to next overlapping section displacement output signal Gate1 of timing sequence generating of the H current potential of above-mentioned displacement output signal Dummy from 82 outputs of logic synthesis circuit portion.Whereby, be used to export 2 sections the shift cache circuit portion that displacement output signal Dummy is adopted, and the shift cache circuit portion that is used for exporting 2 sections parts that next section displacement output signal Gate1 adopted, can share the shift cache circuit portion 53 of 1 section part.Therefore, can reduce the hop count of the shift cache circuit portion of the shift cache circuit that constitutes V driver 5, therefore, the circuit that can simplify the liquid crystal indicator that comprises shift cache circuit constitutes.

In addition, in the 1st embodiment, in logic synthesis circuit portion, in transistor NT 81 (NT91, NT 101) the shift signal SR2 (SR3 that imports of grid, SR4), and at transistor NT 82 (NT 92, NT 102) the shift signal SR3 (SR4 that imports of grid, when SR5) becoming the H current potential, (NT 93 with transistor NT 83, NT 103) become off state and constitute, whereby, (NT 91 at transistor NT 81, NT 101) and transistor NT 82 (NT 92, NT 102) when becoming conducting, (NT 93 can to make transistor NT 83, NT 103) become off state.Whereby, can suppress perforation electric current via transistor NT 81 (NT 91, NT 101), transistor NT 82 (NT 92, NT 102) and transistor NT 83 (NT 93, NT 103) and between enable signal line (ENB) and minus side current potential VBB, circulate.Whereby, can suppress to comprise the increase of current sinking of the liquid crystal indicator of V driver.

(the 2nd embodiment)

The 2nd embodiment possesses the formation much at one with the 1st embodiment.With reference to Fig. 5, be with the 1st embodiment difference: in the inside of V driver 5a, with constituting the transistor of logic synthesis circuit portion 801 to 803 of shift cache circuit portion 501 to 505, direction of scanning commutation circuit portion 600, input signal commutation circuit portion 700 and the multistage of multistage, change to the p channel transistor.In Fig. 5, in order to simplify accompanying drawing, only shown the shift cache circuit portion 501 to 505 of 5 sections parts, and the logic synthesis circuit portion 801 to 803 of 3 sections parts, but in fact dispose respective number of pixels purpose shift cache circuit portion and logic synthesis circuit portion.

Next with reference to Fig. 5 and Fig. 6, the action of V driver 5a of the liquid crystal indicator of the 2nd embodiment is described.In the V of this 2nd embodiment driver 5a, waveform signal after will reversing at the H current potential of commencing signal STV, frequency signal CKV1, frequency signal CKV2 and the enable signal ENB of the 1st embodiment shown in Figure 3 and L current potential is imported and signal STV, frequency signal CKV1, frequency signal CKV2 and enable signal ENB to start with.Whereby, from the shift cache circuit portion 501 to 505 of the 2nd embodiment, the signal that will have the waveform after reversing at the H current potential of the shift signal SR1 to SR5 of the shift cache circuit portion 51 to 55 of the 1st embodiment and L current potential is exported.In addition, from the logic synthesis circuit portion 801 to 803 of the 2nd embodiment, the signal that will have the H current potential of 81 to 83 output signal Dummy that exported of logic synthesis circuit portion at the 1st embodiment, Gate1, Gate2 and the L current potential waveform after reversing is exported.Other action of the V driver 5a of this 2nd embodiment, identical with the action of the V driver 5 of above-mentioned the 1st embodiment.

In the 2nd embodiment, by formation as above, can suppress the increase etc. of the power consumption of V driver 5a, therefore can obtain identical effect with above-mentioned the 1st embodiment.

(the 3rd embodiment)

With reference to Fig. 7, in the 3rd embodiment, illustrate in the formation of above-mentioned the 1st embodiment that the output that is connected in the 3rd section later shift cache circuit portion has the transistor drain of the node of displacement output signal, the supply enable signal replaces the situation of positive side current potential.

That is, as shown in Figure 7, in this 3rd embodiment, shift cache circuit portion 511 to 515, direction of scanning commutation circuit portion 610, input signal commutation circuit portion 710, and the logic synthesis circuit portion 811 to 813 of multistage of multistage is set.In Fig. 7,, only shown the logic synthesis circuit portion 811 to 813 of 511 to 515 and 3 sections parts of shift cache circuit portion of 5 sections parts, but in fact disposed respective number of pixels purpose shift cache circuit portion and logic synthesis circuit portion in order to simplify accompanying drawing.

In addition, the 1st section shift cache circuit portion 511 is constituted by having the 1st 511a of circuit part and the 2nd 511b of circuit part that the circuit identical with the 1st 51a of circuit part of the 1st section the shift cache circuit portion 51 of the 1st embodiment shown in Figure 2 and the 2nd 51b of circuit part constitute.In addition, the 2nd section shift cache circuit portion 512 is constituted by having the 1st 512a of circuit part and the 2nd 512b of circuit part that the circuit identical with the 1st 52a of circuit part of the 2nd section the shift cache circuit portion 52 of the 1st embodiment shown in Figure 2 and the 2nd 52b of circuit part constitute.

At this, in the 3rd embodiment,, connect enable signal line (ENB) respectively in the 3rd section shift cache circuit portion 513, the 4th section shift cache circuit portion 514 and the 5th section shift cache circuit portion 515.

Particularly, the 3rd section shift cache circuit portion 513 is made of the 1st 513a of circuit part and the 2nd 513b of circuit part.The 1st 513a of circuit part and the 2nd 513b of circuit part have the circuit identical with the 1st 53a of circuit part of the 3rd section the shift cache circuit portion 53 of the 1st embodiment shown in Figure 2 and the 2nd 53b of circuit part respectively and constitute.In the 3rd embodiment, enable signal line (ENB) is connected in the drain electrode of transistor NT24.

In addition, the 4th section shift cache circuit portion 514 is made of the 1st 514a of circuit part and the 2nd 514b of circuit part.The 1st 514a of circuit part and the 2nd 514b of circuit part have the circuit identical with the 1st 54a of circuit part of the 4th section the shift cache circuit portion 54 of the 1st embodiment shown in Figure 2 and the 2nd 54b of circuit part respectively and constitute.In the 3rd embodiment, enable signal line (ENB) is connected in the drain electrode of transistor NT34.

In addition, the 5th section shift cache circuit portion 515 is made of the 1st 515a of circuit part and the 2nd 515b of circuit part.The 1st 515a of circuit part and the 2nd 515b of circuit part have the circuit identical with the 1st 55a of circuit part of the 5th section the shift cache circuit portion 55 of the 1st embodiment shown in Figure 2 and the 2nd 55b of circuit part respectively and constitute.In the 3rd embodiment, enable signal line (ENB) is connected in the drain electrode of transistor NT44.

In addition, the direction of scanning commutation circuit portion 610 of the 3rd embodiment has the circuit identical with the direction of scanning commutation circuit portion 60 of the 1st embodiment shown in Figure 2 and constitutes.In the 3rd embodiment, the opposing party of the source/drain of transistor NT 56 is not connected with a side of the source/drain of transistor NT 57.

In addition, the input signal commutation circuit portion 710 of the 3rd embodiment has the circuit identical with the input signal commutation circuit portion 70 of the 1st embodiment shown in Figure 2 and constitutes.

With the logic synthesis circuit portion 811 that the dummy gate electrode line of the 3rd embodiment is connected, comprise transistor NT 81 to NT 84, form transistor NT 85, capacitor C 81 that diode connects.That is, the logic synthesis circuit portion 811 of the 3rd embodiment in the circuit of the logic synthesis circuit portion 81 of the 1st embodiment shown in Figure 2 constitutes, has and the circuit that forms the transistor NT86 that diode connects is not set constitutes.In addition, by transistor NT 83 to NT 85 and capacitor C 81, constitute the current potential permanent circuit 811a of portion.The node ND5 of the logic synthesis circuit portion 811 of the 3rd embodiment via transistor NT 85, and is connected in counter-rotating enable signal line (XENB).

In addition, with the logic synthesis circuit portion 812 that the 1st section gate line is connected, comprise transistor NT 91 to NT 94, form transistor NT 95 that diode connects, and capacitor C 91.That is, the logic synthesis circuit portion 812 of the 3rd embodiment is in the circuit of the logic synthesis circuit portion 82 of the 1st embodiment shown in Figure 2 constitutes, and has the circuit that forms the transistor NT 96 that diode connects is not set constitutes.In addition, constitute the current potential permanent circuit 812a of portion by transistor NT 93 to NT 95 and capacitor C 91.The node ND5 of the logic synthesis circuit portion 812 of the 3rd embodiment via transistor NT 95, and is connected in counter-rotating enable signal line (XENB).

In addition, with the logic synthesis circuit portion 813 that the 2nd section gate line is connected, comprise transistor NT 101 to NT 104, form transistor NT 105 that diode connects, and capacitor C 101.Also promptly, the logic synthesis circuit portion 813 of the 3rd embodiment is in the circuit of the logic synthesis circuit portion 83 of the 1st embodiment shown in Figure 2 constitutes, and has the circuit that forms the transistor NT 106 that diode connects is not set constitutes.In addition, by transistor NT 103 to NT 105 and capacitor C 101, constitute the current potential permanent circuit 813a of portion.The node ND5 of the logic synthesis circuit portion 813 of the 3rd embodiment via transistor NT 105, and is connected in counter-rotating enable signal line (XENB).

In addition, in the 3rd embodiment, except the shift cache circuit portion 511 to 515 of multistage, direction of scanning commutation circuit portion 610, input signal commutation circuit portion 710, and the logic synthesis circuit portion 811 to 813 of multistage, circuit part 910 is set again.This circuit part 910 comprises n channel transistor NT 111 to NT 113, forms the n channel transistor NT 114 of diode connection, reaches capacitor C 111.Below, respectively n channel transistor NT 111 to NT 114 is called transistor NT 111 to NT 114.

At this, in the 3rd embodiment, the transistor NT 111 of forming circuit portion 910 is to NT114, and the TFT that is formed by n type MOS transistor constitutes.

The drain electrode of transistor NT 111 is connected in enable signal line (ENB), and source electrode is connected in node ND6.The grid of this transistor NT 111 is connected in the node ND2 of the 2nd section shift cache circuit portion 512.The source electrode of transistor NT 112 is connected in minus side current potential VBB, and drain electrode is connected in node ND6.The grid of this transistor NT 112 is connected in node ND7.The source electrode of transistor NT 113 is connected in minus side current potential VBB, and drain electrode is connected in node ND7.The grid of this transistor NT 113 is connected in node ND6.One side's of capacitor C 111 electrode is connected in minus side current potential VBB, and the opposing party's electrode is connected in node ND7.In addition, node ND6 is connected in the opposing party of source/drain of the transistor NT 56 of direction of scanning commutation circuit portion 610.In addition, node ND7 is via transistor NT 114, and is connected in counter-rotating enable signal line (XENB).

Next with reference to Fig. 7 and Fig. 8, the action of V driver of the liquid crystal indicator of the 3rd embodiment is described.

The action of the V driver of this 3rd embodiment, identical with the action of the V driver 5 of above-mentioned the 1st embodiment basically.In the V of the 3rd embodiment driver, different with above-mentioned the 1st embodiment, be in output transistor NT 24, NT 34 that the node ND3 of the displacement output signal SR13 to SR15 of the shift cache circuit portion 513 to 515 after the 3rd section connected and the drain electrode of NT 44 to be arranged, supply enable signal ENB replaces positive side current potential VDD.In addition, transistor NT 83, NT 93 that between the minus side current potential VBB of the logic synthesis circuit portion 811 to 813 of each section and node ND4 that output signal is exported, is connected and the grid of NT 103, input counter-rotating enable signal XENB.

Particularly, the action of the shift cache circuit portion 511 and 512 (with reference to Fig. 7) of the 1st section and the 2nd section, identical with the action of the shift cache circuit portion 51 of shown in Figure 2 the 1st section and the 2nd section and 52.And the shift signal SR2 of H current potential (VDD+V α) inputs to the drain electrode of transistor NT 66 from the 2nd section shift cache circuit portion 512.Whereby, because of the direction of scanning switching signal CSV of the current potential of VDD is input to the source potential of the transistor NT 66 of grid conducting, become the current potential of (VDD-Vt).Therefore, current potential (VDD-Vt) is input to the grid of transistor NT 27 of the 3rd section shift cache circuit portion 513.In addition, the displacement output signal SR12 of H current potential (VDD) is input to the grid of transistor NT 21.In addition, the shift signal SR4 of L current potential inputs to the grid of transistor NT22 from the 4th section shift cache circuit portion 514.Whereby, transistor NT 21 and NT 27 become conducting state, and transistor NT22 becomes off state.Therefore, the current potential of L current potential is supplied from minus side current potential VBB via transistor NT 21, so the current potential of node ND1 can drop to the L current potential.Whereby, transistor NT 25 and NT 26 become off state.Under this state, the frequency signal CKV1 that is input into the drain electrode of transistor NT 27 can rise to the H current potential from the L current potential.Whereby, because the current potential of the node ND2 of the 3rd section shift cache circuit portion 513 rises to the H current potential, so transistor NT 24 becomes conducting state.At this moment, because the enable signal ENB of L current potential is provided to the drain electrode of transistor NT 24, so the source potential of transistor NT 24 (current potential of node ND3) remains on the L current potential.

Afterwards, in the 3rd embodiment, the current potential of enable signal ENB rises to the H current potential from the L current potential.Whereby, the current potential of the node ND3 of the 3rd section shift cache circuit portion 513 rises to the H current potential.At this moment, the current potential of the node ND2 of the 3rd section shift cache circuit portion 513 remains on the mode of voltage between the gate-to-source of transistor NT 24 with electric capacity 22, and the current potential that is accompanied by node ND3 rises and raises.Whereby, the current potential of the node ND2 of the 3rd section shift cache circuit portion 513 rises to the current potential of the amount of the above predetermined voltage (V β) of high threshold voltage (Vt) (till the VDD+V β＞VDD+Vt) also than VDD.The current potential (VDD+V β) of the node ND2 of this moment is the also high current potential of current potential (VDD+V α) than the node ND2 after the rising of above-mentioned the 1st embodiment.Afterwards, from the node ND2 of the 3rd section shift cache circuit portion 513, output has the shift signal SR3 of the H current potential of the above current potential (VDD+V β) of VDD+Vt.In addition, in the shift cache circuit portion 514 and 515 after the 4th section, also by the action identical with above-mentioned the 3rd section shift cache circuit portion 513, and the shift signal SR4 and the SR5 of the H current potential of the above current potential (VDD+V β) of the also high VDD+Vt of the shift signal of the current potential (VDD+V α) of the H current potential that output is exported than the shift cache circuit portion of above-mentioned the 1st embodiment.

The shift signal SR3 of the H current potential of the 3rd section shift cache circuit portion 513 inputs to the drain electrode of transistor NT 63 and NT 68 respectively.Whereby, the direction of scanning switching signal CSV of VDD current potential is inputed to grid and the transistor NT 63 of conducting and the source potential of NT 68, all become the current potential of (VDD-Vt).Therefore, current potential (VDD-Vt) is input to the grid of transistor NT 12 of the 2nd section shift cache circuit portion 512, and the grid of the transistor NT 37 of the 4th section shift cache circuit portion 514.Under this state, because the current potential of frequency signal CKV2 rises to H current potential (VDD) from L current potential (VBB), therefore, in the transistor NT 12 of the 2nd section shift cache circuit portion 512, owing to the mos capacitance of transistor NT 12 keeps voltage between gate-to-source, and grid potential is from the current potential difference of (VDD-Vt) rising VDD and VBB.Whereby, can suppress current potential that the node ND1 side of transistor NT 12 produced reduces the threshold voltage (Vt) of transistor NT 12 from VDD amount.The decline to the current potential of H current potential that therefore can be suppressed at that the node ND1 of the 2nd section shift cache circuit portion 512 produced.In addition, input at the current potential of (VDD-Vt) under the 4th section the state of grid of transistor NT 37 of shift cache circuit portion 514, frequency signal CKV2 rises to H current potential (VDD) from L current potential (VBB), therefore in transistor NT 37, owing to the mos capacitance of transistor NT 37 keeps voltage between gate-to-source, and grid potential is from the current potential difference of (VDD-Vt) rising VDD and VBB.Whereby, can suppress current potential that the node ND2 side of transistor NT 37 produced reduces the threshold voltage (Vt) of transistor NT 37 from VDD amount.The decline to the current potential of H current potential that therefore can be suppressed at that the node ND2 of the 4th section shift cache circuit portion 514 produced.As mentioned above, in the shift cache circuit portion of each section, rise to H current potential (VDD) being accompanied by frequency signal CKV1 or the current potential of CKV2, make under the situation that the current potential of node ND1 or node ND2 rises, can be suppressed at the decline of the current potential of the H current potential that node ND1 or node ND2 produced.

In addition, the shift signal SR3 of the H current potential of the 3rd section shift cache circuit portion 513 (VDD+V β) also inputs to the grid of the transistor NT 91 of the logic synthesis circuit portion 812 that is connected with the 1st section gate line.In addition, the shift signal SR4 of the H current potential of the 4th section shift cache circuit portion 514 (VDD+V β) inputs to the grid of the transistor NT 92 of the logic synthesis circuit portion 812 that is connected with the 1st section gate line.Whereby, with logic synthesis circuit portion 812 that the 1st section gate line is connected in, when the current potential of the enable signal ENB of the drain electrode that is input into transistor NT 91 rose to the current potential of H current potential (VDD), can suppress current potential that the node ND4 of transistor NT 92 produced became the current potential that reduces the H current potential behind the threshold voltage (Vt) of transistor NT 91 and NT 92 from VDD.As mentioned above, in the logic synthesis circuit portion 813 that gate line after with the 2nd section is connected, the current potential that is accompanied by enable signal ENB rises to the current potential of H current potential (VDD), and when the current potential of node ND4 is risen, and the current potential that can suppress the H current potential that node ND4 produced significantly reduces.

In addition, in the 3rd embodiment, in logic synthesis circuit portion 811 to 813, export the current potential of output signal of the gate line of each section to, be fixed on when the L current potential, adopt counter-rotating enable signal XENB to fix current potential.For example, with logic synthesis circuit portion 812 that the 1st section gate line is connected in, the enable signal ENB via transistor NT 91 that all becomes conducting state and NT 92 supply the H current potential whereby, makes the output signal Gate1 that exports the 1st section gate line to become the H current potential.Afterwards, the potential drop of enable signal ENB is low to moderate the L current potential, and the current potential of counter-rotating enable signal XENB rises to the H current potential.Whereby, the enable signal ENB of L current potential supplies via transistor NT 91 and NT 92, and therefore, the current potential of the output signal Gate1 of the 1st section gate line drops to the L current potential.

In addition, with logic synthesis circuit portion 812 that the 1st section gate line is connected in, because the current potential of counter-rotating enable signal XENB rises to the H current potential, so counter-rotating enable signal XENB of H current potential, the transistor NT 95 that system connects via the formation diode of logic synthesis circuit portion 812, and input to the grid of transistor NT 93.Whereby, make transistor NT 93 become conducting state.In addition, the current potential of L current potential is supplied to node ND4 side via transistor NT 93 from minus side current potential VBB.Whereby, the current potential that exports the output signal Gate1 of the 1st section gate line to from logic synthesis circuit portion 812 is fixed as the L current potential.

In addition, with logic synthesis circuit portion 812 that the 1st section gate line is connected in, when the counter-rotating enable signal XENB of H current potential is supplied to the grid of transistor NT 93, capacitor C 91 is charged.Whereby, the grid potential of transistor NT 93 (current potential of node ND5) because of transistor NT 94 becomes conducting state, and till supplying the current potential of L current potential via transistor NT 94 from minus side current potential VBB, remains on the H current potential next time.Therefore, owing to till transistor NT 94 becomes conducting state, make transistor NT 93 remain conducting state, therefore next time, current potential by the L current potential supplied from minus side current potential VBB via transistor NT 93 makes output signal Gate1 remain on the state that is fixed as the L current potential.As mentioned above, in the logic synthesis circuit portion 811 to 813 of each section, adopt counter-rotating enable signal XENB to make the current potential of output signal be fixed on the L current potential.

Action beyond the above-mentioned action of the V driver of the 3rd embodiment, identical with the action of the V driver of above-mentioned the 1st embodiment.

As mentioned above, in the 3rd embodiment, the output that is connected in shift cache circuit portion 513 to 515 has transistor NT 24, the NT 34 of the node ND3 of displacement output signal SR13 to SR15, the drain electrode of NT 44, be supplied the enable signal ENB that periodically switches positive side current potential VDD and minus side current potential VBB, whereby, for example in the 3rd section shift cache circuit portion 513, can source potential be changed into VDD from VBB during for conducting at transistor NT 24, therefore can make only the rise variation (V β) of this current potential of the grid potential of transistor NT 24.Whereby, be connected the situation of fixing minus side current potential VBB side, more can positively transistor NT 24 be remained on conducting state than the drain electrode of transistor NT 24.

In addition, as mentioned above, in the 3rd embodiment, in shift cache circuit portion 513 to 515, the enable signal line is connected in transistor NT 24, NT 34, the drain electrode of NT 44, and frequency signal CKV1 (CKV2) is supplied to grid, and ENB constitutes with enable signal, at frequency signal CKV1 (CKV2) after the L current potential rises to the H current potential, switch to the H current potential from the L current potential, whereby, for example, in the 3rd section shift cache circuit portion 513, be accompanied by because of frequency signal CKV1 makes the grid potential of transistor NT 24 and rise to H current potential (VDD) from L current potential (VBB), transistor NT 24 is become after the conducting state, can pass through enable signal ENB, make the source potential of transistor NT 24 rise to H current potential (VDD) from L current potential (VBB).Whereby, can make the grid potential of the transistor NT 24 of this moment, the ascending amount of the source potential of the transistor NT 24 that only rises (V β).In addition, in the 4th section shift cache circuit portion 514, be accompanied by because of frequency signal CKV2 makes the grid potential of transistor NT 34 and rise to H current potential (VDD) from L current potential (VBB), transistor NT 34 is become after the conducting state, can pass through enable signal ENB, make the source potential of transistor NT 34 rise to H current potential (VDD) from L current potential (VBB).Whereby, can make the grid potential of the transistor NT 34 of this moment, the ascending amount of the source potential of the transistor NT 34 that only rises (V β).Whereby, be connected the situation of fixing positive side current potential VDD side than the drain electrode of transistor NT 24 and transistor NT 34, (VDD+V β＞VDD+Vt) therefore more can be easily rises to the above current potential of high threshold voltage (Vt) also than VDD with the current potential of shift signal SR3 and SR4 more can to improve the current potential of shift signal SR3 and SR4.Therefore, can be more easily will have the shift signal SR3 and the SR4 of the above current potential of VDD+Vt, be supplied to the grid of transistor NT 91 of the logic synthesis circuit portion 812 that is connected with the 1st section gate line and the grid of transistor NT 92 respectively.Whereby, more can suppress via the transistor NT 91 of logic synthesis circuit portion 812 and transistor NT 92 and export the current potential of the displacement output signal Gate1 of the 1st section gate line to, the amount of falling-threshold value voltage (Vt).

Other effect of the 3rd embodiment is identical with above-mentioned the 1st embodiment.

(the 4th embodiment)

The 4th embodiment possesses the formation roughly the same with the 3rd embodiment.With reference to Fig. 9, be with the 3rd embodiment difference: will constitute transistor, and the transistor of circuit part 920 of logic synthesis circuit portion 821 to 823 of shift cache circuit portion 521 to 525, direction of scanning commutation circuit portion 620, input signal commutation circuit portion 720, the multistage of multistage, and change to the p channel transistor.In Fig. 9,, only shown the logic synthesis circuit portion 821 to 823 of 521 to 525 and 3 sections parts of shift cache circuit portion of 5 sections parts, but in fact disposed respective number of pixels purpose shift cache circuit portion and logic synthesis circuit portion in order to simplify accompanying drawing.

Next with reference to Fig. 9 and Figure 10, the action of the V driver of the 4th embodiment is described.

In the V of this 4th embodiment driver, waveform signal after will reversing at the H current potential of commencing signal STV, the frequency signal CKV1 of the 3rd embodiment shown in Figure 8, frequency signal CKV2, enable signal ENB and counter-rotating enable signal XENB and L current potential is imported with signal STV, frequency signal CKV1, frequency signal CKV2, enable signal ENB and counter-rotating enable signal XENB to start with.Whereby, from the shift cache circuit portion 521 to 525 of the 4th embodiment, the signal that will have the waveform after reversing at the H current potential of the shift signal SR1 to SR5 of the shift cache circuit portion 511 to 515 of the 3rd embodiment and L current potential is exported.In addition, from the logic synthesis circuit portion 821 to 823 of the 4th embodiment, the signal that will have the waveform after the H current potential of 811 to the 813 output signal Dummy that exported of logic synthesis circuit portion, Gate1, Gate2 of the 3rd embodiment and L current potential reverse is exported.Other action of the V driver of this 4th embodiment, identical with the action of the V driver of above-mentioned the 3rd embodiment.

In the 4th embodiment, by formation as above, can suppress the increase etc. of the current sinking of V driver, therefore can obtain identical effect with above-mentioned the 3rd embodiment.

(the 5th embodiment)

With reference to Figure 11, in the 5th embodiment, explanation is in the formation of above-mentioned the 3rd embodiment, and the output that is connected the 3rd section later shift cache circuit portion has the transistor drain of the node of displacement output signal, every one section situation of then supplying the different each other enable signal of sequential alternately.

That is, shown in 11 figure, in this 5th embodiment, shift cache circuit portion 531 to 535, direction of scanning commutation circuit portion 630, the input signal commutation circuit portion 730 of multistage, the logic synthesis circuit portion 831 to 833 and the circuit part 930 of multistage are set.In Figure 11, in order to simplify accompanying drawing, only shown the shift cache circuit portion 531 to 535 of 5 sections parts, and the logic synthesis circuit portion 831 to 833 of 3 sections parts, but in fact dispose respective number of pixels purpose shift cache circuit portion and logic synthesis circuit portion.

In addition, the 1st section shift cache circuit portion 531 is constituted by having the 1st 531a of circuit part and the 2nd 531b of circuit part that the circuit identical with the 1st 51a of circuit part of the 1st section the shift cache circuit portion 51 of the 1st embodiment shown in Figure 2 and the 2nd 51b of circuit part constitute.In addition, the 2nd section shift cache circuit portion 532 is constituted by having the 1st 532a of circuit part and the 2nd 532b of circuit part that the circuit identical with the 1st 52a of circuit part of the 2nd section the shift cache circuit portion 52 of the 1st embodiment shown in Figure 2 and the 2nd 52b of circuit part constitute.

At this, in the 5th embodiment, the shift cache circuit portion after the 3rd section 533 to 535 is supplied with the enable signal line of enable signal ENB1 every one period then mutual connection respectively, and the enable signal line that is supplied with enable signal ENB2.

Particularly, the 3rd section shift cache circuit portion 533 is made of the 1st 533a of circuit part and the 2nd 533b of circuit part.The 1st 533a of circuit part and the 2nd 533b of circuit part have the circuit identical with the 1st 53a of circuit part of the 3rd section the shift cache circuit portion 53 of the 1st embodiment shown in Figure 2 and the 2nd 53b of circuit part respectively and constitute.In the 5th embodiment, enable signal line (ENB1) is connected in the drain electrode of transistor NT 24.

In addition, the 4th section shift cache circuit portion 534 is made of the 1st 534a of circuit part and the 2nd 534b of circuit part.The 1st 534a of circuit part and the 2nd 534b of circuit part have the circuit identical with the 1st 54a of circuit part of the 4th section the shift cache circuit portion 54 of the 1st embodiment shown in Figure 2 and the 2nd 54b of circuit part respectively and constitute.In the 5th embodiment, enable signal line (ENB2) is connected in the drain electrode of transistor NT 34.

In addition, the 5th section shift cache circuit portion 535 is made of the 1st 535a of circuit part and the 2nd 535b of circuit part.The 1st 535a of circuit part and the 2nd 535b of circuit part have the circuit identical with the 1st 55a of circuit part of the 5th section the shift cache circuit portion 55 of the 1st embodiment shown in Figure 2 and the 2nd 55b of circuit part respectively and constitute.In the 5th embodiment, enable signal line (ENB1) is connected in the drain electrode of transistor NT 44.

In addition, the direction of scanning commutation circuit portion 630 of the 5th embodiment comprises transistor NT 51 to NT 55 and transistor NT 57 to NT 60.Also promptly, the direction of scanning commutation circuit portion 630 of the 5th embodiment has in the circuit of the direction of scanning of the 3rd embodiment shown in Figure 7 commutation circuit portion 610 constitutes, and has the circuit that transistor NT 56 is not set and constitutes.

In addition, the input signal commutation circuit portion 730 of the 5th embodiment has the circuit identical with the input signal commutation circuit portion 710 of the 3rd embodiment shown in Figure 7 and constitutes.

In addition, the logic synthesis circuit portion 831 to 833 of the 5th embodiment has the circuit identical with the logic synthesis circuit portion 811 to 813 of the 3rd embodiment shown in Figure 7 respectively and constitutes.

In addition, the circuit part 930 of the 5th embodiment has the circuit identical with the circuit part 910 of the 3rd embodiment shown in Figure 7 and constitutes.

Next with reference to Figure 11 and Figure 12, the action of V driver of the liquid crystal indicator of the 5th embodiment is described.

The action of the V driver of this 5th embodiment, identical with the action of the V driver of above-mentioned the 3rd embodiment basically.In the V of the 5th embodiment driver, different with above-mentioned the 3rd embodiment, in output transistor NT 24, NT 34 that the node ND3 of the displacement output signal SR13 to SR15 of the shift cache circuit portion 533 to 535 after the 3rd section connected and the drain electrode of NT 54 are arranged, supply sequential different each other enable signal ENB1 and ENB2 alternately.

Particularly, the action of the shift cache circuit portion 531 and 532 (with reference to Figure 11) of the 1st section and the 2nd section, identical with the action of the shift cache circuit portion 511 of the 1st section of the 3rd embodiment shown in Figure 7 and the 2nd section and 512.And the shift signal SR2 of H current potential (VDD+V α) inputs to the drain electrode of transistor NT 66 from the 2nd section shift cache circuit portion 532.Whereby, because of the direction of scanning switching signal CSV of the current potential of VDD is input to the source potential of the transistor NT 66 of grid conducting, become the current potential of (VDD-Vt).Therefore, current potential (VDD-Vt) is input to the grid of transistor NT 27 of the 3rd section shift cache circuit portion 533.In addition, the displacement output signal SR12 of H current potential (VDD) is input to the grid of transistor NT 21.In addition, the shift signal SR4 of L current potential inputs to the grid of transistor NT 22 from the 4th section shift cache circuit portion 534.Whereby, transistor NT 21 and NT 27 become conducting state, and transistor NT 22 becomes off state.Therefore, the current potential of L current potential is supplied from minus side current potential VBB via transistor NT 21, so the current potential of node ND1 can drop to the L current potential.Whereby, transistor NT 25 and NT 26 become off state.Under this state, the frequency signal CKV1 that is input into the drain electrode of transistor NT 27 can rise to the H current potential from the L current potential.Whereby, because the current potential of the node ND2 of the 3rd section shift cache circuit portion 533 rises to the H current potential, so transistor NT 24 becomes conducting state.At this moment, because the enable signal ENB1 of L current potential is provided to the drain electrode of transistor NT 24, so the source potential of transistor NT 24 (current potential of node ND3) remains on the L current potential.

Afterwards, in the 5th embodiment, the current potential of enable signal ENB1 rises to the H current potential from the L current potential.Whereby, the current potential of the node ND3 of the 3rd section shift cache circuit portion 533 rises to the H current potential.At this moment, the current potential of the node ND2 of the 3rd section shift cache circuit portion 533 is the mode that keeps voltage between the gate-to-source of transistor NT24 with electric capacity 22, and the current potential that is accompanied by node ND3 rises and raises.Whereby, the current potential of the node ND2 of the 3rd section shift cache circuit portion 533 rises to the current potential of the amount of the above predetermined voltage (V β) of high threshold voltage (Vt) (till the VDD+V β＞VDD+Vt) also than VDD.The current potential (VDD+V β) of the node ND2 of this moment is the also high current potential of current potential (VDD+V α) than the node ND2 after the rising of above-mentioned the 1st embodiment.Afterwards, from the node ND2 of the 3rd section shift cache circuit portion 533, output has the shift signal SR3 of the H current potential of the above current potential (VDD+V β) of VDD+Vt.

The shift signal SR3 of H current potential (VDD+V β) inputs to the drain electrode of transistor NT 68.Therefore, input to grid and the source potential of the transistor NT 68 of conducting, become the current potential of (VDD-Vt) by direction of scanning switching signal CSV with VDD.Therefore, current potential (VDD-Vt) is input to the grid of transistor NT 37 of the 4th section shift cache circuit portion 534.In addition, the displacement output signal SR13 of H current potential (VDD) inputs to the grid of transistor NT 31.In addition, the shift signal SR5 of L current potential owing to transistor NT 67, exports the grid of transistor NT 32 to from the 5th section shift cache circuit portion 535.Whereby, transistor NT 31 and NT 37 all become conducting state, and transistor NT 32 becomes off state.Therefore via transistor NT 31 from the current potential that minus side current potential VBB supplies the L current potential, make the potential drop of node ND1 be low to moderate the L current potential whereby.Whereby, transistor NT 35 and NT 36 all become conducting state.Afterwards, input to the current potential of frequency signal CKV2 of the drain electrode of transistor NT 37, rise to the H current potential from the L current potential.Whereby, because the current potential of the node ND2 of the 4th section shift cache circuit portion 534 rises to the H current potential, therefore, transistor NT 34 becomes conducting state.At this moment, because the enable signal ENB2 of L current potential is provided to the drain electrode of transistor NT34, so the source potential of transistor NT 34 (current potential of node ND3) remains on the L current potential.

Afterwards, in the 5th embodiment, the current potential of enable signal ENB2 rises to the H current potential from the L current potential.Whereby, the current potential of the node ND3 of the 4th section shift cache circuit portion 534 rises to the H current potential.At this moment, the current potential of the node ND2 of the 4th section shift cache circuit portion 534 is the mode that keeps voltage between the gate-to-source of transistor NT 34 with electric capacity 32, and the current potential that is accompanied by node ND3 rises and raises.Whereby, the current potential of the node ND2 of the 4th section shift cache circuit portion 534 rises to the current potential of the amount of the above predetermined voltage (V β) of high threshold voltage (Vt) (till the VDD+V β＞VDD+Vt) also than VDD.Afterwards, from the node ND2 of the 4th section shift cache circuit portion 534, output has the shift signal SR4 of the H current potential of the above current potential (VDD+V β) of VDD+Vt.

In the shift cache circuit portion after the 5th section shift cache circuit portion 535 and the 6th section, also carry out shift cache circuit portion 533 and 534 identical actions with above-mentioned the 3rd section and the 4th section.Promptly, in the 5th section shift cache circuit portion 535, make frequency signal CKV1 rise to the H current potential, make whereby after the current potential rising of node ND2, make enable signal ENB1 rise to the H current potential, whereby, the current potential of node ND2 is further risen, and become the H current potential (current potential of VDD+V β＞VDD+Vt).In the shift cache circuit portion of next section of the 5th section, make frequency signal CKV2 rise to the H current potential, make whereby after the current potential rising of node ND2, make enable signal ENB2 rise to the H current potential, whereby, the current potential of node ND2 is further risen, and become the H current potential (current potential of VDD+V β＞VDD+Vt).In the shift cache circuit portion of each section, carry out this action alternately.Whereby, the current potential of the shift signal of can be in regular turn the shift cache circuit portion of each section being exported rises to H current potential (VDD+V β＞VDD+Vt).

Action outside the above-mentioned action of the V driver of this 5th embodiment, identical with the action of the V driver of above-mentioned the 3rd embodiment.

As mentioned above, in the 5th embodiment, the output of the shift cache circuit portion 533 to 535 after being connected the 3rd section has the transistor NT 24 of the node ND3 of displacement output signal SR13 to SR15, NT 34, the drain electrode of NT 44, supplied sequential different each other enable signal ENB1 and ENB2 alternately, whereby, for example in the shift cache circuit portion 533 after the 3rd section, identical with the shift cache circuit portion 513 of above-mentioned the 3rd embodiment, be connected the situation of fixing positive side current potential VDD side than the drain electrode of transistor NT 24, more can improve grid potential (the VDD+V β＞VDD+Vt), therefore more can positively transistor NT 24 be remained on conducting state of transistor N T24.

In addition, in the 5th embodiment, adopt different each other enable signal ENB1 and the ENB2 of sequential, whereby, for example in the shift cache circuit portion 533 and 534 of adjacency each other, the transistor NT 24 that cooperates shift cache circuit portion 533 and the transistor NT 34 of shift cache circuit portion 534 be respectively in response to frequency signal CKV1 and CKV2 and the sequential of conducting, and with the source potential of transistor NT 24 with transistor NT 34, be VDD from the VBB change.In addition, at the transistor NT 34 of the transistor NT 24 of shift cache circuit portion 533 and shift cache circuit portion 534 respectively and before becoming off state, the source potential of transistor NT 24 and transistor NT 34 can be remained on VDD in response to frequency signal CKV1 and CKV2.Can be suppressed at transistor NT 24 and transistor NT 34 whereby respectively and between till becoming shutoff in response to frequency signal CKV1 and CKV2, the source potential of transistor NT 24 and transistor NT 34 of resulting from becomes VBB, and makes transistor NT 24 and the grid potential of transistor NT 34 produce the problem of change.At this moment, be input in the grid potential of transistor NT 24 (NT 34) under the situation of transistor NT 37 (NT 47) of shift cache circuit portion 534 (535) of next section, can suppress the instability of the action of transistor NT 37 (NT 47).In addition, also can suppress the timing sequence generating of transistor NT 37 (NT 47) conducting to be postponed because of the instability of the action of transistor NT 37 (NT 47), but the delay of the sequential when therefore the blanketing frequency signal inputs to the grid of transistor NT 34 (NT 44) via transistor NT 37 (NT 47).

In addition, as mentioned above, in the 5th embodiment, in shift cache circuit portion 533 to 535, frequency signal CKV1 and CKV2 are supplied to the grid of transistor NT 24, NT 34, NT 44 alternately, and enable signal ENB1 and ENB2 that sequential is different each other are supplied to drain electrode.Whereby, for example in the 3rd section shift cache circuit portion 533, be accompanied by because of frequency signal CKV1 makes the grid potential of transistor NT 24 and rise to H current potential (VDD) from L current potential (VBB), transistor NT 24 is become after the conducting state, can pass through enable signal ENB1, make the source potential of transistor NT 24 rise to H current potential (VDD) from L current potential (VBB).Whereby, can make the grid potential of the transistor NT 24 of this moment, the ascending amount of the source potential of the transistor NT 24 that only rises (V β).In addition, in the 4th section shift cache circuit portion 534, be accompanied by because of frequency signal CKV2 makes the grid potential of transistor NT 34 and rise to H current potential (VDD) from L current potential (VBB), transistor NT 34 is become after the conducting state, can make the source potential of transistor NT 34 rise to H current potential (VDD) by enable signal ENB2 from L current potential (VBB).Whereby, can make the grid potential of the transistor NT 34 of this moment, the ascending amount of the source potential of the transistor NT 34 that only rises (V β).Whereby, be connected the situation of fixing positive side current potential VDD side than the drain electrode of transistor NT 24 and transistor NT 34, more can improve current potential (the VDD+V β＞VDD+Vt) of shift signal SR3 and SR4, therefore more can be easily with the current potential of shift signal SR3 and SR4, rise to the above current potential of high threshold voltage (Vt) also than VDD.Therefore, can be more easily will have the shift signal SR3 and the SR4 of the above current potential of VDD+Vt, be supplied to the grid of transistor NT 91 of the logic synthesis circuit portion 832 that is connected with the 1st section gate line and the grid of transistor NT 92 respectively.Whereby, more can suppress via the transistor NT 91 of logic synthesis circuit portion 832 and transistor NT 92 and export the current potential of the displacement output signal Gate1 of the 1st section gate line to, the amount of falling-threshold value voltage (Vt).

In addition, in the 5th embodiment, adopt different each other enable signal ENB1 and the ENB2 of sequential, whereby, the transistor NT 27 that for example can cooperate the 3rd section shift cache circuit portion 533, and the sequential of the conducting of the transistor NT 37 of the 4th section shift cache circuit portion 534, make the source potential of transistor NT 27 and transistor NT 37 rise to H current potential (VDD) from L current potential (VBB).In addition, till the transistor NT 37 of the transistor NT 27 of shift cache circuit portion 533 and shift cache circuit portion 534 becomes off state respectively, the source potential of transistor NT 27 and transistor NT 37 can be remained on the H current potential.Can be suppressed at whereby between transistor NT 27 and transistor NT 37 become till the shutoff respectively, the source potential of transistor NT 27 and transistor NT 37 of resulting from drops to L current potential (VBB) and problem that the grid potential of transistor NT 27 and transistor NT 37 is descended.At this moment, also can suppress the current potential of the shift signal SR3 that exported from the node ND2 of the 3rd section shift cache circuit portion 533, and the current potential of the shift signal SR4 that is exported from the node ND2 of the 4th section shift cache circuit portion 534 reduces.Can suppress the action of transistor NT 91 that shift signal SR3 inputs to the logic synthesis circuit portion 832 of grid whereby, and the action of transistor NT 92 that shift signal SR4 inputs to the logic synthesis circuit portion 832 of grid produces unstable.

Other effect of the 5th embodiment is identical with above-mentioned the 3rd embodiment.

(the 6th embodiment)

The 6th embodiment possesses the formation roughly the same with the 5th embodiment.With reference to Figure 13, be with the 5th embodiment difference: will constitute shift cache circuit portion 541 to 515, direction of scanning commutation circuit portion 640, input signal commutation circuit portion 740, the logic synthesis circuit portion 841 to 843 of multistage and the transistor of circuit part 940 of multistage, and change to the p channel transistor.In Figure 13, in order to simplify accompanying drawing, only shown the shift cache circuit portion 541 to 545 of 5 sections parts, and the logic synthesis circuit portion 841 to 843 of 3 sections parts, but in fact dispose respective number of pixels purpose shift cache circuit portion and logic synthesis circuit portion.

Next with reference to Figure 13 and Figure 14, the action of the V driver of the 6th embodiment is described.

In the V of this 6th embodiment driver, waveform signal after will reversing at the H current potential of commencing signal STV, the frequency signal CKV1 of the 5th embodiment shown in Figure 12, frequency signal CKV2, enable signal ENB, enable signal ENB1, enable signal ENB2 and counter-rotating enable signal XENB and L current potential is imported with as commencing signal STV, frequency signal CKV1, frequency signal CKV2, enable signal ENB, enable signal ENB1, enable signal ENB2 and counter-rotating enable signal XENB.Whereby, from the shift cache circuit portion 541 to 545 of the 6th embodiment, the signal that will have the waveform after reversing from the H current potential of the shift signal SR1 to SR5 of the shift cache circuit portion 531 to 535 of the 5th embodiment and L current potential is exported.In addition, from the logic synthesis circuit portion 841 to 843 of the 6th embodiment, the signal that will have the waveform after the H current potential of 831 to the 833 output signal Dummy that exported of logic synthesis circuit portion, Gate1, Gate2 of the 5th embodiment and L current potential reverse is exported.Other action of the V driver of this 6th embodiment, identical with the action of the V driver of above-mentioned the 5th embodiment.

In the 6th embodiment, by formation as above, can suppress the increase etc. of the current sinking of V driver, therefore can obtain identical effect with above-mentioned the 5th embodiment.

(the 7th embodiment)

With reference to Figure 15, in this 7th embodiment, illustrate in the liquid crystal indicator of the 1st embodiment shown in Figure 1, the present invention is applicable to the situation of the H driver that is used for driving (scanning) drain line.

As shown in figure 15, inside at the H driver 4 of the liquid crystal indicator of this 7th embodiment, identical with the V driver 5 of the 1st embodiment shown in Figure 2, be provided with shift cache circuit portion 51 to 55, direction of scanning commutation circuit portion 60, the input signal commutation circuit portion 70 of multistage, the logic synthesis circuit portion 81 to 83 of multistage.In Figure 15,, only shown the logic synthesis circuit portion 81 to 83 of 51 to 55 and 3 sections parts of shift cache circuit portion of 5 sections parts, but in fact disposed respective number of pixels purpose shift cache circuit portion and logic synthesis circuit portion in order to simplify accompanying drawing.In the 7th embodiment, logic synthesis circuit portion 81 to 83 is connected to each other with transversal switch 3.

Particularly, transversal switch 3 comprises the n channel transistor NT 121 to NT 123 of the hop count of counterlogic combiner circuit portion 81 to 83.Below respectively n channel transistor NT 121 to NT 123 is called transistor NT 121 to NT 123.

In addition, the source electrode of transistor NT 121 is connected in the dummy gate electrode line, and drain electrode is connected in video signal cable (Video).The grid of this transistor NT 121 is connected in the node ND4 of logic synthesis circuit portion 81.In addition, the source electrode of transistor NT 122 is connected the 1st section drain line, and drain electrode is connected in video signal cable (Video).The grid of this transistor NT 122 is connected in the node ND4 of logic synthesis circuit portion 82.In addition, the source electrode of transistor NT 123 is connected in the 2nd section drain line, and drain electrode is connected in video signal cable (video).The grid of this transistor NT 123 is connected in the node ND4 of logic synthesis circuit 83.

Next with reference to Figure 15, the transversal switch 3 of liquid crystal indicator of the 7th embodiment and the action of H driver 4 are described.In the H of this 7th embodiment driver 4, the output signal of the H current potential of exporting in regular turn from the logic synthesis circuit portion 81 to 83 of each section inputs to the grid of the transistor NT 121 to NT 123 of pairing transversal switch 3 respectively.Whereby, each section transistor NT 121 to NT 123 of transversal switch 3 becomes conducting state in regular turn.Therefore, vision signal exports the drain line of each section in regular turn via each section transistor NT 121 to NT 123 of transversal switch 3 from video signal cable (Video).Action beyond the H driver 4 of this 7th embodiment above-mentioned, identical with the action of the V driver 5 of above-mentioned the 1st embodiment.

In the 7th embodiment,,, also can obtain to suppress the effect of the increase etc. of current sinking even in H driver 4 by above-mentioned formation.

(the 8th embodiment)

With reference to Figure 16, in this 8th embodiment, the situation that the present invention is applicable to the organic electroluminescence display device that comprises the pixel with n channel transistor is described.

Promptly, as shown in figure 16, in the 8th embodiment, be on substrate 1b, to form display part 6, at this display part 6 with the rectangular pixel 60 that disposes, this pixel 60 comprise n channel transistor 61 and 62 (hereinafter referred to as transistor 61 and 62), auxiliary capacitor 63, anode 64, negative electrode 65 and be clamped in anode 64 and negative electrode 65 between organic electroluminescent element 66.At the display part 6 of Figure 16, shown the formation of 1 pixel.In addition, the source electrode of transistor 61 is connected in the grid of transistor 62 and side's electrode of auxiliary capacitor 63, and drain electrode is connected in drain line.The grid of this transistor 61 is connected gate line.In addition, the source electrode of transistor 62 is connected in anode 64, and drain electrode then is connected in the electric current supply line (not shown).

Formation beyond the above-mentioned part of the organic electroluminescence display device of the 8th embodiment is identical with the liquid crystal indicator of the 1st embodiment shown in Figure 1.

In the 8th embodiment, by above-mentioned formation, in organic electroluminescence display device, also can suppress the increase etc. of the power consumption of V driver 5, therefore can obtain identical effect with above-mentioned the 1st embodiment.In addition, even when organic electroluminescence display device is carried out bilateral scanning, also can suppress the increase of the power consumption of V driver 5.

(the 9th embodiment)

With reference to Figure 17, in this 9th embodiment, the situation that the present invention is applicable to the organic electroluminescence display device that comprises the pixel with p channel transistor is described.

Also be, as shown in figure 17, in the 9th embodiment, be on substrate 1c, to form display part 6a, at this display part 6a with the rectangular pixel 60a that disposes, this pixel 60a comprise p channel transistor 61a and 62a (hereinafter referred to as transistor 61a and 62a), auxiliary capacitor 63a, anode 64a, negative electrode 65a and be clamped in anode 64a and negative electrode 65a between organic electroluminescent element 66a.At the display part 6a of Figure 17, shown the formation of 1 pixel.In addition, the source electrode of transistor 61a is connected in drain line, and drain electrode is connected in the grid of transistor 62a and side's electrode of auxiliary capacitor 63a.The grid of transistor 61a is connected in gate line.In addition, the source electrode of transistor 62a is connected in the electric current supply line (not shown), and drain electrode then is connected in anode 64a.

Formation beyond the above-mentioned part of the organic electroluminescence display device of the 9th embodiment is identical with the liquid crystal indicator of the 2nd embodiment shown in Figure 4.

In the 9th embodiment, by above-mentioned formation, in organic electroluminescence display device, also can suppress the increase etc. of the power consumption of V driver 5a, therefore can obtain identical effect with above-mentioned the 2nd embodiment.In addition, even when organic electroluminescence display device is carried out bilateral scanning, also can suppress the increase of the power consumption of V driver 5a.

The embodiment that is this time disclosed, all explanations all only are used for illustration, are not to have restrictive sense.Scope of the present invention is not the explanation by the foregoing description, but is disclosed by claim, in addition, with the equal meaning and scope of claim in, scope of the present invention comprises all changes.

For example, in above-mentioned the 1st to the 9th embodiment, demonstrate the example that the present invention is used for liquid crystal indicator and organic electroluminescence display device, but the present invention is not limited thereto, also applicable to the display device beyond liquid crystal indicator and the organic electroluminescence display device.

In addition, in above-mentioned the 1st to the 9th embodiment, demonstrates the present invention is used for H driver and any example of V driver, but the present invention is not limited thereto, also the present invention can be used for H driver and V driver both.In the case, more can suppress the increase of power consumption.

In addition, in above-mentioned the 1st to the 9th embodiment, demonstrate being that the shift signal of next section of predetermined section is as the 1st signal with respect to the direction of scanning, and being that the shift signal of the last period of predetermined section comes to be adopted as the 2nd signal with respect to the direction of scanning, but the present invention is not limited thereto, as long as the 1st signal and the 2nd signal can not become the current potential person that can make transistor conducting simultaneously, also can adopt shift signal signal in addition, be used as the 1st signal and the 2nd signal.

In addition, in above-mentioned the 7th embodiment, demonstrate all with the n channel transistor, constitute the transistorized example that H driver of the present invention is adopted, but the present invention is not limited thereto, and also can constitute the transistor that H driver of the present invention is adopted all with the p channel transistor.

In addition, in the 1st, the 3rd, the 5th, the 7th and the 8th embodiment that adopts the n channel transistor, can constitute all electric capacity by the n channel transistor.In addition, in the 2nd, the 4th, the 6th, the 9th embodiment that adopts the p channel transistor, can constitute all electric capacity by the p channel transistor.

Claims (14)

1, a kind of display device possesses shift cache circuit, and this shift cache circuit comprises:

The 1st shift cache circuit portion (52,53,54,55,502,503,504,505,512,513,514,515,522,523,524,525,532,533,534,535,542,543,544,545), transistor by the 1st conduction type is constituted, and exports the 1st shift signal;

The 2nd shift cache circuit portion (52,53,54,55,502,503,504,505,512,513,514,515,522,523,524,525,532,533,534,535,542,543,544,545), transistor by the 1st conduction type is constituted, and export the 2nd shift signal, and be configured in next section of above-mentioned the 1st shift cache circuit portion; And

Logic synthesis circuit portion (81,82,83,801,802,803,811,812,813,821,822,823,831,832,833,841,842,843), it is synthetic that above-mentioned the 1st shift signal and the 2nd shift signal are carried out logic, and output displacement output signal.

2, display device according to claim 1, wherein, above-mentioned logic synthesis circuit portion comprises:

The 1st transistor of the 1st conduction type (NT 81, NT 91, NT 101, PT 81, PT 91, PT 101), one side of source/drain is connected in and is used for supplying the 1st signal wire that makes the 1st signal that the 1st current potential and the 2nd current potential switch, and above-mentioned the 1st shift signal is input to grid; And

The 2nd transistor of the 1st conduction type (NT 81, NT 91, NT 101, PT 81, PT 91, PT 101), a side of source/drain is connected in the opposing party of above-mentioned the 1st transistorized source/drain, and above-mentioned the 2nd shift signal is input to grid;

When above-mentioned the 1st shift signal and above-mentioned the 2nd shift signal are above-mentioned the 1st current potential, above-mentioned the 1st transistor and above-mentioned the 2nd transistor are conducting state, and from above-mentioned the 1st signal wire, with above-mentioned the 1st signal provision of above-mentioned the 1st current potential a side to above-mentioned the 1st transistorized source/drain, whereby, the above-mentioned displacement output signal of above-mentioned the 1st current potential is via above-mentioned the 1st transistor and above-mentioned the 2nd transistor and export;

At above-mentioned the 1st shift signal when above-mentioned the 1st potential change is above-mentioned the 2nd current potential, from above-mentioned the 1st signal wire, with above-mentioned the 1st signal provision of above-mentioned the 2nd current potential a side to above-mentioned the 1st transistorized source/drain, whereby, the above-mentioned displacement output signal of above-mentioned the 2nd current potential is via above-mentioned the 1st transistor and above-mentioned the 2nd transistor and export.

3, display device according to claim 2, wherein, above-mentioned the 1st signal become above-mentioned the 2nd current potential during, above-mentioned being forced to property of displacement output signal remains on above-mentioned the 2nd current potential.

4, display device according to claim 2, wherein, above-mentioned logic synthesis circuit portion comprises current potential permanent circuit portion (81a, 82a, 83a, 801a, 802a, 803a, 811a, 812a, 813a, 821a, 822a, 823a, 831a, 832a, 833a, 841a, 842a, 843a), it, is used for above-mentioned output signal is fixed on above-mentioned the 2nd current potential at above-mentioned the 1st shift signal after above-mentioned the 1st potential change is above-mentioned the 2nd current potential.

5, display device according to claim 4, wherein, above-mentioned current potential permanent circuit portion comprises the 3rd transistor (NT 83, NT 93, NT 103, PT 83, PT 93, PT 103) of the 1st conduction type, it is connected between above-mentioned the 2nd current potential side and above-mentioned the 2nd transistor, and when above-mentioned the 1st shift signal becomes above-mentioned the 2nd current potential, the prearranged signals of above-mentioned the 1st current potential is input into grid, becomes conducting state whereby.

6, display device according to claim 5, wherein, above-mentioned shift cache circuit comprises the 3rd shift cache circuit portion of next section of the 2nd shift cache circuit portion;

When above-mentioned the 1st potential change is above-mentioned the 2nd current potential,, the output signal of above-mentioned the 1st current potential is inputed to the above-mentioned the 3rd transistorized grid at above-mentioned the 1st shift signal from above-mentioned the 3rd shift cache circuit portion.

7, display device according to claim 5 wherein, at the above-mentioned the 3rd transistorized grid, from being used for supplying the 2nd signal wire that makes the 2nd signal that above-mentioned the 1st current potential and above-mentioned the 2nd current potential switch, is supplied above-mentioned the 2nd signal;

When above-mentioned the 1st shift signal became above-mentioned the 2nd current potential, above-mentioned the 2nd signal of above-mentioned the 1st current potential inputed to the above-mentioned the 3rd transistorized grid from above-mentioned the 2nd signal wire.

8, display device according to claim 5 wherein, between the above-mentioned the 3rd transistorized grid and source electrode, is connected with the 1st electric capacity (C 81, C 91, C 101).

9, display device according to claim 5, wherein, above-mentioned current potential permanent circuit portion comprises: be connected in the above-mentioned the 3rd transistorized grid, and carry out the 4th transistor (NT 85, NT 86, NT 95, NT 96, NT 105, NT 106, PT 85, PT 86, PT 95, PT 96, PT 105, PT 106) of the 1st conduction type that diode connects; Above-mentioned prearranged signals inputs to the above-mentioned the 3rd transistorized grid via above-mentioned the 4th transistor.

10, display device according to claim 5 wherein, when above-mentioned the 3rd transistor is above-mentioned the 1st current potential at above-mentioned the 1st shift signal and above-mentioned the 2nd shift signal, becomes off state.

11, display device according to claim 10, wherein, above-mentioned current potential permanent circuit portion comprises the 5th transistor (NT 84, NT 94, NT 104, PT 84, PT 94, PT 104) of the 1st conduction type, it is connected between above-mentioned the 2nd current potential side and the above-mentioned the 3rd transistorized grid, when above-mentioned the 1st shift signal and above-mentioned the 2nd shift signal are above-mentioned the 1st current potential, via above-mentioned the 1st transistor and above-mentioned the 2nd transistor, the above-mentioned output signal of above-mentioned the 1st current potential is inputed to grid, become conducting state whereby.

12, display device according to claim 2, wherein, above-mentioned the 1st shift cache circuit portion comprises: the 6th transistor (NT 14, NT 24, NT 34, NT 44, PT 14, PT 24, PT 34, PT 44), at above-mentioned the 1st current potential of drain electrode supply, and grid is connected in the node that output has above-mentioned the 1st shift signal; And the 2nd electric capacity (C 12, C 22, C 32, C 42), be connected between the above-mentioned the 6th transistorized grid and the source electrode;

Above-mentioned the 2nd shift cache circuit portion comprises: the 7th transistor (NT 14, NT 24, NT34, NT 44, PT 14, PT 24, PT 34, PT 44), and at above-mentioned the 1st current potential of drain electrode supply, and grid is connected in the node that output has above-mentioned the 2nd shift signal; And the 3rd electric capacity (C 12, C 22, C 32, C 42), be connected between the above-mentioned the 7th transistorized grid and the source electrode;

The above-mentioned the 6th transistorized grid potential is in the mode of voltage between the above-mentioned the 6th transistorized gate-to-source of keeping above-mentioned the 2nd electric capacity and being connected, along with the rising of above-mentioned the 6th transistorized source potential or decline and rise or descend;

The above-mentioned the 7th transistorized grid potential is in the mode of voltage between the above-mentioned the 7th transistorized gate-to-source of keeping above-mentioned the 3rd electric capacity and being connected, along with the rising of above-mentioned the 7th transistorized source potential or decline and rise or descend.

13, display device according to claim 12 wherein, in above-mentioned the 6th transistor drain, is connected with and is used for supplying the 3rd signal wire that makes the 3rd signal that above-mentioned the 1st current potential and above-mentioned the 2nd current potential switch, and supply the 1st frequency signal to grid;

In above-mentioned the 7th transistor drain, be connected with above-mentioned the 3rd signal wire that is used for supplying above-mentioned the 3rd signal, and supply the 2nd frequency signal grid;

After above-mentioned the 2nd current potential became above-mentioned the 1st current potential, and above-mentioned the 2nd frequency signal switched to above-mentioned the 1st current potential from above-mentioned the 2nd current potential respectively to above-mentioned the 3rd signal after above-mentioned the 2nd current potential becomes above-mentioned the 1st current potential at above-mentioned the 1st frequency signal.

14, display device according to claim 12 wherein, in above-mentioned the 6th transistor drain, is connected with and is used for supplying the 3rd signal wire that makes the 3rd signal that above-mentioned the 1st current potential and above-mentioned the 2nd current potential switch, and supply the 1st frequency signal to grid;

In above-mentioned the 7th transistor drain, be connected with and be used for supplying the 4th signal wire that makes the 4th signal that above-mentioned the 1st current potential and above-mentioned the 2nd current potential switch, and supply the 2nd frequency signal grid;

Above-mentioned the 3rd signal after above-mentioned the 2nd current potential becomes above-mentioned the 1st current potential, switches to above-mentioned 1st current potential from above-mentioned the 2nd current potential at above-mentioned the 1st frequency signal;

Above-mentioned the 4th signal after above-mentioned the 2nd current potential becomes above-mentioned the 1st current potential, switches to above-mentioned 1st current potential from above-mentioned the 2nd current potential at above-mentioned the 2nd frequency signal.

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