CN101325414B - Input/output circuit and input control circuit - Google Patents
Input/output circuit and input control circuit Download PDFInfo
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- CN101325414B CN101325414B CN2008101444254A CN200810144425A CN101325414B CN 101325414 B CN101325414 B CN 101325414B CN 2008101444254 A CN2008101444254 A CN 2008101444254A CN 200810144425 A CN200810144425 A CN 200810144425A CN 101325414 B CN101325414 B CN 101325414B
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Abstract
The invention relates to an input control circuit in an integrated circuit, an input circuit and an input/output circuit, wherein the input/output circuit comprises a pin, an input end, a power input end and input control circuit, which includes a first PMOS pipe, a second PMOS pipe, an NMOS pipe, an input enable end and an input enable inverter. The source of the first PMOS pipe is connected with the input end of the power; the grid of the first PMOS pipe and the grid of the NMOS pipe are respectively connected with the input enable end; the drain of the first PMOS pipe, the source of the second PMOS pipe and the drain of the NMOS pipe are respectively connected with the input enable inverter; the drain of the second PMOS pipe and the source of the NMOS pipe are respectively connected with the pin P.
Description
Technical field
The present invention relates to integrated circuit, relate in particular to a kind of input/output circuitry and input control circuit.
Background technology
In recent years, the portable consumer electronic product has obtained significant progress, is replacing the first-selection that the conditional electronic product becomes people's consumption gradually.Because the particularity of portable consumer electronic product, an important performance indexes of this electronic product is the stream time after the charging, be cruising time, for a lot of users, the length in cruising time is to weigh a product whether to be worth one of deciding factor of buying.
The input/output circuitry of integrated circuit (IC) chip (hereinafter to be referred as the I/O circuit) is the interface that integrated circuit (IC) chip and external circuitry are carried out exchanges data, it is a kind of circuit of importing and can be used for exporting of promptly can be used for, because a large amount of uses of integrated circuit (IC) chip in the portable consumer electronic product, the I/O circuit has obtained using widely in the portable consumer electronic product, therefore, the I/O circuit catabiotic what can directly have influence on cruising time of portable consumer electronic product.
A kind of I/O circuit of the prior art as shown in Figure 1, wherein O is an output, I is an input, P is a pin, OE is the output enable end, B
1Be triple gate, B
2Be input control circuit, V
DDBe power input, V
SSBe earth terminal.When OE end during for high potential, this circuit is used for dateout, promptly from output O to pin P Data transmission; When OE end during for electronegative potential, this circuit is used to import data, promptly from pin P to input I Data transmission.
Input control circuit B in the above-mentioned I/O circuit
2Concrete structure as shown in Figure 2, input control circuit B
2Comprise two P-channel field-effect transistor (PEFT) pipes (hereinafter to be referred as the PMOS pipe) P
21, P
22, and two N channel field-effect pipes (hereinafter to be referred as the NMOS pipe) N
21, N
22, V wherein
DDEnd connects power supply, P
21, P
22Source potential be high potential, V
SSEnd ground connection, N
21, N
22Source potential be zero potential, I is an input, P is a pin, A is an intermediate node.Neither do output when this I/O circuit and use, also do not do input and use, and pin P is when unsettled, pin P is in high-impedance state, at this moment, owing to have parasitic capacitance in PMOS pipe and the NMOS pipe, these parasitic capacitances can be discharged or charge when pin P is unsettled at leisure, and therefore cause the current potential of pin P from V
DDHigh potential taper to V
SSZero potential, or from V
SSZero potential taper to V
DDHigh potential.If NMOS pipe on state threshold voltage is V
TN, PMOS pipe on state threshold voltage is V
TP, V
TPBe negative value, then the current potential V of ordering as P
PMeet the following conditions
V
TN＜V
P＜(V
DD-|V
TP|)
V
TN＜V
A＜(V
DD-|V
TP|)
Therefore, P
22And N
22Also conducting simultaneously, like this, V
DDAnd V
SSBetween formed following two current paths:
V
DD-P
21-N
21-V
SS
V
DD-P
22-N
22-V
SS
Thereby caused V
DDAnd V
SSBetween electric energy occurs and run off the energy loss when having caused the P point unsettled.
In addition, when OE is a high potential, when this I/O circuit was used to export, the potential change of output O can be passed through input control circuit B
2Be delivered to input I, the circuit that can cause connecting input I is subjected to the interference of output signal, and can be because the connection inlet circuit is interfered and causes electric energy loss; And I/O circuit structure of the prior art also can form interference to the circuit that connects input as signal output the time.
Because a large amount of uses of I/O circuit in chip, I/O circuit of the prior art for these reasons and the electric energy loss meeting that produces significantly improves the power consumption of portable consumer electronic product, thereby shorten the cruising time of portable consumer electronic product.
Summary of the invention
The embodiment of the invention provides a kind of input control circuit, is used to reduce the electric energy loss of input circuit and input/output circuitry.
The embodiment of the invention also provides a kind of input circuit that is used for integrated circuit, is used for reducing the electric energy loss of integrated circuit input circuit.
The embodiment of the invention also provides a kind of input/output circuitry that is used for integrated circuit, is used for reducing the electric energy loss of integrated circuit input/output circuitry.
The input control circuit that the embodiment of the invention provides can comprise: the first P-channel field-effect transistor (PEFT) pipe (P
31), the second P-channel field-effect transistor (PEFT) pipe (P
32), a N channel field-effect pipe (N
31), the 2nd N channel field-effect pipe (N
32), input Enable Pin (IE) and input inverter, wherein:
The first P-channel field-effect transistor (PEFT) pipe (P
31) the source electrode and the second P-channel field-effect transistor (PEFT) pipe (P
32) source electrode connect power input (V respectively
DD);
The first P-channel field-effect transistor (PEFT) pipe (P
31) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
32) drain electrode and the 2nd N channel field-effect pipe (N
32) drain electrode connect input (I) by input inverter respectively;
The first P-channel field-effect transistor (PEFT) pipe (P
31) a grid and a N channel field-effect pipe (N
31) grid connect respectively the input Enable Pin (IE);
The second P-channel field-effect transistor (PEFT) pipe (P
32) grid and the 2nd N channel field-effect pipe (N
32) grid connect pin (P) respectively;
The one N channel field-effect pipe (N
31) source electrode connect earth terminal (V
SS);
The one N channel field-effect pipe (N
31) drain electrode and the 2nd N channel field-effect pipe (N
32) source electrode link to each other.
The input control circuit that the embodiment of the invention provides also can comprise: the first P-channel field-effect transistor (PEFT) pipe (P
41), the second P-channel field-effect transistor (PEFT) pipe (P
42), N channel field-effect pipe (N
41), the input Enable Pin (IE) and the input enable inverter, wherein:
The first P-channel field-effect transistor (PEFT) pipe (P
41) source electrode connect power input (V
DD);
The first P-channel field-effect transistor (PEFT) pipe (P
41) grid and N channel field-effect pipe (N
41) grid connect respectively the input Enable Pin (IE);
The first P-channel field-effect transistor (PEFT) pipe (P
41) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
42) source electrode and N channel field-effect pipe (N
41) drain electrode connect input (I) respectively;
The second P-channel field-effect transistor (PEFT) pipe (P
42) grid connect input and enable inverter;
The second P-channel field-effect transistor (PEFT) pipe (P
42) drain electrode and N channel field-effect pipe (N
41) source electrode connect pin (P) respectively.
The input circuit that the embodiment of the invention provides can comprise pin (P), input (I), power input (V
DD), earth terminal (V
SS) and input control circuit (B
3), wherein, input control circuit (B
3) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
31), the second P-channel field-effect transistor (PEFT) pipe (P
32), a N channel field-effect pipe (N
31), the 2nd N channel field-effect pipe (N
32), input Enable Pin (IE) and input inverter, wherein:
The first P-channel field-effect transistor (PEFT) pipe (P
31) the source electrode and the second P-channel field-effect transistor (PEFT) pipe (P
32) source electrode connect power input (V respectively
DD);
The first P-channel field-effect transistor (PEFT) pipe (P
31) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
32) drain electrode and the 2nd N channel field-effect pipe (N
32) drain electrode connect input (I) by input inverter respectively;
The first P-channel field-effect transistor (PEFT) pipe (P
31) a grid and a N channel field-effect pipe (N
31) grid connect respectively the input Enable Pin (IE);
The second P-channel field-effect transistor (PEFT) pipe (P
32) grid and the 2nd N channel field-effect pipe (N
32) grid connect pin (P) respectively;
The one N channel field-effect pipe (N
31) source electrode connect earth terminal (V
SS);
The one N channel field-effect pipe (N
31) drain electrode and the 2nd N channel field-effect pipe (N
32) source electrode link to each other.
The input circuit that the embodiment of the invention provides also can comprise pin (P), input (I), power input (V
DD) and input control circuit (B
4), wherein, input control circuit (B
4) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
41), the second P-channel field-effect transistor (PEFT) pipe (P
42), N channel field-effect pipe (N
41), the input Enable Pin (IE) and the input enable inverter, wherein:
The first P-channel field-effect transistor (PEFT) pipe (P
41) source electrode connect power input (V
DD);
The first P-channel field-effect transistor (PEFT) pipe (P
41) grid and N channel field-effect pipe (N
41) grid connect respectively the input Enable Pin (IE);
The first P-channel field-effect transistor (PEFT) pipe (P
41) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
42) source electrode and N channel field-effect pipe (N
41) drain electrode connect input (I) respectively;
The second P-channel field-effect transistor (PEFT) pipe (P
42) grid connect input and enable inverter;
The second P-channel field-effect transistor (PEFT) pipe (P
42) drain electrode and N channel field-effect pipe (N
41) source electrode connect pin (P) respectively.
The input/output circuitry that the embodiment of the invention provides can comprise pin (P), input (I), power input (V
DD), earth terminal (V
SS), input control circuit (B
3), output (O), output enable end (OE) and triple gate (B
1), output (O) and triple gate (B
1) input connect output enable end (OE) and triple gate (B
1) the control Enable Pin connect pin (P) and triple gate (B
1) output connect, wherein, input control circuit (B
3) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
31), the second P-channel field-effect transistor (PEFT) pipe (P
32), a N channel field-effect pipe (N
31), the 2nd N channel field-effect pipe (N
32), input Enable Pin (IE) and input inverter, wherein:
The first P-channel field-effect transistor (PEFT) pipe (P
31) the source electrode and the second P-channel field-effect transistor (PEFT) pipe (P
32) source electrode connect power input (V respectively
DD);
The first P-channel field-effect transistor (PEFT) pipe (P
31) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
32) drain electrode and the 2nd N channel field-effect pipe (N
32) drain electrode connect input (I) by input inverter respectively;
The first P-channel field-effect transistor (PEFT) pipe (P
31) a grid and a N channel field-effect pipe (N
31) grid connect respectively the input Enable Pin (IE);
The second P-channel field-effect transistor (PEFT) pipe (P
32) grid and the 2nd N channel field-effect pipe (N
32) grid connect pin (P) respectively;
The one N channel field-effect pipe (N
31) source electrode connect earth terminal (V
SS);
The one N channel field-effect pipe (N
31) drain electrode and the 2nd N channel field-effect pipe (N
32) source electrode link to each other.
The input/output circuitry that the embodiment of the invention provides also can comprise pin (P), input (I), power input (V
DD), input control circuit (B
4), output (O), output enable end (OE) and triple gate (B
1), output (O) and triple gate (B
1) input connect output enable end (OE) and triple gate (B
1) the control Enable Pin connect pin (P) and triple gate (B
1) output connect, wherein, input control circuit (B
4) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
41), the second P-channel field-effect transistor (PEFT) pipe (P
42), N channel field-effect pipe (N
41), the input Enable Pin (IE) and the input enable inverter, wherein:
The first P-channel field-effect transistor (PEFT) pipe (P
41) source electrode connect power input (V
DD);
The first P-channel field-effect transistor (PEFT) pipe (P
41) grid and N channel field-effect pipe (N
41) grid connect respectively the input Enable Pin (IE);
The first P-channel field-effect transistor (PEFT) pipe (P
41) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
42) source electrode and N channel field-effect pipe (N
41) drain electrode connect input (I) respectively;
The second P-channel field-effect transistor (PEFT) pipe (P
42) grid connect input and enable inverter;
The second P-channel field-effect transistor (PEFT) pipe (P
42) drain electrode and N channel field-effect pipe (N
41) source electrode connect pin (P) respectively.
The technical scheme that adopts the embodiment of the invention to provide, can significantly reduce the electric energy loss that input control circuit, input circuit and input/output circuitry are produced when pin is unsettled, greatly reduce the power consumption of the portable consumer electronic product that adopts these circuit, thereby prolonged the cruising time of portable consumer electronic product.
Description of drawings
Fig. 1 is an input/output circuitry schematic diagram of the prior art;
Fig. 2 is the circuit diagram of input/output circuitry input control circuit of the prior art;
Fig. 3 is the circuit diagram of the input control circuit that provides in the embodiment of the invention;
Fig. 4 is the another kind of circuit diagram of the input control circuit that provides in the embodiment of the invention;
Fig. 5 is a kind of circuit diagram of the input/output circuitry that provides in the embodiment of the invention;
Fig. 6 is the another kind of circuit diagram of the input/output circuitry that provides in the embodiment of the invention.
Embodiment
The embodiment of the invention provides a kind of input control circuit that can be used in the integrated circuit, a kind of input circuit and a kind of input/output circuitry (hereinafter to be referred as the I/O circuit), these three kinds of circuit can reduce the energy loss of pin when unsettled effectively, save electric energy to reach, improve the portable consumer electronic product purpose in cruising time; Simultaneously, the I/O circuit that provides in the embodiment of the invention can also reduce the interference of output signal to input when circuit is used to export, reduce the electric energy loss that inlet circuit produces because of being interfered simultaneously.
Fig. 3 is a kind of circuit diagram of the input control circuit that provides of the embodiment of the invention, as shown in Figure 3, and input control circuit B
3Comprise: two PMOS pipe P
31And P
32, and two NMOS pipe N
31And N
32, V
DDConnect power supply, P
31And P
32Source potential be high potential, V
SSGround connection, N
31Source potential be zero potential, N
32Source potential according to N
31Conduction status and decide; Input control circuit B
3Also comprise pin P, input Enable Pin IE and input inverter.Wherein:
P
31Source electrode and P
32Source electrode connect power input V respectively
DD
P
31Drain electrode, P
32Drain electrode and N
32Drain electrode connect input I by input inverter respectively;
P
31Grid and N
31Grid connect input Enable Pin IE respectively;
P
32Grid and N
32Grid connect pin P respectively;
N
31Source electrode connect earth terminal V
SS
N
31Drain electrode and N
32Source electrode link to each other.
As this input control circuit B
3When being used to import, input Enable Pin IE is a high potential, so P
31End N
31Conducting, at this moment this input control circuit B
3Can realize normal input function, for example when pin P is high potential, P
32End N
32Conducting, N
31Conducting simultaneously, V
SSElectronegative potential be converted to high potential by input inverter, thereby input I is the high potential consistent with P; When pin P is electronegative potential, P
32Conducting, N
32End V
DDHigh potential be converted to electronegative potential by input inverter, thereby input I is the electronegative potential consistent with P.
As this input control circuit B
3Be not used in input, when pin P is unsettled, IE is set as electronegative potential, this moment P
31Conducting, N
31End, therefore the current potential as unsettled pin P satisfies condition
V
TN＜V
P＜(V
DD-|V
TP|)
The time, P
32With N
32Conducting simultaneously, but because N
31End V
DDWith V
SSBetween can not form current path, therefore electric energy can not occur and run off, reduced the electric energy loss when pin P is unsettled.
Fig. 4 is the another kind of circuit diagram of the input control circuit that provides of the embodiment of the invention, as shown in Figure 4, and input control circuit B
4Comprise: two PMOS pipe P
41And P
42, and a NMOS pipe N
41, V
DDConnect power supply, P
41Source potential be high potential, P
42Source potential according to P
41Conduction status and decide; Input control circuit B
4Comprise that also pin P, input Enable Pin IE, input enable inverter and input I.Wherein:
P
41Source electrode connect power input V
DD
P
41Grid and N
41Grid connect input Enable Pin IE respectively;
P
41Drain electrode, P
42Source electrode and N
41Drain electrode connect input I respectively;
P
42Grid enable inverter by input and connect input Enable Pin IE;
P
42Drain electrode and N
41Source electrode connect pin P respectively.
As this input control circuit B
4When being used to import, input Enable Pin IE is a high potential, so P
41End N
41And P
42Conducting, this moment, the value of pin P can be passed to input I, this input control circuit B
4Can realize normal input function, for example when pin P is high potential, because N
41And P
42Conducting, so I is the high potential consistent with P; When pin P was electronegative potential, I was the electronegative potential consistent with P.
When this input control circuit be not used in input, when pin P is unsettled, input Enable Pin IE is set as electronegative potential, so P
41Conducting, N
41And P
42End.This moment is because V
DDWith do not have circuit to link to each other between the circuit ground end, can not form current path, therefore no matter why the current potential of pin P is worth, and can not occur because V
DDAnd V
SSBetween form path and the situation that causes electric energy to run off, reduced the electric energy loss when pin P is unsettled.
By the above-mentioned input control circuit that adopts the embodiment of the invention to provide, when input Enable Pin IE was high potential, above-mentioned input control circuit can be realized normal input function, when input Enable Pin IE is electronegative potential, and can be at V
DDWith V
SSBetween form current path, be not used in the electric energy loss when unsettled of input and pin thereby reduced above-mentioned input control circuit.
The input circuit that the embodiment of the invention provides can comprise pin P, input I, power input V
DD, earth terminal V
SS, input Enable Pin IE and input control circuit B
3, input control circuit B
3Particular circuit configurations and aforementioned input control circuit B
3Identical, as shown in Figure 3.
When this input circuit was used to import, input Enable Pin IE was a high potential, so P
31End N
31Conducting, at this moment this input circuit can be realized normal input function, for example when pin P is high potential, P
32End N
32Conducting, N
31Conducting simultaneously, V
SSElectronegative potential be converted to high potential by input inverter, thereby input I is the high potential consistent with P; When pin P is electronegative potential, P
32Conducting, N
32End V
DDHigh potential be converted to electronegative potential by input inverter, thereby input I is the electronegative potential consistent with P.
When this input circuit be not used in input, when pin P is unsettled, IE is set as electronegative potential, this moment P
31Conducting, N
31End, therefore the current potential as unsettled pin P satisfies condition
V
TN＜V
P＜(V
DD-|V
TP|)
The time, P
32With N
32Conducting simultaneously, but because N
31End V
DDWith V
SSBetween can not form current path, therefore electric energy can not occur and run off, reduced the electric energy loss when pin P is unsettled.
The input circuit that the embodiment of the invention provides also can comprise pin P, input I, power input V
DD, input Enable Pin IE and input control circuit B
4, input control circuit B
4Particular circuit configurations and aforementioned input control circuit B
4Identical, as shown in Figure 4.
When this input circuit was used to import, input Enable Pin IE was a high potential, so P
41End N
41And P
42Conducting, this moment, the value of pin P can be passed to input I, and this input circuit can be realized normal input function, for example when pin P is high potential, because N
41And P
42Conducting, so I is the high potential consistent with P; When pin P was electronegative potential, I was the electronegative potential consistent with P.
When this input circuit be not used in input, when pin P is unsettled, input Enable Pin IE is set as electronegative potential, so P
41Conducting, N
41And P
42End.This moment is because V
DDWith do not have circuit to link to each other between the circuit ground end, can not form current path, therefore no matter why the current potential of pin P is worth, and can not occur because V
DDAnd V
SSBetween form path and the situation that causes electric energy to run off, reduced the electric energy loss when pin P is unsettled.
By the above-mentioned input circuit that adopts the embodiment of the invention to provide, when input Enable Pin IE was high potential, above-mentioned input circuit can be realized normal input function, when input Enable Pin IE is electronegative potential, and can be at V
DDWith V
SSBetween form current path, be not used in the electric energy loss when unsettled of input and pin thereby reduced above-mentioned input circuit.
As shown in Figure 5, the I/O circuit that provides of the embodiment of the invention can comprise pin P, input I, power input V
DD, earth terminal V
SS, output O, output enable end OE and triple gate B
1, wherein output O and triple gate B
1Input connect output enable end OE and triple gate B
1The control Enable Pin connect pin P and triple gate B
1Output connect; With respect to I/O circuit of the prior art shown in Figure 1, this I/O circuit that the embodiment of the invention provides comprises input control circuit B
3With input Enable Pin IE, input control circuit B
3Particular circuit configurations and aforementioned input control circuit B
3Identical, as shown in Figure 3.
When this I/O circuit was used to import, input Enable Pin IE was a high potential, so P
31End N
31Conducting, at this moment this I/O circuit can be realized normal input function, for example when pin P is high potential, P
32End N
32Conducting, N
31Conducting simultaneously, V
SSElectronegative potential be converted to high potential by input inverter, thereby input I is the high potential consistent with P; When pin P is electronegative potential, P
32Conducting, N
32End V
DDHigh potential be converted to electronegative potential by input inverter, thereby input I is the electronegative potential consistent with P.
When this I/O circuit was used to export, IE was set as electronegative potential, at this moment P
31Conducting, N
31End V
DDHigh potential be converted to fixing electronegative potential by input inverter at input I, even if therefore be delivered to input I to the signal of pin P output from output O, because input I is fixing electronegative potential, the circuit that connects input I also can not be subjected to the interference of output signal, has reduced the electric energy loss that connects the circuit of input I and produce because be interfered.
When this I/O circuit both had been not used in input, also has been not used in output, and pin P is when unsettled, and IE is set as electronegative potential, this moment P
31Conducting, N
31End, therefore the current potential as unsettled pin P satisfies condition
V
TN＜V
P＜(V
DD-|V
TP|)
The time, P
32With N
32Conducting simultaneously, but because N
31End V
DDWith V
SSBetween can not form current path, therefore electric energy can not occur and run off, reduced the electric energy loss when pin P is unsettled.
As shown in Figure 6, the I/O circuit that provides of the embodiment of the invention also can comprise pin P, input I, power input V
DD, output O, output enable end OE and triple gate B
1, wherein output O and triple gate B
1Input connect output enable end OE and triple gate B
1The control Enable Pin connect pin P and triple gate B
1Output connect; With respect to I/O circuit of the prior art shown in Figure 1, this I/O circuit that the embodiment of the invention provides comprises input control circuit B
4With input Enable Pin IE, input control circuit B
4Particular circuit configurations and aforementioned input control circuit B
4Identical, as shown in Figure 4.
When this I/O circuit was used to import, input Enable Pin IE was a high potential, so P
41End N
41And P
42Conducting, this moment, the value of pin P can be passed to input I, and this I/O circuit can be realized normal input function, for example when pin P is high potential, because N
41And P
42Conducting, so I is the high potential consistent with P; When pin P was electronegative potential, I was the electronegative potential consistent with P.
When this I/O circuit was used to export, input Enable Pin IE was set as electronegative potential, so P
41Conducting, N
14And P
42End.This moment is because P
41Conducting, input I is fixing high potential, and N
41And P
42End, the potential change of pin P can not influence input I, therefore can not be passed to input I from output O to the signal of pin P output, reduce the interference of output signal, reduce the electric energy loss that connects the circuit of input I and produce because be interfered to input I institute connecting circuit.
When this I/O circuit both had been not used in input, also has been not used in output, and pin P is when unsettled, and input Enable Pin IE is set as electronegative potential, so P
41Conducting, N
41And P
42End.This moment is because V
DDWith do not have circuit to link to each other between the circuit ground end, can not form current path, therefore no matter why the current potential of pin P is worth, and can not occur because V
DDAnd V
SSBetween form path and the situation that causes electric energy to run off, reduced the electric energy loss when pin P is unsettled.
By the above-mentioned I/O circuit that adopts the embodiment of the invention to provide, when input Enable Pin IE was high potential, above-mentioned I/O circuit can be realized normal input function, and when input Enable Pin IE was electronegative potential, input was changed to fixing electronegative potential, and can be at V
DDWith V
SSBetween form current path, thereby when above-mentioned I/O circuit is used to export, reduced the interference that output signal causes inlet circuit, and both be not used in input at above-mentioned I/O circuit and also be not used in when output, reduced the electric energy loss when pin is unsettled.
In sum, the input control circuit that provides in the embodiment of the invention, input circuit and I/O circuit all comprise an input Enable Pin IE, when these three kinds of circuit are used to import, can be made as the on off operating mode that high potential changes the part metal-oxide-semiconductor in the input control circuit by importing Enable Pin IE, to realize normal input operation; Also be not used in output and pin when unsettled when these three kinds of circuit both have been not used in input, can be made as the on off operating mode that electronegative potential changes the part metal-oxide-semiconductor in the input control circuit by importing Enable Pin IE, to avoid at V
DDWith V
SSBetween form current path.
The input control circuit that provides in the embodiment of the invention, input circuit and I/O circuit all can be realized normal input function when being used as input circuit; Also be not used in when output both being not used in input, these three kinds of circuit can reduce pin issuable electric energy loss when unsettled; And when above-mentioned I/O circuit was used as output, this I/O circuit can reduce the interference that output signal causes inlet circuit, reduced the electric energy loss that produces when inlet circuit is interfered.Therefore, the input control circuit that provides in the embodiment of the invention, input circuit and I/O circuit can reduce the electric energy loss of self greatly, thereby reduce the power consumption of portable consumer electronic product, prolong the cruising time of portable consumer electronic product.
Obviously, those skilled in the art can carry out various changes and distortion to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within claim of the present invention and the equivalent technologies scope thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (6)
1. an input control circuit is characterized in that, described input control circuit comprises:
The first P-channel field-effect transistor (PEFT) pipe (P
31), the second P-channel field-effect transistor (PEFT) pipe (P
32), a N channel field-effect pipe (N
31), the 2nd N channel field-effect pipe (N
32), input Enable Pin (IE) and input inverter, wherein:
The described first P-channel field-effect transistor (PEFT) pipe (P
31) the source electrode and the second P-channel field-effect transistor (PEFT) pipe (P
32) source electrode connect power input (V respectively
DD);
The described first P-channel field-effect transistor (PEFT) pipe (P
31) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
32) drain electrode and the 2nd N channel field-effect pipe (N
32) drain electrode connect input (I) by input inverter respectively;
The described first P-channel field-effect transistor (PEFT) pipe (P
31) a grid and a N channel field-effect pipe (N
31) grid connect respectively the input Enable Pin (IE);
The described second P-channel field-effect transistor (PEFT) pipe (P
32) grid and the 2nd N channel field-effect pipe (N
32) grid connect pin (P) respectively;
A described N channel field-effect pipe (N
31) source electrode connect earth terminal (V
SS);
A described N channel field-effect pipe (N
31) drain electrode and the 2nd N channel field-effect pipe (N
32) source electrode link to each other.
2. an input control circuit is characterized in that, described input control circuit comprises:
The first P-channel field-effect transistor (PEFT) pipe (P
41), the second P-channel field-effect transistor (PEFT) pipe (P
42), N channel field-effect pipe (N
41), the input Enable Pin (IE) and the input enable inverter, wherein:
The described first P-channel field-effect transistor (PEFT) pipe (P
41) source electrode connect power input (V
DD);
The described first P-channel field-effect transistor (PEFT) pipe (P
41) grid and N channel field-effect pipe (N
41) grid connect respectively the input Enable Pin (IE);
The described first P-channel field-effect transistor (PEFT) pipe (P
41) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
42) source electrode and N channel field-effect pipe (N
41) drain electrode connect input (I) respectively;
The described second P-channel field-effect transistor (PEFT) pipe (P
42) grid connect input and enable inverter;
The described second P-channel field-effect transistor (PEFT) pipe (P
42) drain electrode and N channel field-effect pipe (N
41) source electrode connect pin (P) respectively.
3. an input circuit comprises pin (P), input (I), power input (V
DD), earth terminal (V
SS) and input control circuit (B
3), it is characterized in that described input control circuit (B
3) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
31), the second P-channel field-effect transistor (PEFT) pipe (P
32), a N channel field-effect pipe (N
31), the 2nd N channel field-effect pipe (N
32), input Enable Pin (IE) and input inverter, wherein:
The described first P-channel field-effect transistor (PEFT) pipe (P
31) the source electrode and the second P-channel field-effect transistor (PEFT) pipe (P
32) source electrode connect power input (V respectively
DD);
The described first P-channel field-effect transistor (PEFT) pipe (P
31) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
32) drain electrode and the 2nd N channel field-effect pipe (N
32) drain electrode connect input (I) by input inverter respectively;
The described first P-channel field-effect transistor (PEFT) pipe (P
31) a grid and a N channel field-effect pipe (N
31) grid connect respectively the input Enable Pin (IE);
The described second P-channel field-effect transistor (PEFT) pipe (P
32) grid and the 2nd N channel field-effect pipe (N
32) grid connect pin (P) respectively;
A described N channel field-effect pipe (N
31) source electrode connect earth terminal (V
SS);
A described N channel field-effect pipe (N
31) drain electrode and the 2nd N channel field-effect pipe (N
32) source electrode link to each other.
4. an input circuit comprises pin (P), input (I), power input (V
DD) and input control circuit (B
4), it is characterized in that described input control circuit (B
4) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
41), the second P-channel field-effect transistor (PEFT) pipe (P
42), N channel field-effect pipe (N
41), the input Enable Pin (IE) and the input enable inverter, wherein:
The described first P-channel field-effect transistor (PEFT) pipe (P
41) source electrode connect power input (V
DD);
The described first P-channel field-effect transistor (PEFT) pipe (P
41) grid and N channel field-effect pipe (N
41) grid connect respectively the input Enable Pin (IE);
The described first P-channel field-effect transistor (PEFT) pipe (P
41) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
42) source electrode and N channel field-effect pipe (N
41) drain electrode connect input (I) respectively;
The described second P-channel field-effect transistor (PEFT) pipe (P
42) grid connect input and enable inverter;
The described second P-channel field-effect transistor (PEFT) pipe (P
42) drain electrode and N channel field-effect pipe (N
41) source electrode connect pin (P) respectively.
5. an input/output circuitry comprises pin (P), input (I), power input (V
DD), earth terminal (V
SS), input control circuit (B
3), output (O), output enable end (OE) and triple gate (B
1), output (O) and triple gate (B
1) input connect output enable end (OE) and triple gate (B
1) the control Enable Pin connect pin (P) and triple gate (B
1) output connect, it is characterized in that described input control circuit (B
3) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
31), the second P-channel field-effect transistor (PEFT) pipe (P
32), a N channel field-effect pipe (N
31), the 2nd N channel field-effect pipe (N
32), input Enable Pin (IE) and input inverter, wherein:
The described first P-channel field-effect transistor (PEFT) pipe (P
31) the source electrode and the second P-channel field-effect transistor (PEFT) pipe (P
32) source electrode connect power input (V respectively
DD);
The described first P-channel field-effect transistor (PEFT) pipe (P
31) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
32) drain electrode and the 2nd N channel field-effect pipe (N
32) drain electrode connect input (I) by input inverter respectively;
The described first P-channel field-effect transistor (PEFT) pipe (P
31) a grid and a N channel field-effect pipe (N
31) grid connect respectively the input Enable Pin (IE);
The described second P-channel field-effect transistor (PEFT) pipe (P
32) grid and the 2nd N channel field-effect pipe (N
32) grid connect pin (P) respectively;
A described N channel field-effect pipe (N
31) source electrode connect earth terminal (V
SS);
A described N channel field-effect pipe (N
31) drain electrode and the 2nd N channel field-effect pipe (N
32) source electrode link to each other.
6. an input/output circuitry comprises pin (P), input (I), power input (V
DD), input control circuit (B
4), output (O), output enable end (OE) and triple gate (B
1), output (O) and triple gate (B
1) input connect output enable end (OE) and triple gate (B
1) the control Enable Pin connect pin (P) and triple gate (B
1) output connect, it is characterized in that described input control circuit (B
4) comprising:
The first P-channel field-effect transistor (PEFT) pipe (P
41), the second P-channel field-effect transistor (PEFT) pipe (P
42), N channel field-effect pipe (N
41), the input Enable Pin (IE) and the input enable inverter, wherein:
The described first P-channel field-effect transistor (PEFT) pipe (P
41) source electrode connect power input (V
DD);
The described first P-channel field-effect transistor (PEFT) pipe (P
41) grid and N channel field-effect pipe (N
41) grid connect respectively the input Enable Pin (IE);
The described first P-channel field-effect transistor (PEFT) pipe (P
41) drain electrode, the second P-channel field-effect transistor (PEFT) pipe (P
42) source electrode and N channel field-effect pipe (N
41) drain electrode connect input (I) respectively;
The described second P-channel field-effect transistor (PEFT) pipe (P
42) grid connect input and enable inverter;
The described second P-channel field-effect transistor (PEFT) pipe (P
42) drain electrode and N channel field-effect pipe (N
41) source electrode connect pin (P) respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101444254A CN101325414B (en) | 2008-07-29 | 2008-07-29 | Input/output circuit and input control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101444254A CN101325414B (en) | 2008-07-29 | 2008-07-29 | Input/output circuit and input control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101325414A CN101325414A (en) | 2008-12-17 |
| CN101325414B true CN101325414B (en) | 2011-04-06 |
Family
ID=40188784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101444254A Expired - Fee Related CN101325414B (en) | 2008-07-29 | 2008-07-29 | Input/output circuit and input control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101325414B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101932157B (en) * | 2010-06-24 | 2015-04-01 | 深圳市中庆微科技开发有限公司 | LED constant-current driven chip input circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760606A (en) * | 1995-04-17 | 1998-06-02 | Matsushita Electric Industrial, Co. | High voltage withstanding circuit and voltage level shifter |
| CN1293488A (en) * | 1999-10-15 | 2001-05-02 | 威盛电子股份有限公司 | Single-terminal input voltage level converter controlled by grid voltage |
-
2008
- 2008-07-29 CN CN2008101444254A patent/CN101325414B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760606A (en) * | 1995-04-17 | 1998-06-02 | Matsushita Electric Industrial, Co. | High voltage withstanding circuit and voltage level shifter |
| CN1293488A (en) * | 1999-10-15 | 2001-05-02 | 威盛电子股份有限公司 | Single-terminal input voltage level converter controlled by grid voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101325414A (en) | 2008-12-17 |
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Address after: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: ACTIONS TECHNOLOGY Co.,Ltd. Address before: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee before: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. |
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