CN101321403B - Time slot interchanger - Google Patents
Time slot interchanger Download PDFInfo
- Publication number
- CN101321403B CN101321403B CN2008101089303A CN200810108930A CN101321403B CN 101321403 B CN101321403 B CN 101321403B CN 2008101089303 A CN2008101089303 A CN 2008101089303A CN 200810108930 A CN200810108930 A CN 200810108930A CN 101321403 B CN101321403 B CN 101321403B
- Authority
- CN
- China
- Prior art keywords
- channel
- data
- time slot
- signal
- transmission capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 71
- 238000012545 processing Methods 0.000 claims abstract description 60
- 230000015654 memory Effects 0.000 claims description 55
- 238000003860 storage Methods 0.000 claims description 47
- 230000005039 memory span Effects 0.000 claims description 8
- RGNPBRKPHBKNKX-UHFFFAOYSA-N hexaflumuron Chemical compound C1=C(Cl)C(OC(F)(F)C(F)F)=C(Cl)C=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F RGNPBRKPHBKNKX-UHFFFAOYSA-N 0.000 claims 2
- 230000005055 memory storage Effects 0.000 description 13
- 230000006870 function Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 5
- 102100040338 Ubiquitin-associated and SH3 domain-containing protein B Human genes 0.000 description 4
- 101710143616 Ubiquitin-associated and SH3 domain-containing protein B Proteins 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/08—Time only switching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13103—Memory
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13163—Fault alarm
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13393—Time slot switching, T-stage, time slot interchanging, TSI
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
Abstract
There is provided a time slot interchanger for processing channel setting data functioning as control data for interchanging time slots of multiplexed transmission data. In the time slot interchanger, processing of the channel setting data based on alarm data is performed in accordance with a preset first transmission capacity, and with respect to the channel setting data in accordance with a preset second transmission capacity, processing of the channel setting data in accordance with the first transmission capacity is dispersedly performed in a time series manner.
Description
Technical field
Time slot interchanger relates to the technology that is used to exchange the time slot of distributing to a plurality of transmission data; Even and when relating more specifically to the exchange when the time slot of distributing to high power capacity transmission data; Be used for the basic circuit reprocessing channel that processing channel is provided with the low memory capacity of data (channel is provided with the information of data with the time slot that acts on exchange transmission data) through use data are set, also can suppress the increase of circuit scale.
Summary of the invention
One side according to execution mode; Time slot interchanger comprises: first memory; Be used for being used for the data that processing channel is provided with data according to the first preset transmission capacity repeated storage of disperseing with the time series mode; So that the second transmission capacity processing channel according to preset is provided with data, this first memory has the memory span corresponding to first transmission capacity; And second memory, being used for data and alarm data being set according to the second transmission capacity memory channel, this second memory has the memory span corresponding to second transmission capacity; Wherein first transmission capacity is the 1/n (n: integer) of second transmission capacity.
According to the one side of execution mode, when the channel with the information of the time slot that acts on exchange transmission data was provided with data and is processed, the channel of all channels that hold was provided with not lump of data and handles, and need not to provide the memory corresponding to all channels.And, the 1/n that has corresponding to the memory span of all channels is provided (n: the basic circuit of memory span integer), and through using this basic circuit, the channel of all channels is provided with data and can be processed for n time through repeating to handle.This allows to dwindle and is used for the size that processing channel is provided with the circuit of data.
In addition, when channel was provided with the processing capacity and increases, the number of repetition of processing that can be through increasing basic circuit adapted to the increase that this channel is provided with the processing capacity, and need not to increase the circuit like memory.
Description of drawings
Fig. 1 is the figure that node device has constituted the system of two loop networks;
Fig. 2 is the figure that constitutes the system of interconnection;
Fig. 3 is the device block diagram;
Fig. 4 is the function constitution map that channel is provided with data processing section;
Fig. 5 shows the figure of the signal format that channel that channel is provided with data and alarm data constitutes;
The channel that Fig. 6 shows each channel is provided with the figure of signal format of the arrangement of data and alarm data;
The channel that Fig. 7 shows each channel is provided with the figure of signal format of the formation of data;
Fig. 8 shows the figure of signal format of formation of the alarm data of each channel;
Fig. 9 is the figure of the signal format in channel is provided with data processing section, used;
Figure 10 is about constituting the sequential chart of signal that channel is provided with the MEM part (storage area) of data processing section;
Figure 11 be about constitute channel be provided with data processing section the sequential chart of signal;
Figure 12 is at the figure that constitutes the signal format between each function that channel is provided with data processing section;
Figure 13 is at the figure that constitutes the signal format between each function that channel is provided with data processing section;
Figure 14 is at the figure that constitutes the signal format between each function that channel is provided with data processing section;
Figure 15 is at the figure that constitutes the signal format between each function that channel is provided with data processing section;
Figure 16 is that channel is provided with the figure that channel that data processing section notified to address control memory part is provided with the signal format of data;
Figure 17 shows the figure of 480Gbps capacity processing capacity; And
Figure 18 shows the figure of 480Gbps capacity sequential.
Embodiment
Below, will describe execution mode in detail with reference to accompanying drawing.In these accompanying drawings, same or analogous assembly is by identical symbol indication.
Fig. 1 shows: a plurality of node devices have constituted two loop networks, and each node device is as the time slot interchanger with interpolation (Add)/unload (Drop)/multiplexing (MUX) function.Node device 1 to 5 constitutes the loop network RN1 of a 2F-BLSR (2 fiber bi-directional line switched ring) scheme, and node device 6 to 9 has constituted the loop network RN2 of a 2F-BLSR scheme.Node device 1 and 3 is connected respectively to node device 6 and 7 through the low speed side circuit, thereby has set up ring interconnection, even make and in the low speed side circuit, fault occurred, between loop network RN1 and RN2, also can communicate.
The structure that two BLSR networks are interconnected comprises that DCP (protection bandwidth abandon and continue) structure constructs with DTP (the two of protection bandwidth transmit).The DCP structure is such structure; Wherein use the protection channel to set up host node equipment (primary nodedevice) and the connection between the auxilliary node device (secondary node device) in the same loop network, and wherein end-node equipment (terminal node device) is positioned at outside host node equipment and the auxilliary node device.The DTP structure is such structure, and wherein terminal node equipment is between host node equipment and auxilliary node device.
In Fig. 1, loop network RN1 has the DTP structure.In loop network RN1, node device 1 is as host node equipment, and node device 3 is as auxilliary node device, and node device 2 is as end-node equipment.On the other hand, loop network RN2 has the DCP structure.In loop network RN2, node device 6 is as host node equipment, and node device 7 is as auxilliary node device, and node device 9 is as end-node equipment.
Fig. 2 shows the overview of the required function of the flow process of explaining the signal through interconnection, with interconnected nodes equipment 1,2 in the system construction in the pie graph 1 and 3 and node device 6,7 and 9 relevant.
Here, following example is described: flow process from the low speed side circuit (91) of the terminal node equipment 9 that constitutes loop network RN2 to the signal of the low speed side circuit (22) of the terminal node equipment 2 of formation loop network RN1.(interpolation point) 91 is inserted among the loop network RN2 in the insertion point from the signal of the low speed side circuit (91) of terminal node equipment 9; And after component (removal part) 62 branches of host node equipment 6; Insert loop network RN1 via low speed side circuit (62) in interpolation part 11, as the signal on the circuit (11) of the host node equipment 1 that constitutes loop network RN1.In addition; The protection bandwidth that this signal also passes through loop network RN2 from the removal part 62 of host node equipment 6; And removal part 72 branches at auxilliary node device 7; Thereby insert loop network RN1 via low speed side circuit (72) in interpolation part 31, as the signal on the circuit (31) of the auxilliary node device 3 that constitutes loop network RN1.These are inserted into signal among the loop network RN1 in each the removal part 22a and the 22b branch of terminal node equipment 2, and are input to path switching part (PSW part) 23.If on the downside channel of host node equipment 6 and host node equipment 1, do not have fault, then PSW part 23 is selected signal from removal part 22a.Otherwise PSW part 23 is selected signal from removal part 22b.The signal of selecting outputs to low speed side circuit (22).
To describe now as the flow process signal on the rightabout, from the low speed side circuit (21) of terminal node equipment 2 to the signal of the low speed side circuit (92) of terminal node equipment 9.Be inserted into the bandwidth of operation among the loop network RN1 from the signal of the low speed side circuit (21) of terminal node equipment 2 adding part 21a, and be inserted into the protection bandwidth adding part 21b.Be inserted into removal part 12 branches of the signal of bandwidth of operation at host node equipment 1; And, be inserted into services selection device part (SS part) 64 via low speed side circuit (12) as the signal on the low speed side circuit (61) of the auxilliary node device 6 that constitutes loop network RN2.Be inserted into removal part 32 branches of the signal of protection bandwidth, and, be inserted into the protection bandwidth of loop network RN2 via low speed side circuit (32) as the signal on the low speed side circuit (71) of the auxilliary node device 7 that constitutes loop network RN2 at host node equipment 3.If on the downside channel of host node equipment 6 and host node equipment 1, do not have fault, then the SS part 64 of host node equipment 6 is selected signal from low speed side circuit (61).Otherwise, the signal that SS part 64 is selected from the protection bandwidth of secondary nodes 7.The signal of selecting is in removal part 92 branches of terminal node equipment 9, and outputs to low speed side circuit (92), as the signal of bandwidth of operation among the loop network RN2.
Fig. 3 is the device block diagram.To use this figure to describe as the for example general introduction of the time slot interchanger of SONET (Synchronous Optical Network)/SDH (synchronous digital classification)-self-reacting device.
Unit controls part 300 is provided with data from the external equipment receive channel such as service equipment, and will transfer of data be set to time slot interchanger 100W and 100P according to the channel of the time slot allocation of transmitting data.Unit controls part 300 also receives the transmission path warning from line interface part 201 grades, and alarm data is transferred to time slot interchanger 100W and 100P, as being used to handle time gas exchange is provided with data with channel control information.Here, the transmission path warning refers to be included in the information among the TOH (transmission expense), and TOH is the transmission path form corresponding to SONET/SDH.
Time gas exchange part 130 uses following processes to carry out the time gas exchange of transmission data.At first; Time gas exchange part 130 receives the transmission data from line interface part 201; Then based on the address that writes from address control memory part 120; The transmission data that receive are written in the memory (not shown) that provides in the time gas exchange part 130, and read the transmission data from this memory based on the address of reading from address control memory part 120.
Address control memory part 120 is provided with data based on the channel that comes self-channel that data processing section 110 is set, and generation will be notified writing the address and reading the address to time gas exchange part 130.Address control memory part 120 generates and is used to write the sequence address of address, and the random address that is used to read the address.Promptly; Time gas exchange part 130 writes the transmission data of reception based on said sequence address; And address control memory part 120 produces said random address; Be used for reading the time slot of the transmission data that write, so that the time slot of the transmission data that exchanges data writes is set according to channel based on corresponding address.
Channel is provided with data processing section 110 and from the channel that unit controls part 300 receives according to the time slot allocation of transmission data data is set, and channel is provided with data and shows the channel signal that constitutes the transmission data and distribute to which time slot.Channel is provided with data processing section 110 and also is used to handle time gas exchange is provided with data with channel alarm data from 300 receptions of unit controls part.Then, channel is provided with the time slot of data processing section 110 according to the transmission data that received by time gas exchange part 130, channel is set data are set.And according to alarm data, channel is provided with data processing section 110 and channel is provided with the channel that data switch to corresponding to the switching purpose of channel signal ground data are set.For example, attempt when breaking down owing to transmission path channel signal when working band switches to the protection bandwidth, channel is provided with data processing section 110 switches to channel signal the protection bandwidth from the time slot of bandwidth of operation time slot.
First execution mode
In this first execution mode; For example time slot interchanger (also being described to node device) has constituted the 2F-BLSR loop network; And the maximum of the transmission capacity of being handled by time slot interchanger is assumed that 160Gbps; Promptly; Time slot interchanger be assumed that the line speed holding to have 2.4Gbps up to 64 STS (synchronous driving signal)-48, and processing unit's (following its may also be referred to as CH (channel)) of being provided with as its channel of supposition STS-1 (this also can be described to 51.84Mbps or transmission capacity 50Mbps).
Fig. 4 shows the overview that illustrated channel among Fig. 3 is provided with the functional configuration of data processing section 110.The details of each function will be described later.
Fig. 5 shows the channel architecture that the channel that is produced by the unit controls part shown in Fig. 3 300 is provided with data and alarm data, and this channel is provided with data and alarm data and is notified data processing section 110 to channel is set.The unit of processing clock is 1/2 the 77.76MHz (this also is described to the 78M clock) that equals STS-3 (155.52Mbps).
As shown in Figure 5, signal uses two STS-48 that handle unit as, occupies 96 78M clock zones.Particularly, about each the bar road in these two circuits: circuit is input to the east side of node device and on the sense of the west side output of this node device, promptly at signal; The EW direction; And circuit is its opposition side (signal is input to the west side and from the sense of east side output, that is, WE direction); Channel 1 (CH1) is used as bandwidth of operation (WK) to each of channel 24 (CH24); And channel 25 is used as protection bandwidth (PT) to each of channel 48 (CH48), that is, 96 channels are handled unit as one altogether.The system of work (SYS) is got by this processing unit by 96 channels are formed.The formation of signal will be described with reference to Fig. 7 that hereinafter is described.
About this processing section; According to alarm data each channel is carried out the zone that channel is provided with the exchange of data as being used for; The same 96 big 78M clock zones with above-mentioned " SYS " zone are provided, have allowed in a frame (9720 78M clock zones), to handle the transmission capacity (two STS-48 with transmission capacity of 5Gbps equal 32SYS) of 160Gbps thus.
Fig. 6 shows the arrangement that channel signal format, each channel in the pie graph 5 is provided with data and alarm data.
Give each channel allocation 78M clock 4, and its 2 constitute signal areas.Data are set channel and alarm data comprises 16 parallel signals (0 to 15) and 8 parallel signals (0 to 7) respectively.
The channel that Fig. 7 shows each channel shown in Fig. 6 is provided with the signal content and the structure of data, that is, the channel that Fig. 7 illustrates each channel is provided with destination (switching purpose ground).
Through these 6 parallel signals (6) from the 0th to the 5th; Distinguish with the channel number (CH1 to CH48) of 50Mbps capacity as the STS-1 of unit; And through the 6th parallel signal (1), distinguish side number (side 1 and side 2), side number shows two STS-48 on EW and the WE direction.Through these 4 parallel signals (4) from the 7th to the 10th; Distinguished with the system number (SYS# 0 to SYS#15) of 5Gbps capacity (96 channel capacity) as 1 system; And through the 11st parallel signal (1), distinguishing transmission capacity is the unit ( 80G# 0 and 80G#1) of the 80Gbps of 16 systems.
Therefore, up to the 11st signal, just can distinguish the channel of the transmission capacity that constitutes 160Gbps.In addition, in order to distinguish the transmission capacity of 160Gbps, use 3 parallel signals (3) from the 12nd to the 14th.
And, use the 15th signal (1), be provided with and whether carry out the channel setting.
Fig. 8 shows the formation and the signal content of the alarm data of each channel shown in Fig. 6.
Through these 5 parallel signals (5), the alarm condition of each channel is set from the 0th to the 4th.Through these 3 parallel signals (3), the splicing state of each channel is set from the 5th to the 7th.
The channel that Fig. 9 shows among Fig. 4 is provided with the inner signal format of using of data processing section.
Each of Figure 10 and Figure 11 shows the sequential of signal that the storage area of data processing section is set about the channel in the pie graph 4, and represented writing sequential and reading sequential memory respectively.System number is described to SYS0 to SYS15 (symbol # omits at this).
Figure 12 respectively shows the form of the signal between each function that channel in pie graph 4 is provided with data processing section to Figure 15.
Figure 16 shows channel the form that channel that data processing section 110 notified to address control memory part 120 is provided with data is set.
In Fig. 4; Storage area 1101 receives 24 parallel signals of Fig. 5 to the signal format shown in Fig. 8, and channel self-adapting ground is stored about the channel corresponding to 3072 channels (96 channels * 16 * 2) of the transmission capacity of 160Gbps data and alarm data are set.Storage area 1101 is read the signal of the signal format shown in Fig. 9.
In Fig. 9, the processing unit that channel is provided with data is known as SYS, and it comprises 96 channels corresponding to two STS-48.Alternately read the group 80G# 0 from SYS# 0 to SYS# 15 and the group 80G# 1 from SYS# 0 to SYS# 15 in the frame the frame from storage area 1101.Handle unit to this; The same 96 big 78M clock zones with above-mentioned " SYS " zone are provided; Carry out the zone that channel is provided with the exchange processing of data as being used for based on the alarm data of each channel, allow in a frame (9720 78M clocks zones), to handle the transmission capacity (two STS-48 with transmission capacity of 5Gbps equal 32SYS) of 160Gbps thus.In each SYS, read so that multiplexing to the signal among the CH48 (protection bandwidth) to CH24 (bandwidth of operation) and CH25 corresponding to the side 1 of two STS-48 and signal and the CH1 in each side in the side 2.Here, the signal of each CH comprises 24 parallel signals, that is, 16 are used for parallel signal and 8 parallel signals that are used for alarm data that channel is provided with data.The content of these signals is identical with shown in Fig. 7 and Fig. 8 those.
In Fig. 4, from the signal of storage area 1101 to DTPSW parts 1102; Signal from DTPSW part 1102 to each XC part 1103 and DCPThr part 1104; Signal from each XC part 1103 and DCPThr part 1104 to SS parts 1105; And from SS part 1105 to storage area 1106 signal adopts the signal format shown in Fig. 9.
In Fig. 4; The alarm data that storage area 1111 will be 1101 that read from storage area, comprise in the signal Fig. 9 is written in the both sides memory that comprises in the storage area 1111 to each group 80G# 0 and 80#G1; Shown in the S1 among Figure 10; That is, storage area 1111 is written to the signal shown in Figure 12 in the both sides memory that comprises in the storage area 1111 to group 80G# 0 and 80#G1.In the memory of each group 80G# 0 of storage and 80#G1, alarm data writes 96 zones by time sequence mode with SYS position unit, and in 192 zones of twice that are these 96 zones, reads.Read output signal adopts the sequential shown in the S2 among Figure 10, and is transferred to the DTPSW control section 1112 shown in Fig. 4.
In Fig. 4, in the alarm data of the channel that constitutes DTP, when relevant warning was suggested, DTPSW control section 1112 was provided for the transmission data are switched to from active side the control signal of protection side.That is, under the situation of the signal shown in Figure 13, for each channel provides control bit, and when having selected bandwidth of operation, logic level is set to " 0 ", and when having selected the protection bandwidth, logic level is set to " 1 ".
In Fig. 4, storage area 1113 will be written in the both sides memory that comprises in the storage area 1113 by the signal (shown in Figure 13) that DTPSW control section 1112 is provided with.That is, be transferred to the sequential of signal (shown in Figure 13) employing of storage area 1113 by the signal shown in the S2 Figure 10 from DTPSW control section 1112.Through writing sequential (W) by shown in the S2 this, signal is written in the both sides memory that comprises in the storage area 1113.
Step S2 in Figure 10, storage area 1113 will be that the signal (control data) that unit writes among the Figure 13 in two 96 zones reads in 96 zones (as indicated by the S2 among Figure 10 " R ") with SYS.The signal of reading (control data) constitutes the sequential shown in the S3 among Figure 10, and is transferred to the DTPSW control section 1102 among Fig. 4.
In Fig. 4, to the signal of reading from storage area 1101 (Fig. 9), DTPSW part 1102 is based on the signal of being read by above-mentioned storage area 1113 (control data), and being unit with SYS makes a choice between the bandwidth of operation of each channel and protection bandwidth.
By DTPSW part 1102 is that the signal (signal of form shown in Figure 9) that unit selects between bandwidth of operation and protection bandwidth is transferred to XC part 1103 and DCPThr part 1104 with the channel.
Based on the alarm data that is written in the storage area 1114; XC control section 1115 is that unit produces signal (channel with content shown in Fig. 7 is provided with data) with the channel, this signal be used for SYS be unit be controlled at CH1 to the bandwidth of operation channel signal of CH24 and CH25 to the switching (channel setting) between the boundary belt wide channels signal of CH48.
S4 in Figure 11, storage area 1106 will be that channel that unit writes is provided with in 96 zones that data read into each SYS with SYS.
In Fig. 4, XC part 1103 is based on the signal (channel is provided with data) that writes in the storage area 1116, and the signal (Fig. 9) that comes from 1102 transmission of DTPSW part is carried out the channel setting.
Be transferred to SS part 1105 by the signal (being described as adding the side signal) of XC part 1103 outputs and the signal of being exported by DCPThr part 1104 (being described as Thr side signal), wherein these two types of signals all are the forms shown in Fig. 9.
Shown in the S6 of Figure 11, based on alarm data 1117 that read from storage area by SYS unit, that constitute the channel of DCP, SS control section 1118 produces the control signal that is used to select Thr side signal under the situation that relevant warning occurs.That is, under the situation of signal as shown in FIG. 15, the control bit of channel unit is provided, and when selecting to add the side signal, logic level is set to " 0 ", and when selecting Thr side signal, logic level is set to " 1 ".
In Fig. 4, to adding side signal and Thr side signal, SS part 1105 is that side signal or Thr side signal are selected to add for each channel by unit based on the signal of reading from above-mentioned storage area 1119 (control data) with SYS.
It is interpolation side signal or the Thr side signal (signal of the form shown in Fig. 9) that the unit is selected for each channel that storage area 1106 orders write with SYS; And after the channel of reading 3072 channels of the transmission capacity with 160Gbps in lump was provided with data, storage area 1106 was transferred to the address control memory part 120 shown in Fig. 3 through the signal format shown in Figure 16 with it.
As can the signal format from Figure 16 see; With the channel shown in Fig. 3 data division 110 different address control storage parts 120 are set in order above-mentioned signal to be transferred on functional block, 1 concurrent transmission of 78M clock signal in the forward position of index signal and in the forward position of signal part provides index signal anterior fixed pattern (pattern).
Timing sequence generating part 1107 is produced as writing of above-mentioned storage area and reads required clock signal, clock signal etc.
Through this execution mode; Use to realize redundantly structured DTP structure and DCP structure and and loop network between the time slot interchanger of interconnection in, based on alarm data the exchange that channel is provided with data is handled and can be realized as handling unit with the transmission capacity of two loop network circuits.Therefore; In the ring-type capacity of trunk is that 64 STS-48 (160Gbps capacity), channel setting unit are that number is set is that 3072 channels (under the situation of 96ch * 32=3072ch), can carry out through the SYS unit's (5Gbps capacity) with 96 channels and be that unit sequence repeats this processing and realizes for 32 times with SYS by the processing that the required channel of time gas exchange is provided with data for STS-1 (50Mbps capacity) and channel.Particularly; Storage area 1101 among Fig. 4 and 1106 each all need be corresponding to the memory span of transmission capacity 160Gbps, and in storage area 1111,1113,1114,1116,1117 and 1119 each can both realize above-mentioned processing through the memory span corresponding to transmission capacity 5Gbps.This makes that can reduce processing channel is provided with the required circuit scale of data (memory size particularly).
When channel is provided with the processing capacity and increases, should the number of repetition of the processing that the increase of processing capacity can be through increasing basic circuit was set and contained at channel, and need not increase quantity like the circuit of memory.
Second execution mode
In first embodiment, the maximum of the transmission capacity that has proposed to be handled by the single time slot interchanger is the situation of 160Gbps (that is the STS-48 that, has the line speed of 2.4Gbps is received nearly 64).
In a second embodiment, propose such situation, the maximum of the transmission capacity of wherein being handled by the single time slot interchanger is 480Gbps for example.
Figure 17 shows 480Gbps capacity processing capacity.Here, Reference numeral 111 expression inter-process parts, Reference numeral 112 expression scratchpad memory parts, Reference numeral 113 expression external memory storage INF parts, and Reference numeral 114 expression external memory storages.
Inter-process part 111 has the function that the channel of in first embodiment, describing is provided with data processing section 110, and carries out the processing that channel is provided with data with the capacity of 160Gbps.
External memory storage INF part 112 is to be used for the temporary transient memory channel of the capacity of 160Gbps memory of data being set, described in first execution mode, and constitute the memory that both sides dispose.
When carrying out capacity processing channel with 160Gbps data be set, external memory storage INF part 113 usefulness act on memory 114 externally and the scratchpad memory part 112 that disposes with both sides between the interface of swap data.
External memory storage 114 is provided with data with the capacity storage channel of 480Gbps.External memory storage 114 is the memories corresponding to the storage area among first embodiment 1101 and 1106.
Figure 18 illustrates 480Gbps capacity sequential.
Described in first execution mode; Owing to being provided with data, can be handled the channel of handling with the 160Gbps capacity by 1 frame, 1 frame ground; So via external memory storage INF part 113, write both sides scratchpad memory part 112 in an alternating manner from the required data of the bodge for 160Gbps of external memory storage 114.
The channel that inter-process part 111 reads out from a side of scratchpad memory part 112 is provided with data; And after having carried out channel required processing (contents processing in the first embodiment describe) is set, inter-process unit 111 writes result in one side of scratchpad memory part 112.Then, inter-process part 111 order is carried out the processing of each 160Gbps capacity, and in an alternating manner order is as a result write both sides scratchpad memory part 112.
External memory storage INF part 113 will be stored in above-mentioned channel in the scratchpad memory part 112 and data are set write external memory storage in proper order.
Through this execution mode; The loop wire capacity is that 192 STS-48 (480Gbps capacity), channel selected cell are that number is set is that 9216 channels (under the situation of 3072ch * 3=9216ch), handle and can handle and repeat this processing in proper order with the 160Gbps bodge and realize through carrying out with the 160Gbps bodge by the exchange that the required channel of time gas exchange is provided with data for STS-1 (50Mbps capacity) and channel therein.Therefore; Through constitute inter-process part, scratchpad memory, external memory storage INF part by ASIC; And through in response to the size of handling capacity external memory storage being set, being used for the scale (particularly memory size) that channel that ASIC constitutes is provided with the treatment circuit of data can be reduced.
When channel was provided with the increase of processing capacity, the increase that this channel is provided with the processing capacity can be received through the capacity of adjusting external memory storage and the number of iterations that increases the processing in the basic ASIC circuit, and need not to change the ASIC circuit.
Claims (5)
1. time slot interchanger, this time slot interchanger comprises:
Time Slot Switching Circuit is used to exchange the time slot of multiplexing transmission signals;
The address control memory circuit is used to generate write address that switching time slot uses and reads the address, and said write address and the said address of reading are informed to said Time Slot Switching Circuit; And
Channel is provided with data processing circuit, and the channel that is used to receive according to the time slot allocation of said multiplexing transmission signals is provided with data, and according to alarm data the channel that is received is provided with the channel that data switch to corresponding to the switching purpose ground of channel signal data are set,
Wherein, data be set generate said write address and the said address of reading based on channel that data processing circuit switches to is set by said channel,
Wherein, said channel is provided with data processing circuit and comprises:
The first memory circuit; Be used for according to the first preset transmission capacity; Storage is used to handle the alarm data that the said channel that distributes with the time series mode is provided with data; So that handle said channel according to the second preset transmission capacity data are set, said first memory circuit has the memory span corresponding to said first transmission capacity; And
The second memory circuit is used for storing said channel according to said second transmission capacity data and said alarm data is set, and this second memory circuit has the memory span corresponding to said second transmission capacity;
Wherein said alarm data is copied out and is stored in the said first memory circuit from said second memory circuit; Being stored in channel that the said alarm data in the said first memory circuit handled is provided with data and is stored in the said second memory circuit; Said first transmission capacity is the 1/n of said second transmission capacity, and n is an integer.
2. time slot interchanger as claimed in claim 1,
Wherein said first memory circuit is used to handle the data n time that said channel is provided with data according to said preset first transmission capacity storage, so that handle said channel according to the said second preset transmission capacity data is set.
3. time slot interchanger as claimed in claim 1,
Wherein said time slot interchanger is SONET-self-reacting device or SDH self-reacting device,
Wherein said first transmission capacity has the transmission capacity corresponding to two transmission lines of the STM-16 among OC-48 among the said SONET or the said SDH, and said second transmission capacity and said first transmission capacity 32 times the same big, and wherein said n is 32.
4. time slot interchanger as claimed in claim 1,
Wherein said time slot interchanger is SONET self-reacting device or SDH self-reacting device,
Be that unit is provided with data to said channel and handles wherein with the channel of 51.84Mbps.
5. time slot interchanger as claimed in claim 1,
Wherein said time slot interchanger is the device with 2F-BLSR system.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007-151935 | 2007-06-07 | ||
| JP2007151935 | 2007-06-07 | ||
| JP2007151935A JP4910893B2 (en) | 2007-06-07 | 2007-06-07 | Time slot replacement device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101321403A CN101321403A (en) | 2008-12-10 |
| CN101321403B true CN101321403B (en) | 2012-03-07 |
Family
ID=39596054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008101089303A Active CN101321403B (en) | 2007-06-07 | 2008-06-06 | Time slot interchanger |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8582597B2 (en) |
| JP (1) | JP4910893B2 (en) |
| CN (1) | CN101321403B (en) |
| GB (1) | GB2449962B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5861371B2 (en) | 2011-10-12 | 2016-02-16 | 富士通株式会社 | Line switching device |
| CN103023597B (en) * | 2012-12-27 | 2016-06-08 | 华为技术有限公司 | The method and apparatus of optical network data transmission |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4999832A (en) * | 1989-11-27 | 1991-03-12 | At&T Bell Laboratories | Broadband multirate switching architecture |
| CN1177246A (en) * | 1996-07-10 | 1998-03-25 | 富士通株式会社 | Cross connection system for time-division multiplexed signal |
| CN1296371A (en) * | 1999-11-11 | 2001-05-23 | 朗迅科技公司 | Space/time exchanger structure |
| US6330237B1 (en) * | 1998-03-20 | 2001-12-11 | Fujitsu Limited | Time slot assignment circuit |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US271045A (en) * | 1883-01-23 | Car-coupling | ||
| US5323390A (en) * | 1992-10-20 | 1994-06-21 | At&T Bell Laboratories | Multirate, sonet-ready, switching arrangement |
| US5883902A (en) * | 1996-12-04 | 1999-03-16 | Alcatel Usa Sourcing, L.P. | Time slot interchanger and digital communications terminal for ISDN D-channel assembly |
| JPH10208027A (en) | 1997-01-21 | 1998-08-07 | Fuji Xerox Co Ltd | Image processor, image processing method and image processing control program storage medium |
| US6628652B1 (en) * | 1998-09-18 | 2003-09-30 | Lucent Technologies Inc. | Flexible telecommunications switching network |
| JP3790097B2 (en) * | 2000-12-04 | 2006-06-28 | 富士通株式会社 | Station recognition method for ring network |
| JP2004112738A (en) | 2002-07-25 | 2004-04-08 | Fujitsu Ltd | Resolution conversion method and pixel data processing circuit for single-ccd color-image sensor |
| US6967948B2 (en) * | 2002-10-31 | 2005-11-22 | Ciena Corporation | Out-of-band signalling apparatus and method for an optical cross connect |
| JP4239668B2 (en) * | 2003-05-07 | 2009-03-18 | 日本電気株式会社 | Data memory control method |
| US7944876B2 (en) * | 2004-06-02 | 2011-05-17 | Integrated Device Technology, Inc | Time slot interchange switch with bit error rate testing |
-
2007
- 2007-06-07 JP JP2007151935A patent/JP4910893B2/en active Active
-
2008
- 2008-05-16 GB GB0808980.7A patent/GB2449962B/en active Active
- 2008-06-03 US US12/155,402 patent/US8582597B2/en active Active
- 2008-06-06 CN CN2008101089303A patent/CN101321403B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4999832A (en) * | 1989-11-27 | 1991-03-12 | At&T Bell Laboratories | Broadband multirate switching architecture |
| CN1177246A (en) * | 1996-07-10 | 1998-03-25 | 富士通株式会社 | Cross connection system for time-division multiplexed signal |
| US6330237B1 (en) * | 1998-03-20 | 2001-12-11 | Fujitsu Limited | Time slot assignment circuit |
| CN1296371A (en) * | 1999-11-11 | 2001-05-23 | 朗迅科技公司 | Space/time exchanger structure |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2449962B (en) | 2012-07-25 |
| JP4910893B2 (en) | 2012-04-04 |
| CN101321403A (en) | 2008-12-10 |
| JP2008306482A (en) | 2008-12-18 |
| GB0808980D0 (en) | 2008-06-25 |
| US8582597B2 (en) | 2013-11-12 |
| GB2449962A (en) | 2008-12-10 |
| US20080304508A1 (en) | 2008-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6614754B1 (en) | Bi-directional line switched ring network system | |
| US20060120360A1 (en) | Stackplane architecture | |
| JPH09307577A (en) | Communication network, communication network fault recovery system and optical communication network node | |
| US5119368A (en) | High-speed time-division switching system | |
| US20060209899A1 (en) | Switch for integrated telecommunication networks | |
| KR20130120498A (en) | Network node for an optical transport network | |
| KR100331606B1 (en) | ATM cell switch device and ATM exchange | |
| CN101321403B (en) | Time slot interchanger | |
| US7349411B2 (en) | Economically expansible switching network | |
| US7042913B2 (en) | Method and system for writing data to memory elements | |
| US6317429B1 (en) | Communication apparatus, network system using communication apparatus and control method used in network system | |
| US7075952B1 (en) | Multiplexing in a PDH telecommunications network | |
| CN101741681B (en) | Node apparatus | |
| US6393019B1 (en) | Matrix switch | |
| US7382723B2 (en) | Hitless switching system and transmission apparatus | |
| JP3429666B2 (en) | Time slot assignment circuit | |
| US7054324B1 (en) | Interface transmitter for communications among network elements | |
| KR100226540B1 (en) | Atm switch address generating circuit | |
| US7978736B2 (en) | Efficient provisioning of a VT/TU cross-connect | |
| US7184662B2 (en) | Switching network | |
| US8355632B2 (en) | Transmission apparatus | |
| JP2937666B2 (en) | Cross connect device | |
| JP3561853B2 (en) | Double ring network system | |
| JP3716840B2 (en) | Non-instantaneous switching system and transmission device | |
| JP3116574B2 (en) | Switch control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |