CN101312344B - Integration data receiving method and receiver - Google Patents
Integration data receiving method and receiver Download PDFInfo
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- CN101312344B CN101312344B CN200710052238A CN200710052238A CN101312344B CN 101312344 B CN101312344 B CN 101312344B CN 200710052238 A CN200710052238 A CN 200710052238A CN 200710052238 A CN200710052238 A CN 200710052238A CN 101312344 B CN101312344 B CN 101312344B
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Abstract
The invention discloses a data receiving method and a receiver, firstly in one clock signal response, N (N is a natural number) input differential pairs are integrated and amplified, in a first clock signal response, an electric level of at least one pair of differential signals is pre-charged to power supply voltage, in a second clock signal response, an integration result of at least one pair of differential signals is output, and then, in one clock signal response, at least one input differential pair is detected and amplified to output as a detected data. A receiver comprises an integration circuit and a detecting amplifying circuit, firstly a first stage integration circuit comprises an integration element, a capacitor, a discharge branch circuit MOS tube and a charge element MOS tube, secondly, a second stage detecting amplifying circuit comprises a detecting amplifying element and a latched output element to detect and amplify the first stage integration result, an input of the latched output element is connected with an output of the detecting amplifying element to latch and output detected amplified results.
Description
Technical field
The present invention relates to semiconductor device, more particularly, relate to a kind of integration data receiving method, and the data sink that adopts this method of reseptance, carry out integration with data-signal clock synchronization and detect the data that receive in order to that will receive.
Background technology
In the world, little swing difference signal is widely used in the interface circuit of High Speed System, in order to transmit high-speed data signal.There is multiple high-speed data method of reseptance to be suggested at present, most based on the reference voltage comparison principle, United States Patent (USP) 6160423 (US Patent 6160423) for example.
In above-mentioned patent documentation, a kind of method of utilizing single ended voltage and time reference synchronized oscillation source SSVTR and its complementary signal SSVTR to receive single-ended data input signal has been described.
The data sink that is proposed in the above-mentioned patent documentation receives single-ended input data signal SN simultaneously by the positive input terminal of two comparators
XThe negative input end of above-mentioned two comparators is received respectively on the SSVTR and reverse signal SSVTR thereof with time reference synchronized oscillation, and the output result of two comparators is selected according to received data-signal of previous cycle by selector switch, as detected input data signal.
SSVTR, SSVTR and SN
XPass between three signals is: when initial, and single-ended data input signal SN
XWhen logic high, equate, be converted to logic low with SSVTR then, and remain on low level, thereby equate with SSVTR with SSVTR; And then be converted to high level with SSVTR.Keep high level again, thereby equate with SSVTR.
From above-mentioned SSVTR, SSVTR and SN
XRelationship description between three signals as can be known, if detected input data signal is different with detected input data signal in last one-period in present clock period, then selector switch will be kept the output result of the same comparator of selection as output signal; If detected input data signal is identical with detected input data signal in last one-period in the present clock period, then selector switch will select the output result of another comparator as output signal.Could guarantee the stable of circuit like this.
The data receive method that above-mentioned patent documentation proposed need not to use and receives the needed high impedance vref signal of traditional little amplitude of oscillation single-ended signal, and more necessary voltage swing is reduced, thereby reduces power consumption.
Yet,, the high-frequency noise on the input signal is suppressed indifferent because the data receive method that above-mentioned patent documentation proposed remains device principle based on the comparison; Simultaneously, because the overturn point of inverter can change with circuit technology, operating voltage and variation of temperature, so the data that receive can not guarantee accurately to be detected.In addition, if the incoming signal level of comparator is lower, then also be difficult to accurately survey the data that received.
Summary of the invention
The objective of the invention is to be to provide a kind of integration data receiving method, based on the integration sampling principle, compare with the data receive method of the traditional principle of device based on the comparison, its major advantage is: method is simple, receive data accuracy height, need not to provide reference voltage, can effectively overcome high-frequency noise on the input signal and disturb, therefore be more suitable for being used to receive high-speed data signal receiving the influence of data precision.
Another object of the present invention is to be to provide a kind of integration data receiver, and it is simple in structure, and is easy and simple to handle, receives data accuracy height.Compare with the data receive method of the traditional principle of device based on the comparison, its major advantage is: adopt the integration sampling technology, need not to provide reference voltage, can effectively suppress high-frequency noise on the input signal and disturb the influence that data is received precision, be more suitable for being used to receive high-speed data signal; Can come compensating circuit technology, supply voltage and variation of temperature by the CONTROL signal of adjusting in the receiver, and guarantee that by adjusting capacitance discharges speed input signal can be hunted down in a clock cycle; Integral accuracy only depends on the electric capacity of a pair of appropriateness coupling in the circuit, therefore to the dependence of circuit technology a little less than.
In order to achieve the above object, the present invention adopts following technical measures:
A kind of data receive method adopts the integration sampling technology, the steps include:
(a) in a clock signal response, integration also amplifies N to (N is a natural number) input difference (or single-ended) signal, and exports the integral result of at least one pair of differential signal in a clock signal response.
(b) in a clock signal response, detect and amplify the integral result of at least one pair of input difference (or single-ended) signal, and it is latched output as detected data value.
More than in two steps, first step has guaranteed that the difference of input signal is integrated at the appointed time, and with integral result output, has filtered the interference of input high-frequency noise; Second step guaranteed the detected at the appointed time amplification of integral result and latched output, makes receiver can reliably export detected data.
A kind of data sink of realizing described integration data receiving method, its structural relation is, comprises:
(a) first order integrating circuit comprises integral element, charge member and arresting element, and control signal corresponding, in order to receive N to difference (or single-ended) data-signal of (N is a natural number) input and with its difference integration;
(b) amplifying circuit is detected in the second level, comprises detecting amplifier element and latching output element two parts.The input that detects amplifier element is connected in the output of described first order integrating circuit, in order to detect the integral result that amplifies the first order; The input of latching output element is connected in the output that detects amplifier element, latchs output in order to will detect the amplification result.
According to the present invention, a kind of data sink that is applicable to the High-speed I interface can be provided, to compare with traditional data sink, its major advantage is:
(a) simple in structure, easy and simple to handle, receive data accuracy height;
(b) adopt the integration sampling technology, need not to provide reference voltage, can suppress effectively that high-frequency noise disturbs the influence that data is received precision on the input signal;
(c) can come compensating circuit technology, supply voltage and variation of temperature by the CONTROL signal of adjusting in the circuit, and guarantee that by adjusting capacitance discharges speed input signal can be hunted down in a clock cycle;
(d) integral accuracy only depends on the electric capacity of a pair of appropriateness coupling in the circuit, therefore to the dependence of circuit technology a little less than.
Description of drawings
Fig. 1 is the structural representation of integration data receiver among the present invention;
Fig. 2 is the circuit diagram of the embodiment of integrating circuit among the present invention;
Fig. 3 is for detecting the circuit diagram of the embodiment of amplifying circuit among the present invention;
Fig. 4 is the schematic diagram of integration data receiving method among the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in further detail:
Fig. 4 is the schematic diagram of integration data receiving method among the present invention.As can be known from Fig. 4, this method of reseptance is realized by two steps:
A. in a clock signal response, integration also amplifies N to (N is a natural number) input difference (or single-ended) signal, and exports the integral result of at least one pair of differential signal in a clock signal response.More particularly, be that the phase I in a clock signal period is charged to supply voltage in advance with the level of at least one pair of differential signal, the second stage in a clock signal period is carried out integration with the difference of input data signal, and integral result is exported.
B. in a clock signal response, detect and amplify the integral result of at least one pair of input difference (or single-ended) signal, and it is latched output as detected data value.More particularly, be that the second stage in a clock signal period is amplified the integral result detection of at least one pair of input difference (or single-ended) signal, and the phase I in a clock signal period is latched output with amplifying signal.
More than in two steps, first step has guaranteed that the difference of input signal is integrated at the appointed time, and with integral result output, has filtered the interference of input high-frequency noise; Second step guaranteed the detected at the appointed time amplification of integral result and latched output, makes receiver can reliably export detected data.
Fig. 1 is the structural representation of integration data receiver of the present invention.As can be known from Fig. 1, integration data receiver of the present invention comprises integrating circuit 11 and detects 12 two parts of amplifying circuit.Wherein, integrating circuit 11 receives N to (N is a natural number) differential data input signal from input terminal DI and DI, and under the effect of clock sync signal STROBE, the difference of input signal is carried out integration, in addition, integrating circuit 11 is also by CONTROL signal controlling integration amount, in order to different circuit technologies, operating voltage and variation of temperature are compensated; Detect amplifying circuit 12 under the effect of clock sync signal STROBE, export to lead-out terminal DO and DO from described integrating circuit 11 reception integrated signals and amplification, in order to the N that receives integrating circuit 11 outputs integral result, with its amplification and latch output to (N is a natural number) differential signal.
Fig. 2 is the circuit diagram of the embodiment of integrating circuit 11 among the present invention.As can be known from Fig. 2, integrating circuit 11 is made up of integral element 21, charge member 22 and arresting element 23.Wherein, the structural relation of integral element 21 is: an end of an end of first capacitor C 1 and second capacitor C 2 is connected all on supply voltage VDD, and the other end of first capacitor C 1 is connected on the node 201, and the other end of second capacitor C 2 is connected on the node 202; The structural relation of charge member 22 is: the source end of a P channel type MOS transistor MP1 and the 2nd P channel type MOS transistor MP2 all is connected on the supply voltage VDD, the drain terminal of the one P channel type MOS transistor MP1 is connected on the node 201, the drain terminal of the 2nd P channel type MOS transistor MP2 is connected on the node 202, the source of the 3rd P channel type MOS transistor MP3 is leaked two ends and is connected on node 201 and the node 202, first, the two and the 3rd P channel type MOS transistor MP1, the grid end of MP2 and MP3 is connected on the output of inverter 24, and the input of inverter is connected on the input terminal STROBE; The structural relation of arresting element 23 is: the source end of a N channel type MOS transistor MN1 and the 2nd N channel type MOS transistor MN2 all is connected on the node 203, the drain terminal of the one N channel type MOS transistor MN1 is connected on the node 201, the drain terminal of the 2nd N channel type MOS transistor MN2 is connected on the node 202, the grid end of the one N channel type MOS transistor MN1 is connected on the input terminal DATA, the grid end of the 2nd N channel type MOS transistor MN2 is connected on the input terminal DATAB, the drain terminal of the 3rd to the 6th N channel type MOS transistor MN3～MN6 is connected on the node 203, the source end of the 3rd to the 6th N channel type MOS transistor MN3～MN6 is connected on the drain terminal of the 7th to the tenth N channel type MOS transistor MN7～MN10, the source end of the 7th to the tenth N channel type MOS transistor MN7～MN10 is connected on the ground node VSS, the grid end of the 3rd to the 6th N channel type MOS transistor MN3～MN6 is connected on four control bus CONTROL, and the grid end of the 7th to the tenth N channel type MOS transistor MN7～MN10 is connected on the output of inverter 24.Need to prove that in this novel practical, the figure place of control bus CONTROL depends on the branch road number in the arresting element 23 and is not limited to 4.
The action of above-mentioned integrating circuit 11 then, is described.The STROBE signal is and the input data signal clock signal synchronous.When the STROBE signal is the logical one level, the equal conducting of the 1st to the 3rd P channel type MOS transistor MP1～MP3, this moment, node 201 and 202 nodes were precharged to supply voltage VDD, also were that the level on lead-out terminal OUT and the OUTB is supply voltage VDD; When the STROBE signal becomes the logical zero level, whether node 201 and 202 discharge will depend on the level on input terminal DATA and the DATAB.If DATA is a logical one and DATAB is a logical zero, then node 201 will discharge; Otherwise if DATA is a logical zero and DATAB is a logical one, then node 202 will discharge.Like this, the voltage difference between input terminal DATA and the DATAB will be integrated, and be converted to the voltage difference between node 201 and the node 202, and by lead-out terminal OUTB and OUT the voltage difference of this integration be exported.When the STROBE signal became again to logical one again, integration finished, and node 201 and 202 is precharged to supply voltage VDD again, at this moment detects amplifying circuit and starts working.The effect of arresting element 21 is: open what of discharge paths by the signal controlling on the sub-CONTROL of bus input end, thereby the size of the discharging current of first capacitor C 1 and second capacitor C 2 in the control integral element, like this, can compensate different circuit technologies, supply voltage and influence of temperature variation by adjusting being provided with of control bus CONTROL.
Fig. 3 is the circuit diagram that detects the embodiment of amplifying circuit 12 among the present invention.As can be known from Fig. 3, detect amplifying circuit 12 by detecting amplifier element 31 and latching output element 32 and form.Wherein, the structural relation that detects amplifier element 31 is: the source end of first to fourth P channel type MOS transistor MP1～MP4 is connected on the supply voltage VDD, first, three P channel type MOS transistor MP1, the grid end of the drain terminal of MP3 and the 2nd P channel type MOS transistor MP2 is connected on the node 310, second, four P channel type MOS transistor MP2, the grid end of the drain terminal of MP4 and a P channel type MOS transistor MP1 is connected on the node 311, the drain terminal of the 5th P channel type MOS transistor MP5 and source end are connected on respectively on node 310 and the node 311, the drain terminal of the grid end of the one N channel type MOS transistor MN1 and the 2nd N channel type MOS transistor MN2 is connected on the node 311, the grid end of the drain terminal of the one N channel type MOS transistor MN1 and the 2nd N channel type MOS transistor MN2 is connected on the node 310, the drain terminal of the source end of the one N channel type MOS transistor MN1 and the 3rd N channel type MOS transistor MN3 is connected on the node 312, the drain terminal of the source end of the 2nd N channel type MOS transistor MN2 and the 4th N channel type MOS transistor MN4 is connected on the node 313, the 3rd, four N channel type MOS transistor MN3, the drain terminal of the source end of MN4 and the 5th N channel type MOS transistor MN5 is connected on the node 314, the source end of the 5th N channel type MOS transistor MN5 is connected on the ground node VSS, and the grid end of the 3rd to the 5th P channel type MOS transistor MP3～MP5 and the 5th N channel type MOS transistor MN5 is connected on the input terminal STROBE; The grid end of the 3rd N channel type MOS transistor MN3 is connected on the input terminal DATA, and the grid end of the 4th N channel type MOS transistor MN4 is connected on the input terminal DATAB.The structural relation that latchs output element 32 is: the source end of the 6th to nine P channel type MOS transistor MP6～MP9 is connected on the supply voltage VDD, the 6th, the grid end of the drain terminal of eight P channel type MOS transistor MP6 and MP8 and the 9th P channel type MOS transistor MP9 is connected on the node 320, the 7th, the grid end of the drain terminal of nine P channel type MOS transistor MP7 and MP9 and the 8th P channel type MOS transistor MP8 is connected on the node 321, the 6th, eight N channel type MOS transistor MN6, the source end of the drain terminal of MN8 and the 9th N channel type MOS transistor MN9 is connected on the node 320, the 7th, nine N channel type MOS transistor MN7, the grid end of the drain terminal of MN9 and the 8th N channel type MOS transistor MN8 is connected on the node 321, the grid end of the 6th P channel type MOS transistor MP6 is connected on the node 311, the grid end of the 7th P channel type MOS transistor MP7 is connected on the node 310, the input of inverter INV1 is connected on the node 310 and output is connected to the grid end of the 6th N channel type MOS transistor MN6, and the input of inverter INV2 is connected on the node 311 and output is connected the grid end of the 7th N channel type MOS transistor MN7; Node 320 is connected on the lead-out terminal OUTB, and node 321 is connected on the lead-out terminal OUT.
The action of above-mentioned detection amplifying circuit 12 then, is described.Signal on the input terminal STROBE is for detecting the enable signal of amplifier element 31.When the STROBE signal is the logical zero level, the the 3rd to five P channel type MOS transistor MP3～MP5 conducting and the 5th N channel type MOS transistor MN5 ends, make that the data input DATA and the DATAB that detect amplifying circuit 12 are invalid, this moment, the level of node 310 and node 311 was precharged to supply voltage VDD, make the 6th, seven P channel type MOS transistor MP6, MP7 and the 6th, seven N channel type MOS transistor MN6, MN7 ends, node 320 and 321 level cross-couplings be connected the 8th, nine P channel type MOS transistor MP8, MP9 and the 8th, nine N channel type MOS transistor MN8, the positive feedback effect of MN9 keeps latch mode down, and output OUT and OUTB keep the data-signal in previous cycle; When the STROBE signal becomes the logical one level by the logical zero level, third and fourth P channel type MOS transistor MP3, MP4 end and the 5th N channel type MOS transistor MN5 conducting, detect amplifier element 31 and begin effect, the integral result (being the difference between DATA and the DATAB) of sampling integrating circuit 11 in the time of an inverter delay, difference is exaggerated at node 310 and 311 places, and by output latch element 32 result amplified is converted to the level of node 320 and 321 and passes through lead-out terminal OUT and OUTB dateout.
From the above-mentioned course of work as can be known, at the clock signal STROBE with data sync is in the time of logical zero level, data sink carries out integration with the differential signal on input terminal DI and the DI, and jump on the STROBE signal along the time integral result sampled and amplifies output.Owing to adopted the integration sampling technology, will effectively suppress the interference of input signal high-frequency noise.Owing in arresting element 21, introduced control signal corresponding CONTROL, can regulate integral process, therefore can when circuit technology, operating voltage and variations in temperature, make certain compensation, improved the robustness of design.
Claims (2)
1. an integration data receiving method the steps include:
A. in a clock signal response, integration also amplifies N to input difference/or single-ended signal, wherein N is natural number and the integral result of exporting at least one pair of differential signal in a clock signal response, be phase I in a clock signal period level of at least one pair of differential signal to be charged to supply voltage in advance, second stage in a clock signal period is carried out integration with the difference of input data signal, and integral result is exported;
B. in a clock signal response, detect and amplify at least one pair of input difference/or the integral result of single-ended signal, and it is latched output as detected data value, be in a clock signal period second stage with at least one pair of input difference/or the integral result of single-ended signal detect and amplify, and the phase I in a clock signal period is latched output with amplifying signal.
2. integration data receiver, it comprises that the first order integrating circuit (11) and the second level detects amplifying circuit (12) two parts, it is characterized in that:
A. first order integrating circuit (11) comprises integral element (21), charge member (22) and arresting element (23), and control signal corresponding, in order to receive N to the difference of input/or single-ended data-signal and with its difference integration; Wherein N is a natural number, the structural relation of integral element (21) is: an end of an end of first capacitor C 1 and second capacitor C 2 is connected all on supply voltage VDD, the other end of first capacitor C 1 is connected on the node 201, and the other end of second capacitor C 2 is connected on the node 202; The structural relation of charge member (22) is: the source end of a P channel type MOS transistor MP1 and the 2nd P channel type MOS transistor MP2 all is connected on the supply voltage VDD, the drain terminal of the one P channel type MOS transistor MP1 is connected on the node 201, the drain terminal of the 2nd P channel type MOS transistor MP2 is connected on the node 202, the source of the 3rd P channel type MOS transistor MP3 is leaked two ends and is connected on node 201 and the node 202, first, the two and the 3rd P channel type MOS transistor MP1, the grid end of MP2 and MP3 is connected on the output of inverter 24, and the input of inverter (24) is connected on the input terminal STROBE; The structural relation of arresting element (23) is: the source end of a N channel type MOS transistor MN1 and the 2nd N channel type MOS transistor MN2 all is connected on the node 203, the drain terminal of the one N channel type MOS transistor MN1 is connected on the node 201, the drain terminal of the 2nd N channel type MOS transistor MN2 is connected on the node 202, the grid end of the one N channel type MOS transistor MN1 is connected on the input terminal DATA, the grid end of the 2nd N channel type MOS transistor MN2 is connected on the input terminal DATAB, the drain terminal of the 3rd to the 6th N channel type MOS transistor MN3～MN6 is connected on the node 203, the source end of the 3rd to the 6th N channel type MOS transistor MN3～MN6 is connected on the drain terminal of the 7th to the tenth N channel type MOS transistor MN7～MN10, the source end of the 7th to the tenth N channel type MOS transistor MN7～MN10 is connected on the ground node VSS, the grid end of the 3rd to the 6th N channel type MOS transistor MN3～MN6 is connected on four control bus CONTROL, and the grid end of the 7th to the tenth N channel type MOS transistor MN7～MN10 is connected on the output of inverter (24);
B. amplifying circuit (12) is detected in the second level, comprise and detect amplifier element (31) and latch output element (32) two parts, the input that detects amplifier element (31) is connected in the output of described first order integrating circuit (11), in order to detect the integral result that amplifies the first order; The input of latching output element (32) is connected in the output that detects amplifier element (31), latchs output in order to will detect the amplification result; Wherein, the structural relation that detects amplifier element (31) is: the source end of first to fourth P channel type MOS transistor MP1～MP4 is connected on the supply voltage VDD, first, three P channel type MOS transistor MP1, the grid end of the drain terminal of MP3 and the 2nd P channel type MOS transistor MP2 is connected on the node 310, second, four P channel type MOS transistor MP2, the grid end of the drain terminal of MP4 and a P channel type MOS transistor MP1 is connected on the node 311, the drain terminal of the 5th P channel type MOS transistor MP5 and source end are connected on respectively on node 310 and the node 311, the drain terminal of the grid end of the one N channel type MOS transistor MN1 and the 2nd N channel type MOS transistor MN2 is connected on the node 311, the grid end of the drain terminal of the one N channel type MOS transistor MN1 and the 2nd N channel type MOS transistor MN2 is connected on the node 310, the drain terminal of the source end of the one N channel type MOS transistor MN1 and the 3rd N channel type MOS transistor MN3 is connected on the node 312, the drain terminal of the source end of the 2nd N channel type MOS transistor MN2 and the 4th N channel type MOS transistor MN4 is connected on the node 313, the 3rd, four N channel type MOS transistor MN3, the drain terminal of the source end of MN4 and the 5th N channel type MOS transistor MN5 is connected on the node 314, the source end of the 5th N channel type MOS transistor MN5 is connected on the ground node VSS, and the grid end of the 3rd to the 5th P channel type MOS transistor MP3～MP5 and the 5th N channel type MOS transistor MN5 is connected on the input terminal STROBE; The grid end of the 3rd N channel type MOS transistor MN3 is connected on the input terminal DATA, the grid end of the 4th N channel type MOS transistor MN4 is connected on the input terminal DATAB, the structural relation that latchs output element (32) is: the source end of the 6th to nine P channel type MOS transistor MP6～MP9 is connected on the supply voltage VDD, the 6th, the grid end of the drain terminal of eight P channel type MOS transistor MP6 and MP8 and the 9th P channel type MOS transistor MP9 is connected on the node 320, the 7th, the grid end of the drain terminal of nine P channel type MOS transistor MP7 and MP9 and the 8th P channel type MOS transistor MP8 is connected on the node 321, the 6th, eight N channel type MOS transistor MN6, the source end of the drain terminal of MN8 and the 9th N channel type MOS transistor MN9 is connected on the node 320, the 7th, nine N channel type MOS transistor MN7, the grid end of the drain terminal of MN9 and the 8th N channel type MOS transistor MN8 is connected on the node 321, the grid end of the 6th P channel type MOS transistor MP6 is connected on the node 311, the grid end of the 7th P channel type MOS transistor MP7 is connected on the node 310, the input of inverter INV1 is connected on the node 310 and output is connected to the grid end of the 6th N channel type MOS transistor MN6, and the input of inverter INV2 is connected on the node 311 and output is connected the grid end of the 7th N channel type MOS transistor MN7; Node 320 is connected on the lead-out terminal OUTB, and node 321 is connected on the lead-out terminal OUT.
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| DE102017110976B8 (en) * | 2017-05-19 | 2018-12-06 | Infineon Technologies Austria Ag | Self-oscillating multi-ramp converter and method for converting a capacitance into a digital signal |
| KR102599059B1 (en) * | 2018-10-11 | 2023-11-08 | 삼성디스플레이 주식회사 | Transition detector and clock data recovery unit including the same |
| TWI674754B (en) * | 2018-12-28 | 2019-10-11 | 新唐科技股份有限公司 | Data retention circuit |
| CN115617584A (en) * | 2021-07-16 | 2023-01-17 | 长鑫存储技术有限公司 | Receiver, memory and test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2197778Y (en) * | 1994-05-09 | 1995-05-17 | 华东光电集成器件研究所 | interface power supply of exchanging machine |
| CN2395476Y (en) * | 1999-06-26 | 2000-09-06 | 深圳市中兴通讯股份有限公司 | Feeding unit for user interface of program control exchanger |
| CN2627504Y (en) * | 2003-06-26 | 2004-07-21 | 上海雷磁新泾仪器有限责任公司 | Double-display potentiostat |
| CN201113970Y (en) * | 2007-05-24 | 2008-09-10 | 武汉芯动科技有限公司 | Integral data receiver |
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2007
- 2007-05-24 CN CN200710052238A patent/CN101312344B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2197778Y (en) * | 1994-05-09 | 1995-05-17 | 华东光电集成器件研究所 | interface power supply of exchanging machine |
| CN2395476Y (en) * | 1999-06-26 | 2000-09-06 | 深圳市中兴通讯股份有限公司 | Feeding unit for user interface of program control exchanger |
| CN2627504Y (en) * | 2003-06-26 | 2004-07-21 | 上海雷磁新泾仪器有限责任公司 | Double-display potentiostat |
| CN201113970Y (en) * | 2007-05-24 | 2008-09-10 | 武汉芯动科技有限公司 | Integral data receiver |
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