CN101308705A - Shift register and shift registering apparatus - Google Patents
Shift register and shift registering apparatus Download PDFInfo
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- CN101308705A CN101308705A CNA2007101063328A CN200710106332A CN101308705A CN 101308705 A CN101308705 A CN 101308705A CN A2007101063328 A CNA2007101063328 A CN A2007101063328A CN 200710106332 A CN200710106332 A CN 200710106332A CN 101308705 A CN101308705 A CN 101308705A
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Abstract
The invention discloses a shift register and shift registering devices thereof. The shift register comprises a plurality of shift registering devices, each of which comprises a pre-charge circuit, a pull-up circuit and a pull-down circuit. The pre-charge circuit is used to sample input signals according to a first time-pulse signal and a second time-pulse signal to respectively produce a first charge signal and a second charge signal. The pull-up circuit is coupled with the pre-charge circuit to receive a third time-pulse signal and the first charge signal and outputs output signals. The pull-down circuit is coupled with the pre-charge circuit and the pull-up circuit to receive the forth time-pulse signal and the second charge signal and determines whether to couple the output signals to the common electric potential or not. The shift register can prevent the deterioration of the amorphous silicon film of an amorphous silicon film transistor due to long-time voltage bias at the grid of the amorphous silicon film transistor, improve the reliability of the amorphous silicon film transistor, and further strengthen the stability of the whole circuit.
Description
Technical field
The invention relates to a kind of shift registor and shift register device thereof, and particularly be subjected to bias voltage for a long time relevant for a kind of grid of amorphous silicon film transistor of avoiding, and the shift registor and the shift register device thereof that cause output voltage to charge fully.
Background technology
Under the fixed situation of panel processing procedure, want directly on glass plate, to do circuit, just must use amorphous silicon film transistor (amorphous silicon thin film transistor is called for short a-Si TFT).Because in amorphous silicon film transistor, the critical voltage of P type amorphous silicon film transistor than the critical voltage of N type amorphous silicon film transistor come big, cause on ease of use, not having that N type amorphous silicon film transistor comes is good, therefore generally be made in circuit on the glass plate also based on full N type amorphous silicon film transistor circuit.
The phase inverter (inverter) of full N type amorphous silicon film transistor is the circuit structure that often is made on the glass plate, as shown in Figure 1.Fig. 1 is the circuit diagram of existing full N type amorphous silicon film transistor phase inverter.Please refer to Fig. 1.Circuit shown in Figure 1 comprises transistor 101 and 102, and VDD and GND are expressed as supply voltage and ground voltage respectively, and Vin and Vo then are expressed as input signal and output signal respectively.
As seen from Figure 1, the grid of transistor 101 directly is coupled to supply voltage VDD.But this kind bias voltage mode has utmost point adverse influence for inverter circuit, reason is that the grid of amorphous silicon film transistor is if be subjected to Dc bias for a long time, will cause the deterioration of amorphous silicon membrane and many defectives occur, and then (threshold voltage Vt) becomes very big to cause the critical voltage of amorphous silicon film transistor.Therefore, in sort circuit structure shown in Figure 1, because after work a period of time, the drift that will make progress of the critical voltage of transistor 101, make the voltage of output signal Vo can't charge fully, the inverter circuit that therefore has this structure can't work long hours.
With present technology, amorphous silicon film transistor has been used to make the shift register device on the glass plate.But in the many relevant patent formerly, avoided inverter structure as shown in Figure 1 though some patent utilization is arranged cleverly, but still do not improved the critical voltage drift problem that amorphous silicon film transistor is produced by long-time bias voltage.United States Patent (USP) US7038653 number with all be wherein an example for US5222082 number.Circuit shown in Figure 2 is exactly the circuit diagram of the shift register device that disclosed for US7038653 number of United States Patent (USP).As seen from Figure 2, the inverter structure that in empty frame 174, is presented, its transistor 201 still continues to be subjected to the bias voltage of VON, so that the problem of critical voltage drift also still can take place transistor 201, causes this shift register device to use for a long time.
Circuit shown in Figure 3 is exactly the circuit diagram of the shift register device that disclosed for US5222082 number of United States Patent (USP).In Fig. 3, though can't see a similar circuit structure shown in Figure 1, because this shift register device is in when work, the electric charge that its node P2 can exist some to discharge causes the transistor 301 can biased one section long time.Therefore, this shift register device is after process is worked for a long time, and the critical voltage of transistor 301 just significantly rises, and makes the voltage of output terminal OUTPUT to charge fully, causes this shift register device also can't use for a long time.
In order to solve the critical voltage shift phenomenon that amorphous silicon film transistor causes too for a long time because of bias voltage, each manufacturer takes a lot of trouble to do one's utmost invariably, by hook want to improve above-mentioned this defective, yet even to this day, do not occur also but that any effective solution was arranged.
Summary of the invention
Purpose of the present invention just provides a kind of shift registor and shift register device thereof, it can avoid the grid of amorphous silicon film transistor to be subjected to bias voltage for a long time and to cause the amorphous silicon membrane deterioration, promote the fiduciary level of amorphous silicon film transistor, and then increase the degree of stability of integrated circuit.
A further object of the present invention provides a kind of shift registor and shift register device thereof, and it can avoid amorphous silicon film transistor to produce critical voltage drift phenomenon, makes output voltage to charge fully.
Another purpose of the present invention provides a kind of shift registor and shift register device thereof, and it can use for a long time.
Based on above-mentioned purpose, the present invention proposes a kind of shift register device.This shift register device comprises pre-charge circuit, pull-up circuit and pull-down circuit.Pre-charge circuit is in order to respectively according to first clock signal and second clock signal input signal of taking a sample, to produce first charging signals and second charging signals respectively.Pull-up circuit couples pre-charge circuit, in order to receive the 3rd clock signal and first charging signals, output signal output according to this.Pull-down circuit couples pre-charge circuit and pull-up circuit, and in order to receive the 4th clock signal and second charging signals, whether decision according to this is coupled to common electric potential with output signal.Wherein input signal, first clock signal, the activation between the first phase of second clock signal, the 3rd clock signal be in second phase activation, the activation between the third phase of the 4th clock signal, and the second phase between the first phase after, between the third phase after the second phase.
Based on above-mentioned purpose, the present invention proposes a kind of shift registor, and it comprises first shift register device and second shift register device.The first shift register device receiving inputted signal, and according to first clock signal, second clock signal, the 3rd clock signal and the 4th clock signal and the displacement input signal, to produce first output signal.Second shift register device receives first output signal, and according to first clock signal, second clock signal, the 5th clock signal and the 6th clock signal and displacement first output signal, to produce second output signal.
According to shift register device of the present invention, above-mentioned pre-charge circuit comprises first switch, second switch, first energy storage device and second energy storage device.First switch has first end, second end and control end.First termination of this first switch is received input signal, and the control end of first switch receives first clock signal, determines whether conducting according to this.First energy storage device has first end and second end.First end of this first energy storage device couples second end of first switch, and in order to exporting the first above-mentioned charging signals, and second end of first energy storage device couples common electric potential.
Second switch has first end, second end and control end.First termination of this second switch is received input signal, and the control end of second switch receives second clock signal, determines whether conducting according to this.Second energy storage device has first end and second end.First end of this second energy storage device couples second end of second switch, and in order to exporting the second above-mentioned charging signals, and second end of second energy storage device couples common electric potential.In this embodiment, first switch and second switch are all realized with N type amorphous silicon film transistor.
According to shift register device of the present invention, above-mentioned pull-up circuit comprises the 3rd switch and the 4th switch.The 3rd switch has first end, second end and control end.First end of this 3rd switch couples pre-charge circuit, and in order to receiving first charging signals, and the control end of the 3rd switch receives the 3rd clock signal, determines whether conducting according to this.The 4th switch has first end, second end and control end.First termination of this 4th switch is received the 3rd clock signal, and the control end of the 4th switch couples second end of the 3rd switch, and the 4th switch is according to signal that its control end received and determine whether export the 3rd clock signal, to form above-mentioned output signal.In this embodiment, the 3rd switch and the 4th switch are all realized with N type amorphous silicon film transistor.
According to shift register device of the present invention, above-mentioned pull-down circuit comprises the 5th switch and the 6th switch.The 5th switch has first end, second end and control end.First end of this 5th switch couples pre-charge circuit, and in order to receiving second charging signals, and the control end of the 5th switch receives the 4th clock signal, determines whether conducting according to this.The 6th switch has first end, second end and control end.First end of this 6th switch couples second end of the 4th switch, second end of the 6th switch couples common electric potential, and the control end of the 6th switch couples second end of the 5th switch, and the 6th switch is according to signal that its control end received and determine whether conducting, so that above-mentioned output signal is coupled to common electric potential.
According to described shift register device of the present invention, it also can comprise first buffer circuit.This first buffer circuit couples a shared node of pull-up circuit and pull-down circuit, and this common points is in order to output signal output, and first buffer circuit is in order to the driving force of buffering and enhancing output signal.
The first above-mentioned buffer circuit comprises first switch, second switch and energy storage device.First switch has first end, second end and control end.First end of this first switch couples supply voltage, and the control end of first switch receives output signal, determine whether conducting according to this, and second end of first switch is as the output terminal of first buffer circuit.Energy storage device has first end and second end.First end of this energy storage device couples the control end of first switch, and second end of energy storage device couples second end of first switch.Second switch has first end, second end and control end.First end of this second switch couples second end of first switch, and second end of second switch couples common electric potential, and the control end of second switch receives the control pulse wave, determines whether conducting according to this, and the rising edge of wherein controlling pulse wave is the falling edge of output signal.Wherein, first switch in first buffer circuit and second switch are all realized with N type amorphous silicon film transistor.
According to shift register device of the present invention, it also can comprise second buffer circuit except comprising first buffer circuit.This second buffer circuit couples the output terminal of first buffer circuit, presents non-floating in order to the output terminal that keeps first buffer circuit.
The second above-mentioned buffer circuit comprises bias set circuit and the 3rd switch.This bias set circuit couples the output terminal of first buffer circuit, in order to produce bias voltage signal according to the output of first buffer circuit.The 3rd switch has first end, second end and control end.First end of this 3rd switch couples the output terminal of first buffer circuit, and second end of the 3rd switch couples common electric potential, and the control end of the 3rd switch receives bias voltage signal, determines the conducting degree according to this.
Above-mentioned bias set circuit comprises first impedance, second impedance, the 3rd impedance and the 4th switch.First impedance has first end and second end.First end of this first impedance couples supply voltage.Second impedance has first end and second end.First end of this second impedance couples second end of first impedance, and second end of second impedance couples common electric potential.A wherein end of the 3rd impedance couples common electric potential.The 4th switch has first end, second end and control end.First end of this 4th switch couples the other end of the 3rd impedance, the control end of the 4th switch couples the output terminal of first buffer circuit, in order to determining whether conducting according to the output of first buffer circuit, and second end of the 4th switch couples first end of second impedance, in order to the output bias signal.Wherein, first switch and second switch in first buffer circuit, and the 3rd switch in second buffer circuit and the 4th switch are all realized with N type amorphous silicon film transistor.
According to shift register device of the present invention, it also can comprise buffer circuit.This buffer circuit is the second above-mentioned buffer circuit.This buffer circuit couples a shared node of pull-up circuit and pull-down circuit, and this common points is in order to output signal output, and buffer circuit is in order to transmitting output signal, and keeps above-mentioned common points to present non-floating.
According to shift registor of the present invention, first clock signal and second clock signal reverse signal each other wherein.The frequency of the 3rd clock signal and the 4th clock signal and responsibility cycle are than being all 1/2nd of first clock signal, and pulse wave activation time of pulse wave of arranging sequence number in the pulse wave activation time of the 3rd clock signal and first clock signal and be odd number is identical, and the arrangement sequence number is that pulse wave activation time of pulse wave of even number is identical in the pulse wave activation time of the 4th clock signal and first clock signal.The frequency of the 5th clock signal and the 6th clock signal and responsibility cycle are than being all 1/2nd of second clock signal, and pulse wave activation time of pulse wave of arranging sequence number in the pulse wave activation time of the 5th clock signal and second clock signal and be odd number is identical, and the arrangement sequence number is that pulse wave activation time of pulse wave of even number is identical in the pulse wave activation time of the 6th clock signal and second clock signal.
The present invention couples relation because of adopting specific transistor (amorphous silicon film transistor), avoid traditional inverter circuit structure, and several specific clock pulses of arranging in pairs or groups are controlled the keying state of these amorphous silicon film transistors, reach both movable input signal, can avoid the grid of amorphous silicon film transistor to be subjected to the effect of bias voltage for a long time again.Therefore the present invention not only makes the amorphous silicon membrane in the amorphous silicon film transistor be difficult for deterioration, promote the fiduciary level of amorphous silicon film transistor, also make the critical voltage drift phenomenon of amorphous silicon film transistor can reduce to minimum, and then make output voltage to charge fully, and can use for a long time.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the circuit diagram of existing full N type amorphous silicon film transistor phase inverter.
The circuit diagram of the shift register device that Fig. 2 is disclosed for US7038653 number for United States Patent (USP).
The circuit diagram of the shift register device that Fig. 3 is disclosed for US5222082 number for United States Patent (USP).
Fig. 4 is the circuit diagram according to the shift register device of one embodiment of the invention.
Fig. 5 is each signal timing diagram of circuit shown in Figure 4.
Fig. 6 is the signal mode graphoid of circuit shown in Figure 4.
Fig. 7 is the circuit diagram according to the shift register device of another preferred embodiment of the present invention.
Fig. 8 is the circuit diagram according to the shift register device of another preferred embodiment of the present invention.
Fig. 9 is according to the circuit diagram of the shift register device of a preferred embodiment more of the present invention.
Figure 10 is the device calcspar according to the shift registor of one embodiment of the invention.
Figure 11 is each clock signal of circuit shown in Figure 10, and the sequential chart of each output signal of preceding level Four shift register device.
Embodiment
Fig. 4 is the circuit diagram according to the shift register device of one embodiment of the invention.Please refer to Fig. 4.This shift register device comprises pre-charge circuit 410, pull-up circuit 420 and pull-down circuit 430.Pre-charge circuit 410 is in order to respectively according to clock signal CK1 and CK2 sampling input signal Vin, to produce charging signals PCS1 and PCS2 respectively.Pull-up circuit 420 couples pre-charge circuit 410, in order to receive clock signal CK3 and charging signals PCS1, output signal output Vout according to this.Pull-down circuit 430 couples pre-charge circuit 410 and pull-up circuit 420, and in order to receive clock signal CK4 and charging signals PCS2, whether decision according to this is coupled to common electric potential GND with output signal Vout.
Pull-up circuit 420 comprises switch 421,422 and energy storage device 423.Switch 421 has first end, second end and control end, and its first end couples pre-charge circuit 410, and in order to receiving charging signals PCS1, and the control end of switch 421 receives clock signal CK3, determines whether conducting according to this.Switch 422 has first end, second end and control end, and its first termination time receiving arteries and veins signal CK3, and the control end of switch 422 couples second end of switch 421, and switch 422 determines whether export clock signal CK3 according to signal that its control end received, to form output signal Vout.Energy storage device 423 has first end and second end, and its first end couples the control end of switch 422, and second end of energy storage device 423 couples second end of switch 422.
Pull-down circuit 430 comprises switch 431,432 and energy storage device 433.Switch 431 has first end, second end and control end, and its first end couples pre-charge circuit 410, and in order to receiving charging signals PCS2, and the control end of switch 431 receives clock signal CK4, determines whether conducting according to this.Switch 432 has first end, second end and control end, and its first end couples second end of switch 422, second end of switch 432 couples common electric potential GND, and the control end of switch 432 couples second end of switch 431, and switch 432 is according to signal that its control end received and determine whether conducting, so that output signal Vout is coupled to common electric potential GND.Energy storage device 433 has first end and second end, and its first end couples the control end of switch 432, and second end of energy storage device 433 couples common electric potential GND.
In this embodiment, switch 411,412,421,422,431 and 432 is all realized with N type amorphous silicon film transistor, and first end of each switch, it is exactly a wherein source/drain electrode of N type amorphous silicon film transistor, second end of each switch, be exactly another source/drain electrode of N type amorphous silicon film transistor, and the control end of each switch is exactly the grid of N type amorphous silicon film transistor.Energy storage device 413,414,423 and 433 all realizes with electric capacity, and first end of each energy storage device is exactly a wherein end of electric capacity, and second end of each energy storage device is exactly the other end of electric capacity.
Fig. 5 is each signal timing diagram of circuit shown in Figure 4.Please according to the explanation needs and with reference to Fig. 4 and Fig. 5.When input signal Vin T1 activation between the first phase, the then first clock signal CK1 and second clock signal CK2 T1 activation between the first phase too, with difference actuating switch 411 and 412, and then sampling input signal Vin.Therefore input signal Vin is able to by 413 chargings of 411 pairs of energy storage devices of switch, with generation charging signals PCS1, and by 414 chargings of 412 pairs of energy storage devices of switch, to produce charging signals PCS2.
Next, clock signal CK3 with actuating switch 421, makes that charging signals PCS1 is able to remove actuating switch 422 by switch 421 in second phase T2 activation, and then makes switch 422 output clock signal CK3, to form output signal Vout.Clock signal CK4 T3 activation between the third phase then with actuating switch 431, makes that charging signals PCS2 is able to remove actuating switch 432 by switch 431, so that output signal Vout is coupled to common electric potential GND.
On practical design, be noted that, energy storage device 413 and 414 is owing to be to be responsible for store charge, and energy storage device 423 and 433 is the voltage of the control end (grid of N type amorphous silicon film transistor) of being responsible for providing switch 422 and 432 respectively, so the capacitance of energy storage device 423 and 433 must just can make the grid of N type amorphous silicon film transistor obtain enough voltage much smaller than the capacitance of energy storage device 413 and 414.In addition, energy storage device 423 also has another function, allow the voltage of output signal Vout can charge more complete exactly, this is to produce coupling effect because energy storage device 423 can be coupled near its stray capacitance (parasitic capacitance), and then the voltage of the control end of raising switch 422, make switch 422 obtain enough channel sized, this phenomenon is called Bootstrap (bootstrapping) phenomenon.
Fig. 6 is the signal mode graphoid of circuit shown in Figure 4.P1 among Fig. 6 and P2 are expressed as node P1 among Fig. 4 and the voltage signal on the P2 respectively.Can find by the analog result among Fig. 6, voltage signal on node P1 and the P2 is all very of short duration, the time of the switch 422 and 432 in the obvious presentation graphs 4 (N type amorphous silicon film transistor) bias voltage is quite short, therefore provable the present invention can significantly promote the fiduciary level of N type amorphous silicon film transistor really, has also improved the degree of stability of entire circuit simultaneously.
In order to make shift register device can be operated in higher frequency in the bigger load of the interior promotion of shorter time, the user of high-order can also add buffer circuit in shift register device shown in Figure 4, as shown in Figure 7.Fig. 7 is the circuit diagram according to the shift register device of another preferred embodiment of the present invention.Please refer to Fig. 7.Buffer circuit 710 couples the common points P3 of pull-up circuit 420 and pull-down circuit 430, in order to the driving force of buffering and enhancing output signal Vout.
In this embodiment, switch 711 and 712 is all realized with N type amorphous silicon film transistor, and first end of each switch, it is exactly a wherein source/drain electrode of N type amorphous silicon film transistor, second end of each switch, be exactly another source/drain electrode of N type amorphous silicon film transistor, and the control end of each switch is exactly the grid of N type amorphous silicon film transistor.Energy storage device 713 realizes with electric capacity, and first end of energy storage device 713 is exactly a wherein end of electric capacity, and second end of energy storage device 713 is exactly the other end of electric capacity.
Because it is exactly the ON time of switch 711 that output signal Vout presents the time of noble potential (logical one), and the rising edge of control pulse wave CP is the falling edge of output signal Vout, therefore the output signal Vout ' of buffer circuit 710 and output signal Vout almost do not have phase differential between the two, so signal Vout ' can be considered as output signal Vout, just the current potential of signal Vout ' is near the current potential of supply voltage VDD, help within the short time, promoting bigger load, make shift register device can be operated in higher frequency.In addition, the function of energy storage device 713 is similar to the function of energy storage device 423, does not repeat them here.
For the output terminal 714 that prevents buffer circuit 710 presents suspension joint (floating) state when signal Vout ' presents electronegative potential (logical zero), cause noise (noise) to take advantage of the occasion to scurry into the shift register device from output terminal 714, therefore the user also can add another kind of buffer circuit again in shift register device shown in Figure 7, as shown in Figure 8.Fig. 8 is the circuit diagram according to the shift register device of another preferred embodiment of the present invention.Please refer to Fig. 8, buffer circuit 810 can avoid the output terminal 714 of buffer circuit 710 to present a kind of buffer circuit of floating exactly.
Bias set circuit 811 comprises impedance 813,814 and 815 and switch 816.Impedance 813 has first end and second end, and its first end couples supply voltage VDD.Impedance 814 has first end and second end, and its first end couples second end of impedance 813, and second end of impedance 814 couples common electric potential GND.A wherein end of impedance 815 couples common electric potential GND.Switch 816 has first end, second end and control end, and its first end couples the other end of impedance 815, the control end of switch 816 couples the output terminal 714 of buffer circuit 710, determine whether conducting in order to the output signal Vout ' of foundation buffer circuit 710, and second end of switch 816 couples first end of impedance 814, in order to output bias signal BS.
In this embodiment, switch 812 and 816 is all realized with N type amorphous silicon film transistor, and first end of each switch, it is exactly a wherein source/drain electrode of N type amorphous silicon film transistor, second end of each switch, be exactly another source/drain electrode of N type amorphous silicon film transistor, and the control end of each switch is exactly the grid of N type amorphous silicon film transistor.Impedance 813,814 and 815 all realizes with resistance, and first end of each impedance is exactly a wherein end of resistance, and second end of each impedance is exactly the other end of resistance.
By suitably adjusting impedance 813 and 814 the two resistance ratios, make the control end (grid of amorphous silicon film transistor) of switch 812 not maintain low-voltage during output signal Vout ' (for example by adjusting the resistance of impedance 813 at buffer circuit 710, make the control end of switch 812 be reduced to 10 volts) by originally 30 volts, and make switch 812 obtain a less passage by this low-voltage, therefore extraneous noise can conduct to common electric potential GND by switch 812, also just can not disturb the regular event of shift register device.When buffer circuit 710 output signal Vout ', switch 816 conductings, make that impedance 815 is in parallel with 814 and obtain a less resistance, and then make the passage of switch 812 become littler and advance to be similar to close (turn off) state, therefore also be unlikely the normal output that influences signal Vout '.
Because the bias voltage on the control end (grid of amorphous silicon film transistor) of switch 812 is reduced to 10 volts from specified 30 volts, so the drift amount of the critical voltage of switch 812 is very little.In fact, though the size of critical voltage drift amount is to be decided by the processing procedure of amorphous silicon film transistor manufacturer, and different films also can cause different side-play amounts, yet no matter why are the processing procedure of amorphous silicon film transistor and film, document via experiment proves, when the grid bias of amorphous silicon film transistor about 10 volts, even through 100,000 seconds, also only about 0.1～0.2 volt of the drift amount of critical voltage.In addition, be noted that on practical design the size of switch 816 must reach greatly, otherwise can shape after switch 816 conductings same big resistance, make the voltage of control end of switch 812 can not diminish, cause the voltage of signal Vout ' to descend.
Certainly, if the driving force of output signal Vout is enough, when so but needing to increase the noise resisting ability of shift register device, the user just can not need add buffer circuit 710 in shift register device, get final product and only need add buffer circuit 810, as shown in Figure 9.Fig. 9 is according to the circuit diagram of the shift register device of a preferred embodiment more of the present invention.Buffer circuit 810 couples the common points P3 of pull-up circuit 420 and pull-down circuit 430, in order to transmission output signal Vout, and keeps common points P3 to present non-floating.Because working method is similar to aforesaid embodiment, does not repeat them here.
By the teaching of aforementioned each embodiment, these those skilled in the art should know by inference easily, if a plurality of shift register devices of serial connection just can have multistage output signal, as shown in figure 10.
Figure 10 is the device calcspar according to the shift registor of one embodiment of the invention.Please according to the explanation needs and with reference to Figure 10 and Fig. 4.Figure 10 shows the preceding level Four shift register device in the shift registor.Input end A in each grade shift register device is expressed as the control end of the switch 411 of Fig. 4, input end B in each grade shift register device is expressed as the control end of the switch 421 of Fig. 4, input end C in each grade shift register device is expressed as the control end of the switch 412 of Fig. 4, input end D in each grade shift register device is expressed as the control end of the switch 431 of Fig. 4, and the input end E in each grade shift register device is expressed as first end of the switch 422 of Fig. 4, as for each input end of other grades please the rest may be inferred.
Referring again to Figure 10.First shift register device, 1010 receiving inputted signal Vin, and according to the first clock signal CLK1, the second clock signal CLK2, the 3rd clock signal CLK3 and the 4th clock signal CLK4 and displacement input signal Vin, to produce the first output signal Vout1.Second shift register device 1020 receives the first output signal Vout1, and according to the first clock signal CLK1, the second clock signal CLK2, the 5th clock signal CLK5 and the 6th clock signal CLK6 and the displacement first output signal Vout1, to produce the second output signal Vout2.
The 3rd shift register device 1030 receives the second output signal Vout2, and according to the first clock signal CLK1, the second clock signal CLK2, the 3rd clock signal CLK3 and the 4th clock signal CLK4 and the displacement second output signal Vout2, to produce the 3rd output signal Vout3.The 4th shift register device 1040 receives the 3rd output signal Vout3, and according to the first clock signal CLK1, the second clock signal CLK2, the 5th clock signal CLK5 and the 6th clock signal CLK6 and displacement the 3rd output signal Vout3, to produce the 4th output signal Vout4.
Each clock signal of this embodiment, and each output signal relation each other of preceding level Four shift register device is as shown in figure 11.Figure 11 is each clock signal of circuit shown in Figure 10, and the sequential chart of each output signal of preceding level Four shift register device.Please refer to Figure 11.The first clock signal CLK1 and the second clock signal CLK2 be reverse signal each other.The frequency of the 3rd clock signal CLK3 and the 4th clock signal CLK4 and responsibility cycle are than being all 1/2nd of the first clock signal CLK1, and pulse wave activation time of pulse wave of arranging sequence number among the pulse wave activation time of the 3rd clock signal CLK3 and the first clock signal CLK1 and be odd number is identical, and the arrangement sequence number is that pulse wave activation time of pulse wave of even number is identical among the pulse wave activation time of the 4th clock signal CLK4 and the first clock signal CLK1.
The frequency of the 5th clock signal CLK5 and the 6th clock signal CLK6 and responsibility cycle are than being all 1/2nd of the second clock signal CLK2, and pulse wave activation time of pulse wave of arranging sequence number among the pulse wave activation time of the 5th clock signal CLK5 and the second clock signal CLK2 and be odd number is identical, and the arrangement sequence number is that pulse wave activation time of pulse wave of even number is identical among the pulse wave activation time of the 6th clock signal CLK6 and the second clock signal CLK2.Vout1, Vout2, Vout3 and Vout4 then represent first output signal, second output signal, the 3rd output signal and the 4th output signal respectively.
As for the later clock signal classification that shift register device at different levels received of the 4th shift register device 1040, then begin from the 5th shift registor (not illustrating), the clock signal classification that is received according to first shift register device 1010, second shift register device 1020, the 3rd shift register device 1030 and the 4th shift register device 1040 in regular turn, with per four shift register devices is that a round-robin mode receives its needed clock signal separately, does not repeat them here.What deserves to be mentioned is that the output signal that needed control pulse wave CP can directly adopt the next stage shift register device to be exported in each grade shift register device does not need additional designs.
For the convenience that illustrates, more than switch among each embodiment all be to implement with N type amorphous silicon film transistor, this is that the present invention of hypothesis user desire utilization earlier is on glass plate, but at other is not that strict restriction needs to use under the environment of amorphous silicon film transistor, and the switch in the various embodiments described above can be implemented with general N type metal oxide semiconductor transistor (N-type metal-oxide-semiconductor transistor).
Indulge the above, the present invention couples relation because of adopting specific transistor (amorphous silicon film transistor), avoid traditional inverter circuit structure, and several specific clock pulses of arranging in pairs or groups are controlled the keying state of these amorphous silicon film transistors, reach both movable input signal, can avoid the grid of amorphous silicon film transistor to be subjected to the effect of bias voltage for a long time again.Therefore the present invention not only makes the amorphous silicon membrane in the amorphous silicon film transistor be difficult for deterioration, promote the fiduciary level of amorphous silicon film transistor, also make the critical voltage drift phenomenon of amorphous silicon film transistor can reduce to minimum, and then make output voltage to charge fully.Moreover shift registor of the present invention and shift register device thereof can also use for a long time.
In addition, shift register device of the present invention is owing to only need 6 transistors to get final product work, therefore layout is simple, improved previous patent US6064713, US5105187, US5410583, the common drawback of loop such as US6300928 and US6970530 complexity, and shift registor of the present invention and shift register device thereof have significantly reduced the bias voltage time of amorphous silicon film transistor, improve the fiduciary level of amorphous silicon film transistor, improved previous patent US7038653, US5222082, US6690347 and US6970530 etc. always have an amorphous silicon film transistor at least by the common drawback of long-time bias voltage.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (33)
1. shift register device comprises:
One pre-charge circuit is in order to respectively according to one first clock signal and the one second clock signal input signal of taking a sample, to produce one first charging signals and one second charging signals respectively;
One pull-up circuit couples this pre-charge circuit, in order to receive one the 3rd clock signal and this first charging signals, exports an output signal according to this; And
One pull-down circuit couples this pre-charge circuit and this pull-up circuit, and in order to receive one the 4th clock signal and this second charging signals, whether decision according to this is coupled to a common electric potential with this output signal,
Wherein this input signal, this first clock signal and this second clock signal activation between a first phase, the 3rd clock signal is in second phase activation, the activation between a third phase of the 4th clock signal, and should the second phase between this first phase after, between this third phase after this second phase.
2. shift register device as claimed in claim 1 is characterized in that, this pre-charge circuit comprises:
One first switch has first end, second end and control end, and first termination of this first switch is received this input signal, and the control end of this first switch receives this first clock signal, determines whether conducting according to this;
One first energy storage device has first end and second end, and first end of this first energy storage device couples second end of this first switch, and in order to export this first charging signals, second end of this first energy storage device couples this common electric potential;
One second switch has first end, second end and control end, and first termination of this second switch is received this input signal, and the control end of this second switch receives this second clock signal, determines whether conducting according to this; And
One second energy storage device has first end and second end, and first end of this second energy storage device couples second end of this second switch, and in order to export this second charging signals, second end of this second energy storage device couples this common electric potential.
3. shift register device as claimed in claim 2, it is characterized in that, this first switch and this second switch respectively comprise a N type metal oxide semiconductor transistor, the transistorized wherein source/drain electrode of described N type metal oxide semiconductor is as first end of this first switch and first end of second switch, transistorized another source/drain electrode of described N type metal oxide semiconductor is as second end of this first switch and second end of this second switch, and the transistorized grid of described N type metal oxide semiconductor is as the control end of this first switch and the control end of this second switch.
4. shift register device as claimed in claim 2, it is characterized in that, this first switch and this second switch respectively comprise a N type amorphous silicon film transistor, a wherein source/drain electrode of described N type amorphous silicon film transistor is as first end of this first switch and first end of this second switch, another source/drain electrode of described N type amorphous silicon film transistor is as second end of this first switch and second end of this second switch, and the grid of described N type amorphous silicon film transistor is as the control end of this first switch and the control end of this second switch.
5. shift register device as claimed in claim 2, it is characterized in that, this first energy storage device and this second energy storage device respectively comprise an electric capacity, two ends of described electric capacity are respectively as first end and second end of this first energy storage device, and respectively as first end and second end of this second energy storage device.
6. shift register device as claimed in claim 1 is characterized in that, this pull-up circuit comprises:
One the 3rd switch has first end, second end and control end, and first end of the 3rd switch couples this pre-charge circuit, and in order to receive this first charging signals, the control end of the 3rd switch receives the 3rd clock signal, determines whether conducting according to this; And
One the 4th switch, have first end, second end and control end, first termination of the 4th switch is received the 3rd clock signal, the control end of the 4th switch couples second end of the 3rd switch, and the 4th switch is according to signal that its control end received and determine whether export the 3rd clock signal, to form this output signal.
7. shift register device as claimed in claim 6, it is characterized in that, the 3rd switch and the 4th switch respectively comprise a N type metal oxide semiconductor transistor, the transistorized wherein source/drain electrode of described N type metal oxide semiconductor is as first end of the 3rd switch and first end of the 4th switch, transistorized another source/drain electrode of described N type metal oxide semiconductor is as second end of the 3rd switch and second end of the 4th switch, and the transistorized grid of described N type metal oxide semiconductor is as the control end of the 3rd switch and the control end of the 4th switch.
8. shift register device as claimed in claim 6, it is characterized in that, the 3rd switch and the 4th switch respectively comprise a N type amorphous silicon film transistor, a wherein source/drain electrode of described N type amorphous silicon film transistor is as first end of the 3rd switch and first end of the 4th switch, another source/drain electrode of described N type amorphous silicon film transistor is as second end of the 3rd switch and second end of the 4th switch, and the grid of described N type amorphous silicon film transistor is as the control end of the 3rd switch and the control end of the 4th switch.
9. shift register device as claimed in claim 6 is characterized in that, this pull-up circuit also comprises:
One the 3rd energy storage device has first end and second end, and first end of the 3rd energy storage device couples the control end of the 4th switch, and second end of the 3rd energy storage device couples second end of the 4th switch.
10. shift register device as claimed in claim 9 is characterized in that the 3rd energy storage device comprises an electric capacity, and two ends of this electric capacity are respectively as first end and second end of the 3rd energy storage device.
11. shift register device as claimed in claim 1 is characterized in that, this pull-down circuit comprises:
One the 5th switch has first end, second end and control end, and first end of the 5th switch couples this pre-charge circuit, and in order to receive this second charging signals, the control end of the 5th switch receives the 4th clock signal, determines whether conducting according to this; And
One the 6th switch, have first end, second end and control end, first end of the 6th switch couples second end of the 4th switch, second end of the 6th switch couples this common electric potential, the control end of the 6th switch couples second end of the 5th switch, and the 6th switch is according to signal that its control end received and determine whether conducting, so that this output signal is coupled to this common electric potential.
12. shift register device as claimed in claim 11, it is characterized in that, the 5th switch and the 6th switch respectively comprise a N type metal oxide semiconductor transistor, the transistorized wherein source/drain electrode of described N type metal oxide semiconductor is as first end of the 5th switch and first end of the 6th switch, transistorized another source/drain electrode of described N type metal oxide semiconductor is as second end of the 5th switch and second end of the 6th switch, and the transistorized grid of described N type metal oxide semiconductor is as the control end of the 5th switch and the control end of the 6th switch.
13. shift register device as claimed in claim 11, it is characterized in that, the 5th switch and the 6th switch respectively comprise a N type amorphous silicon film transistor, a wherein source/drain electrode of described N type amorphous silicon film transistor is as first end of the 5th switch and first end of the 6th switch, another source/drain electrode of described N type amorphous silicon film transistor is as second end of the 5th switch and second end of the 6th switch, and the grid of described N type amorphous silicon film transistor is as the control end of the 5th switch and the control end of the 6th switch.
14. shift register device as claimed in claim 11 is characterized in that, this pull-down circuit also comprises:
One the 4th energy storage device has first end and second end, and first end of the 4th energy storage device couples the control end of the 6th switch, and second end of the 4th energy storage device couples this common electric potential.
15. shift register device as claimed in claim 14 is characterized in that, the 4th energy storage device comprises an electric capacity, and two ends of this electric capacity are respectively as first end and second end of the 4th energy storage device.
16. shift register device as claimed in claim 1, it is characterized in that, the 3rd clock signal is the reverse signal of this first clock signal, and the frequency of this second clock signal and the 4th clock signal and responsibility cycle are than being all 1/2nd of this first clock signal.
17. shift register device as claimed in claim 1 is characterized in that, also comprises:
One buffer circuit couples a shared node of this pull-up circuit and this pull-down circuit, and this common points is in order to exporting this output signal, and this buffer circuit is in order to transmitting this output signal, and keeps this common points to present non-floating.
18. shift register device as claimed in claim 17 is characterized in that, this buffer circuit comprises:
One bias set circuit couples this common points, in order to produce a bias voltage signal according to this output signal; And
One first switch has first end, second end and control end, and first end of this first switch couples this common points, and second end of this first switch couples this common electric potential, and the control end of this first switch receives this bias voltage signal, determines the conducting degree according to this.
19. shift register device as claimed in claim 18 is characterized in that, this bias set circuit comprises:
One first impedance has first end and second end, and first end of this first impedance couples a supply voltage;
One second impedance has first end and second end, and first end of this second impedance couples second end of this first impedance, and second end of this second impedance couples this common electric potential;
One the 3rd impedance, a wherein end of the 3rd impedance couples this common electric potential; And
One second switch, have one first end, one second end and a control end, first end of this second switch couples the other end of the 3rd impedance, the control end of this second switch couples this common points, in order to determine whether conducting according to this output signal, and second end of this second switch couples first end of this second impedance, in order to export this bias voltage signal.
20. shift register device as claimed in claim 19, it is characterized in that, this first switch and this second switch respectively comprise a N type metal oxide semiconductor transistor, the transistorized wherein source/drain electrode of described N type metal oxide semiconductor is as first end of this first switch and first end of this second switch, transistorized another source/drain electrode of described N type metal oxide semiconductor is as second end of this first switch and second end of this second switch, and the transistorized grid of described N type metal oxide semiconductor is as the control end of this first switch and the control end of this second switch.
21. shift register device as claimed in claim 19, it is characterized in that, this first switch and this second switch respectively comprise a N type amorphous silicon film transistor, a wherein source/drain electrode of described N type amorphous silicon film transistor is as first end of this first switch and first end of this second switch, another source/drain electrode of described N type amorphous silicon film transistor is as second end of this first switch and second end of this second switch, and the grid of described N type amorphous silicon film transistor is as the control end of this first switch and the control end of this second switch.
22. shift register device as claimed in claim 1 is characterized in that, also comprises:
One first buffer circuit, this first buffer circuit couple a shared node of this pull-up circuit and this pull-down circuit, and this common points is in order to exporting this output signal, and this first buffer circuit is in order to buffering and strengthen the driving force of this output signal.
23. shift register device as claimed in claim 22 is characterized in that, this first buffer circuit comprises:
One first switch, have first end, second end and control end, first end of this first switch couples a supply voltage, and the control end of this first switch receives this output signal, determine whether conducting according to this, second end of this first switch is as the output terminal of this first buffer circuit;
One energy storage device has first end and second end, and first end of this energy storage device couples the control end of this first switch, and second end of this energy storage device couples second end of this first switch; And
One second switch, have first end, second end and control end, first end of this second switch couples second end of this first switch, second end of this second switch couples this common electric potential, the control end of this second switch receives a control pulse wave, determine whether conducting according to this, rising edge that wherein should the control pulse wave is the falling edge of this output signal.
24. shift register device as claimed in claim 23, it is characterized in that, this first switch and this second switch respectively comprise a N type metal oxide semiconductor transistor, the transistorized wherein source/drain electrode of described N type metal oxide semiconductor is as first end of this first switch and first end of this second switch, transistorized another source/drain electrode of described N type metal oxide semiconductor is as second end of this first switch and second end of this second switch, and the transistorized grid of described N type metal oxide semiconductor is as the control end of this first switch and the control end of this second switch.
25. shift register device as claimed in claim 23, it is characterized in that, this first switch and this second switch respectively comprise a N type amorphous silicon film transistor, a wherein source/drain electrode of described N type amorphous silicon film transistor is as first end of this first switch and first end of this second switch, another source/drain electrode of described N type amorphous silicon film transistor is as second end of this first switch and second end of this second switch, and the grid of described N type amorphous silicon film transistor is as the control end of this first switch and the control end of this second switch.
26. shift register device as claimed in claim 23 is characterized in that, this energy storage device comprises an electric capacity, and two ends of this electric capacity are respectively as first end and second end of this energy storage device.
27. shift register device as claimed in claim 23 is characterized in that, also comprises:
One second buffer circuit, this second buffer circuit couples the output terminal of this first buffer circuit, presents non-floating in order to the output terminal that keeps this first buffer circuit.
28. shift register device as claimed in claim 27 is characterized in that, this second buffer circuit comprises:
One bias set circuit couples the output terminal of this first buffer circuit, in order to produce a bias voltage signal according to the output of this first buffer circuit; And
One the 3rd switch, have first end, second end and control end, first end of the 3rd switch couples the output terminal of this first buffer circuit, and second end of the 3rd switch couples this common electric potential, the control end of the 3rd switch receives this bias voltage signal, determines the conducting degree according to this.
29. shift register device as claimed in claim 28 is characterized in that, this bias set circuit comprises:
One first impedance has first end and second end, and first end of this first impedance couples this supply voltage;
One second impedance has first end and second end, and first end of this second impedance couples second end of this first impedance, and second end of this second impedance couples this common electric potential;
One the 3rd impedance, a wherein end of the 3rd impedance couples this common electric potential; And
One the 4th switch, have first end, second end and control end, first end of the 4th switch couples the other end of the 3rd impedance, the control end of the 4th switch couples the output terminal of this first buffer circuit, in order to determine whether conducting according to the output of this first buffer circuit, and second end of the 4th switch couples first end of this second impedance, in order to export this bias voltage signal.
30. shift register device as claimed in claim 29, it is characterized in that, the 3rd switch and the 4th switch respectively comprise a N type metal oxide semiconductor transistor, the transistorized wherein source/drain electrode of described N type metal oxide semiconductor is as first end of the 3rd switch and first end of the 4th switch, transistorized another source/drain electrode of described N type metal oxide semiconductor is as second end of the 3rd switch and second end of the 4th switch, and the transistorized grid of described N type metal oxide semiconductor is as the control end of the 3rd switch and the control end of the 4th switch.
31. shift register device as claimed in claim 29, it is characterized in that, the 3rd switch and the 4th switch respectively comprise a N type amorphous silicon film transistor, a wherein source/drain electrode of described N type amorphous silicon film transistor is as first end of the 3rd switch and first end of the 4th switch, another source/drain electrode of described N type amorphous silicon film transistor is as second end of the 3rd switch and second end of the 4th switch, and the grid of described N type amorphous silicon film transistor is as the control end of the 3rd switch and the control end of the 4th switch.
32. a shift registor comprises:
One first shift register device receives an input signal, and according to one first clock signal, one second clock signal, one the 3rd clock signal and one the 4th clock signal and this input signal of displacement, to produce one first output signal; And
One second shift register device receives this first output signal, and according to this first clock signal, this second clock signal, one the 5th clock signal and one the 6th clock signal this first output signal of displacement, to produce one second output signal.
33. shift registor as claimed in claim 32, it is characterized in that, this first clock signal and this second clock signal be reverse signal each other, the frequency of the 3rd clock signal and the 4th clock signal and responsibility cycle are than being all 1/2nd of this first clock signal, and pulse wave activation time of pulse wave of arranging sequence number in the pulse wave activation time of the 3rd clock signal and this first clock signal and be odd number is identical, and arrange sequence number in the pulse wave activation time of the 4th clock signal and this first clock signal is that pulse wave activation time of pulse wave of even number is identical, the frequency of the 5th clock signal and the 6th clock signal and responsibility cycle are than being all 1/2nd of this second clock signal, and pulse wave activation time of pulse wave of arranging sequence number in the pulse wave activation time of the 5th clock signal and this second clock signal and be odd number is identical, and the arrangement sequence number is that pulse wave activation time of pulse wave of even number is identical in the pulse wave activation time of the 6th clock signal and this second clock signal.
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| CN2007101063328A CN101308705B (en) | 2007-05-15 | 2007-05-15 | Shift register and shift registering apparatus |
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| CN2007101063328A CN101308705B (en) | 2007-05-15 | 2007-05-15 | Shift register and shift registering apparatus |
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| TWI393978B (en) * | 2009-07-14 | 2013-04-21 | Au Optronics Corp | Liquid crystal display and shift register device thereof |
| CN103198866A (en) * | 2013-03-06 | 2013-07-10 | 京东方科技集团股份有限公司 | Shift registers, gate drive circuit, array substrate and display device |
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