CN101304237B - Amplifier apparatus capable of eliminating migration voltage - Google Patents
Amplifier apparatus capable of eliminating migration voltage Download PDFInfo
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- CN101304237B CN101304237B CN2007101028362A CN200710102836A CN101304237B CN 101304237 B CN101304237 B CN 101304237B CN 2007101028362 A CN2007101028362 A CN 2007101028362A CN 200710102836 A CN200710102836 A CN 200710102836A CN 101304237 B CN101304237 B CN 101304237B
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Abstract
An amplifier installation which can remove the offset voltage comprises an offset voltage removing device, an input stage circuit, an output stage circuit, a false output stage circuit, a commutation circuit and a voltage output terminal. The commutation circuit is coupled to a part among the input stage circuit, the output stage circuit and the false output stage circuit, is used for choosing according to an operation mode to conduct one preamplifier signals which are outputted by the input stage circuit to the output stage circuit and to feed back a first feedback voltage which is outputted by the output stage circuit to the input stage circuit; or to conduct the preamplifier signals which are outputted by the input stage circuit to the false output stage circuit and to feed back the second feedback voltage output by the false output stage circuit to the input stage circuit.
Description
Technical field
The present invention relates to a kind of amplifier installation of eliminating offset voltage, relate in particular to a kind of dummy output level circuit that utilizes, be not subjected to the influence of load, thereby eliminate the amplifier installation of offset voltage influence fully to guarantee stored offset voltage.
Background technology
Operational amplifier is that an important circuit bank becomes assembly in the various electronic installations, and it is widely used in fields such as household electrical appliances, industry and scientific instrument.Circuit designers often can use operational amplifier to realize many different operational functions, as buffer, filter, analog-to-digital converter etc.
Desirable operational amplifier possesses following properties: input impedance infinity, output impedance equal zero, open the loop gain infinity, common-mode rejection ratio (Common Mode Rejection Ratio) is infinitely great, frequency range is infinitely great.Yet because the restriction of semiconductor technology and integrated circuit technique, there is some non-ideal characteristic in the actual operation amplifier.Therefore, known technology is represented the imperfection of operational amplifier with an offset voltage (Offset Voltage).For the imperfection of compensated operational amplifier, industry has proposed many offset voltage removing methods and relevant apparatus thereof.
For instance, please refer to Fig. 1, Fig. 1 is a known schematic diagram of eliminating the amplifier installation 100 of offset voltage.Amplifier installation 100 comprises a unit gain operational amplifier 110, an offset voltage cancellation element 120 and an equivalent voltage source 102.The gain of unit gain operational amplifier 110 is 1, and promptly output voltage V o equals input voltage Vi, and it comprises an input stage circuit 1101 and an output-stage circuit 1102.Equivalent voltage source 102 is used for the imperfection (not being present on the side circuit) of representation unit gain operational amplifier 110, the offset voltage of the voltage Vos representation unit gain operational amplifier 110 that it produced.120 of offset voltage cancellation elements are used for compensating migration voltage, and it includes switch S 11, S12, S21 and a capacitor C s.
Offset voltage cancellation element 120 utilizes virtual short (Virtual Short) characteristic of unit gain operational amplifier 110, eliminates the influence of offset voltage Vos, and its function mode is as follows.At first, when amplifier installation 100 operates in an offset voltage storage mode, switch S 11, S12 conducting, and switch S 21 is closed, then the positive input terminal of unit gain operational amplifier 110 and the voltage difference between output end vo (being offset voltage Vos) can be charged to capacitor C s.Then, when amplifier installation 100 operates in offset voltage elimination pattern, switch S 21 conductings, and switch S 11, S12 are closed, the stored voltage difference in capacitor C s two ends then, its size and polarity can be offset the influence of offset voltage Vos, make that the voltage difference between (input voltage Vi is) positive input terminal and output end vo is 0 at 0 o'clock, thereby eliminate offset voltage Vos.
When the output voltage V o of amplifier installation 100 changes along with input voltage Vi, the conducting of offset voltage cancellation element 120 by diverter switch S11, S12, S21 with close, but the influence of compensating migration voltage Vos.Yet, when the output of unit gain operational amplifier 110 is coupled to an electric capacity, the time that output voltage V o changes with input voltage Vi can be subjected to the rate of reversing (Slew Rate) influence of unit gain operational amplifier 110, that is output voltage V o can't with input voltage Vi synchronous change, make the gap of output voltage V o and input voltage Vi within a certain period, be not equal to 0.In this case, the magnitude of voltage that is stored in capacitor C s can change because of the skew of output voltage V o, promptly is not equal to the value of offset voltage Vos.Thus, when amplifier installation 100 operates in offset voltage elimination pattern, because the magnitude of voltage of capacitor C s is not equal to the value of offset voltage Vos, makes offset voltage Vos to be eliminated fully, thereby influences the performance and the scope of application thereof of amplifier installation 100.
Summary of the invention
Therefore, main purpose of the present invention promptly is to provide a kind of amplifier installation of eliminating offset voltage.
The present invention discloses a kind of amplifier installation of eliminating offset voltage, include an offset voltage cancellation element, include an input voltage receiving terminal, one first output and one second output, be used for receiving an input voltage by this input voltage receiving terminal, and according to an operator scheme, the influence of compensating migration voltage is to export a compensation result by this first output and this second output; One input stage circuit is used for this compensation result of exporting according to this first output and this second output of this offset voltage cancellation element, exports a prime amplifying signal; One output-stage circuit is used for this prime amplifying signal of exporting according to this input stage circuit, and voltage and one first feedback voltage are amplified in output one; One dummy output level circuit is used for this prime amplifying signal of exporting according to this input stage circuit, exports one second feedback voltage; One switches circuit, be coupled between this input stage circuit, this output-stage circuit and this dummy output level circuit, be used for according to this operator scheme, this first feedback voltage that this prime amplifying signal conducting that this input stage circuit is exported in selection is also exported this output-stage circuit to this output-stage circuit feeds back to this input stage circuit, and this second feedback voltage that this prime amplifying signal conducting of maybe this input stage circuit being exported is also exported this dummy output level circuit to this dummy output level circuit feeds back to this input stage circuit; An and voltage output end, be used for exporting this amplification voltage that this output-stage circuit is exported, this offset voltage cancellation element includes: one first switch includes one first end and be coupled to this input voltage receiving terminal, and one second end is coupled to this first output; One second switch includes one first end, and one second end is coupled to this second output; One the 3rd switch includes one first end and is coupled to this input voltage receiving terminal, and one second end is coupled to this first end of this second switch; And an electric capacity, include between this second end and this first output that one first end is coupled to this first switch, and one second end is coupled between this second end of this first end of this second switch and the 3rd switch.
Description of drawings
Fig. 1 is a known schematic diagram of eliminating the amplifier installation of offset voltage.
Fig. 2 can eliminate the schematic diagram of the amplifier installation of offset voltage for the embodiment of the invention.
Fig. 3 is the schematic diagram of the voltage adjuster realized according to the amplifier installation of Fig. 2.
Fig. 4 is the schematic diagram of one embodiment of the invention amplifier installation.
Fig. 5 is the schematic diagram of one embodiment of the invention amplifier installation.
Fig. 6 is the schematic diagram of the digital to analog converter realized according to the amplifier installation of Fig. 2.
Fig. 7 is the schematic diagram of the gain amplifier realized according to the amplifier installation of Fig. 2.
The reference numeral explanation
110 unit gain operational amplifiers
120 offset voltage cancellation elements
102 equivalent voltage sources
100,20 amplifier installations
30 voltage adjusters
200,300,500 offset voltage cancellation elements
202,302,502 input stage circuits
204,304,404,504 output-stage circuits
206,306,506 dummy output level circuit
208,308,508 commutation circuits
210,310,510 voltage output ends
216 equivalent voltage sources
211 input voltage receiving terminals
212 first outputs
214 second outputs
Vam_F prime amplifying signal
V_FB1 first feedback voltage
V_FB2 second feedback voltage
3020,5020,5040,5060 first input ends
3022,5022,5042,5,062 second inputs
3024,3044,5044 outputs
5,024 first outputs
5,026 second outputs
3040,3060 inputs
3042,3062,5046,5064 feedback voltage outputs
S23, S24, S25, S13, S14, S15 switch
The Vo output voltage
The Vi input voltage
The Vos offset voltage
Cs electric capacity
PMOS1, PMOS2 P-type mos transistor
The CS1 current source
Embodiment
Please refer to Fig. 2, Fig. 2 can eliminate the schematic diagram of the amplifier installation 20 of offset voltage for the embodiment of the invention.Amplifier installation 20 includes an offset voltage cancellation element 200, an input stage circuit 202, an output-stage circuit 204, a dummy output level circuit 206, a switching circuit 208 and a voltage output end 210.Offset voltage cancellation element 200 comprises an input voltage receiving terminal 211, one first output 212 and one second output 214, be used for receiving an input voltage Vi by input voltage receiving terminal 211, and according to an operator scheme, the influence of compensating migration voltage, with by first output 212 and second output, 214 output offset voltage compensation results to input stage circuit 202, then input stage circuit 202 can be exported a prime amplifying signal Vam_F according to this.According to the prime amplifying signal Vam_F that input stage circuit 202 is exported, output-stage circuit 204 an exportable voltage Vo and first feedback voltage V _ FB1, dummy output level circuit 206 then exportable second feedback voltage V _ FB2.Commutation circuit 208 is coupled between input stage circuit 202, output-stage circuit 204 and the dummy output level circuit 206, be used for according to different operator schemes, selection feeds back to input stage circuit 202 with prime amplifying signal Vam_F conducting to output-stage circuit 204 and first feedback voltage V _ FB1 that output-stage circuit 204 is exported, or prime amplifying signal Vam_F conducting to dummy output level circuit 206 and second feedback voltage V _ FB2 that dummy output level circuit 206 is exported fed back to input stage circuit 202.210 of voltage output ends are used for output voltage V o.In addition, an equivalent voltage source 216 is used for representing the imperfection (not being present on the side circuit) of amplifier installation 20, and the voltage Vos that it produced represents offset voltage.
The function mode of amplifier installation 20 is as follows.At first, when amplifier installation 20 operates in an offset voltage storage mode, offset voltage cancellation element 200 stores offset voltage Vos, and commutation circuit 208 feeds back to input stage circuit 202 with prime amplifying signal Vam_F conducting to dummy output level circuit 206 and second feedback voltage V _ FB2 that dummy output level circuit 206 is exported, and promptly output-stage circuit 204 does not act on.In this case, offset voltage cancellation element 200 stored voltages can not be subjected to the influence of output-stage circuit 204 load variations and change.When amplifier installation 20 operates in offset voltage elimination pattern, commutation circuit 208 feeds back to input stage circuit 202 with prime amplifying signal Vam_F conducting to output-stage circuit 204 and first feedback voltage V _ FB1 that output-stage circuit 204 is exported, i.e. dummy output level circuit 206 does not act on.In this case, output voltage V o can change with input voltage Vi, and offset voltage Vos can be eliminated accurately.
In other words, when operating in the offset voltage storage mode, dummy output level circuit 206 acts on, and output-stage circuit 204 does not act on.Because dummy output level circuit 206 is not coupled to voltage output end 210, the second feedback voltage V _ FB2 that makes dummy output level circuit 206 be exported can not be subjected to the influence of the load that voltage output end 210 coupled.Therefore, when operating in the offset voltage storage mode, offset voltage cancellation element 200 can accurately store offset voltage Vos.Thus, when operating in offset voltage elimination pattern, offset voltage cancellation element 200 can be eliminated the influence of offset voltage Vos fully, makes the reliability of amplifier installation 20 be increased.
What pay special attention to is, amplifier installation 20 shown in Figure 2 is embodiments of the invention, and those skilled in the art can make different variations according to this, as realizing output-stage circuit 204 with the circuit that can strengthen the rate of reversing.In addition, between each inter-module online in order to the expression signal transmission path, the entity number of, lines can change according to this according to different application.
For instance, please refer to Fig. 3, Fig. 3 is the schematic diagram of the voltage adjuster 30 realized according to the amplifier installation 20 of Fig. 2.Voltage adjuster 30 includes an offset voltage cancellation element 300, an input stage circuit 302, an output-stage circuit 304, a dummy output level circuit 306, switching circuit 308, a voltage output end 310 and a capacitor C
LThe input voltage Vi of voltage adjuster 30 is a certain value, but capacitor C
LStored output voltage V o can change because of the operation of load circuit.The framework of offset voltage cancellation element 300 is identical with offset voltage cancellation element 120 among Fig. 1, is made up of switch S 11, S12, S21 and capacitor C s.Input stage circuit 302 is in order to receive the signal that offset voltage cancellation element 300 is exported by a first input end 3020 and one second input 3022, after a prime processing unit (not being plotted among Fig. 3) processing, by an output 3024 output prime amplifying signal Vam_F.Commutation circuit 308 is made up of switch S 23, S24, S13, S14, is used for controlling the binding of input stage circuit 302 and output-stage circuit 304 or dummy output level circuit 306.When switch S 23, S24 conducting, output-stage circuit 304 receives prime amplifying signal Vam_F by an input 3040, after back grade processing unit (a being formed) processing by a P-type mos transistor PMOS1 and resistance R 1, R2, by an output 3044 output voltage V o to capacitor C
L, and by second input 3022 of a feedback voltage output 3042 output feedback signals to input stage circuit 302.Similarly, when switch S 13, S14 conducting, dummy output level circuit 306 receives prime amplifying signal Vam_F by an input 3060, after back grade processing unit (a being formed) processing, by second input 3022 of a feedback voltage output 3062 output feedback signals to input stage circuit 302 by a P-type mos transistor PMOS2 and a current source CS1.
In Fig. 3, offset voltage cancellation element 300 and commutation circuit 308 be according to different operator schemes, the conducting of control switch S11, S12, S13, S14, S21, S23, S24 with close.When voltage adjuster 30 operates in the offset voltage storage mode, switch S 11, S12, S13, S14 conducting, and switch S 21, S23, S24 are closed, then only dummy output level circuit 306 effects, therefore, input stage circuit 302 forms the unit gain operational amplifier with dummy output level circuit 306, and capacitor C s stores offset voltage.In this case, because dummy output level circuit 306 is not coupled to voltage output end 310, the feedback voltage that makes dummy output level circuit 306 be exported can not be subjected to the capacitor C that voltage output end 310 is coupled
LInfluence, therefore, the stored voltage of capacitor C s can not be subjected to the influence of output-stage circuit 304 load changes.Then, when voltage adjuster 30 operates in offset voltage elimination pattern, switch S 11, S12, S13, S14 close, and switch S 21, S23, S24 conducting, then only output-stage circuit 304 effects, therefore, output voltage V o can change with input voltage Vi, and offset voltage Vos can be eliminated accurately.
In other words, when operating in the offset voltage storage mode, dummy output level circuit 306 acts on, and output-stage circuit 304 does not act on.Because dummy output level circuit 306 is not coupled to voltage output end 310, the feedback voltage that makes dummy output level circuit 306 be exported can not be subjected to the influence of the load that voltage output end 310 coupled.Therefore, when operating in the offset voltage storage mode, capacitor C s can accurately store offset voltage Vos.Thus, when operating in offset voltage and eliminate pattern, the influence that offset voltage cancellation element 300 can more accurate elimination offset voltage Vos makes the accuracy of voltage adjuster 30 be increased.
In Fig. 3, dummy output level circuit 306 is category-A (Class-A) output-stage circuit, and output-stage circuit 304 then is made up of transistor PMOS1 and resistance R 1, R2, and certainly, output-stage circuit 304 also can be replaced by the category-A output-stage circuit.Please refer to Fig. 4, Fig. 4 is the schematic diagram of one embodiment of the invention amplifier installation 40.The circuit framework of amplifier installation 40 is similar to the voltage adjuster of Fig. 3 30, precisely because output-stage circuit 404 is the category-A output-stage circuit, the associative operation mode repeats no more.
As previously mentioned, in Fig. 2, between each inter-module online in order to the expression signal transmission path, the entity number of, lines can change according to this according to different application.For example, when realizing the amplifier installation 20 of Fig. 2 with track to track formula framework, input stage circuit 202 comprises two outputs.Please refer to Fig. 5, Fig. 5 is the schematic diagram of one embodiment of the invention amplifier installation 50.Amplifier installation 50 includes an offset voltage cancellation element 500, an input stage circuit 502, an output-stage circuit 504, a dummy output level circuit 506, a switching circuit 508 and a voltage output end 510.Offset voltage cancellation element 500 is identical with offset voltage cancellation element 200, in order to the influence of compensating migration voltage.502 signals of being exported by a first input end 5020 and one second input, 5022 reception offset voltage cancellation elements 500 of input stage circuit, after a prime processing unit (not being plotted among Fig. 5) processing, by one first output 5024 and one second output, 5026 output prime amplifying signals.Commutation circuit 508 is made up of switch S 23, S24, S25, S13, S14, S15, is used for controlling the binding of input stage circuit 502 and output-stage circuit 504 or dummy output level circuit 506.When switch S 23, S24, S25 conducting, output-stage circuit 504 receives the prime amplifying signal by a first input end 5040 and one second input 5042, after back grade processing unit (a being formed) processing by P type and N transistor npn npn, by an output 5044 output voltage V o, and by second input 5022 of a feedback voltage output 5046 output feedback signals to input stage circuit 502.Similarly, when switch S 13, S14, S15 conducting, dummy output level circuit 506 receives the prime amplifying signal by a first input end 5060 and one second input 5062, after back grade processing unit (a being formed) processing, by second input 5022 of a feedback voltage output 5064 output feedback signals to input stage circuit 502 by P type and N transistor npn npn.
Therefore, in the present invention, because dummy output level circuit is not coupled to voltage output end, the feedback voltage that makes dummy output level circuit be exported can not be subjected to the influence of the load that voltage output end couples.Therefore, when operating in the offset voltage storage mode, the offset voltage cancellation element can accurately store offset voltage Vos, makes the influence that the offset voltage cancellation element can more accurate elimination offset voltage Vos, increasing accuracy, and then enlarges range of application.For example, in Fig. 6, amplifier installation 20 realizes that one is used for the output buffer of digital to analog converter; In Fig. 7, amplifier installation 20 is realized a gain amplifier (having increased divider resistance on the feedback path of output-stage circuit 204).
In sum, the present invention utilizes dummy output level circuit, guarantees that the stored offset voltage of offset voltage cancellation element is not subjected to the influence of load, makes the influence that the offset voltage cancellation element can more accurate elimination offset voltage, with the increase accuracy, and then enlarge range of application.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (35)
1. the amplifier installation that can eliminate offset voltage includes:
One offset voltage cancellation element, include an input voltage receiving terminal, one first output and one second output, be used for receiving an input voltage by this input voltage receiving terminal, and according to an operator scheme, the influence of compensating migration voltage is to export a compensation result by this first output and this second output;
One input stage circuit is used for this compensation result of exporting according to this first output and this second output of this offset voltage cancellation element, exports a prime amplifying signal;
One output-stage circuit is used for this prime amplifying signal of exporting according to this input stage circuit, and voltage and one first feedback voltage are amplified in output one;
One dummy output level circuit is used for this prime amplifying signal of exporting according to this input stage circuit, exports one second feedback voltage;
One switches circuit, be coupled between this input stage circuit, this output-stage circuit and this dummy output level circuit, be used for according to this operator scheme, this first feedback voltage that this prime amplifying signal conducting that this input stage circuit is exported in selection is also exported this output-stage circuit to this output-stage circuit feeds back to this input stage circuit, and this second feedback voltage that this prime amplifying signal conducting of maybe this input stage circuit being exported is also exported this dummy output level circuit to this dummy output level circuit feeds back to this input stage circuit; And
One voltage output end is used for exporting this amplification voltage that this output-stage circuit is exported,
This offset voltage cancellation element includes:
One first switch includes one first end and is coupled to this input voltage receiving terminal, and one second end is coupled to this first output;
One second switch includes one first end, and one second end is coupled to this second output;
One the 3rd switch includes one first end and is coupled to this input voltage receiving terminal, and one second end is coupled to this first end of this second switch; And
One electric capacity includes between this second end and this first output that one first end is coupled to this first switch, and one second end is coupled between this second end of this first end of this second switch and the 3rd switch.
2. amplifier installation as claimed in claim 1, wherein when this operator scheme is the offset voltage storage mode, this first switch and this second switch conducting, the 3rd switch cuts out.
3. amplifier installation as claimed in claim 1, wherein when this operator scheme was offset voltage elimination pattern, this first switch and this second switch were closed, the 3rd switch conduction.
4. amplifier installation as claimed in claim 1, wherein this input stage circuit includes:
One first input end is coupled to this first output of this offset voltage cancellation element;
One second input is coupled to this second output of this offset voltage cancellation element;
One output; And
One prime processing unit is coupled to this first input end, this second input and this output, is used for signal according to this first input end and this second input, exports this prime amplifying signal by this output;
Wherein, this second input and this first input end are virtual short.
5. amplifier installation as claimed in claim 4, wherein this output-stage circuit includes:
One input;
One feedback voltage output;
One output; And
One back grade processing unit, this prime amplifying signal that is used for receiving according to this input is exported this first feedback voltage and is exported this amplification voltage by this output by this feedback voltage output.
6. amplifier installation as claimed in claim 5, wherein this back level processing unit includes:
One transistor includes one first end and is coupled to this input, and one second end is coupled to a power supply generator, and one the 3rd end is coupled to this output, is used for signal according to this first end, and this second end of conducting is to the binding of the 3rd end;
One first resistance, one end are coupled between this transistorized the 3rd end and this output, and the other end is coupled to this feedback voltage output; And
One second resistance, one end are coupled between this feedback voltage output and this first resistance, and the other end is coupled to a ground end.
7. amplifier installation as claimed in claim 6, wherein this transistor is a P-type mos transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
8. amplifier installation as claimed in claim 5, wherein this back level processing unit includes:
One transistor, include one first end and be coupled to this input, one second end is coupled to a power supply generator, and one the 3rd end is coupled to this output and this feedback voltage output, be used for signal according to this first end, this second end of conducting is to the binding of the 3rd end; And
One current source is coupled to this output, this feedback voltage output and this transistorized the 3rd end, is used for drawing electric current.
9. amplifier installation as claimed in claim 8, wherein this transistor is a P-type mos transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
10. amplifier installation as claimed in claim 5, wherein this dummy output level circuit includes:
One input;
One feedback voltage output; And
One back grade processing unit, this prime amplifying signal that is used for receiving according to this input is exported this second feedback voltage by this feedback voltage output.
11. amplifier installation as claimed in claim 10, wherein this back level processing unit includes:
One transistor includes one first end and is coupled to this input, and one second end is coupled to a power supply generator, and one the 3rd end is coupled to this feedback voltage output, is used for signal according to this first end, and this second end of conducting is to the binding of the 3rd end; And
One current source is coupled to this feedback voltage output and this transistorized the 3rd end, is used for drawing electric current.
12. amplifier installation as claimed in claim 11, wherein this transistor is a P-type mos transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
13. amplifier installation as claimed in claim 10, wherein this commutation circuit includes:
One first switch includes this output that one first end is coupled to this input stage circuit, and one second end is coupled to this input of this output-stage circuit;
One second switch includes this output that one first end is coupled to this input stage circuit, and one second end is coupled to this input of this dummy output level circuit;
One the 3rd switch includes this second input that one first end is coupled to this input stage circuit, and one second end is coupled to this feedback voltage output of this output-stage circuit; And
One the 4th switch includes this second input that one first end is coupled to this input stage circuit, and one second end is coupled to this feedback voltage output of this dummy output level circuit.
14. amplifier installation as claimed in claim 13, wherein when this operator scheme is the offset voltage storage mode, this second switch of this commutation circuit and the 4th switch conduction of this commutation circuit, the 3rd switch of this of this commutation circuit first switch and this commutation circuit cuts out.
15. amplifier installation as claimed in claim 13, wherein when this operator scheme is offset voltage elimination pattern, this second switch of this commutation circuit and the 4th switch of this commutation circuit are closed, the 3rd switch conduction of this of this commutation circuit first switch and this commutation circuit.
16. amplifier installation as claimed in claim 13, wherein this second switch of this of this commutation circuit first switch and this commutation circuit is realized with a selector.
17. amplifier installation as claimed in claim 13, wherein the 4th switch of the 3rd switch of this commutation circuit and this commutation circuit is realized with a selector.
18. amplifier installation as claimed in claim 1, wherein this input stage circuit is a track to track formula input stage circuit, includes:
One first input end is coupled to this first output of this offset voltage cancellation element;
One second input is coupled to this second output of this offset voltage cancellation element;
One first output;
One second output; And
One prime processing unit, be coupled to this first input end, this second input, this first output and this second output, be used for signal according to this first input end and this second input, export this prime amplifying signal by this first output and this second output;
Wherein, this second input and this first input end are virtual short.
19. amplifier installation as claimed in claim 18, wherein this output-stage circuit includes:
One first input end;
One second input;
One feedback voltage output;
One output; And
One back grade processing unit is used for this prime amplifying signal of being received according to this first input end and this second input, exports this first feedback voltage by this feedback voltage output and reaches and export this amplification voltage by this output.
20. amplifier installation as claimed in claim 19, wherein this back level processing unit includes:
One the first transistor, include one first end and be coupled to this first input end, one second end is coupled to a power supply generator, and one the 3rd end is coupled between this output and this feedback voltage output, be used for signal according to this first end, this second end of conducting is to the binding of the 3rd end; And
One transistor seconds, include one first end and be coupled to this second input, one second end is coupled to the 3rd end of this output, this feedback voltage output and this first transistor, and one the 3rd end is coupled to a ground end, be used for signal according to this first end, this second end of conducting is to the binding of the 3rd end.
21. amplifier installation as claimed in claim 20, wherein this first transistor is a P-type mos transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
22. amplifier installation as claimed in claim 20, wherein this transistor seconds is a N type metal oxide semiconductor transistor, and this first end is a grid, and this second end is drain electrode, and the 3rd end is a source electrode.
23. amplifier installation as claimed in claim 19, wherein this dummy output level circuit includes:
One first input end;
One second input;
One feedback voltage output; And
One back grade processing unit is used for this prime amplifying signal of being received according to this first input end and this second input, exports this second feedback voltage by this feedback voltage output.
24. amplifier installation as claimed in claim 23, wherein this back level processing unit includes:
One the first transistor includes one first end and is coupled to this first input end, and one second end is coupled to a power supply generator, and one the 3rd end is coupled to this feedback voltage output, is used for signal according to this first end, and this second end of conducting is to the binding of the 3rd end; And
One transistor seconds, include one first end and be coupled to this second input, one second end is coupled between the 3rd end of this feedback voltage output and this first transistor, and one the 3rd end is coupled to a ground end, be used for signal according to this first end, this second end of conducting is to the binding of the 3rd end.
25. amplifier installation as claimed in claim 24, wherein this first transistor is a P-type mos transistor, and this first end is a grid, and this second end is a source electrode, and the 3rd end is drain electrode.
26. amplifier installation as claimed in claim 24, wherein this transistor seconds is a N type metal oxide semiconductor transistor, and this first end is a grid, and this second end is drain electrode, and the 3rd end is a source electrode.
27. amplifier installation as claimed in claim 23, wherein this commutation circuit includes:
One first switch includes this first output that one first end is coupled to this input stage circuit, and one second end is coupled to this first input end of this output-stage circuit;
One second switch includes this second input that one first end is coupled to this input stage circuit, and one second end is coupled between this feedback voltage output and this output of this output-stage circuit;
One the 3rd switch includes this second output that one first end is coupled to this input stage circuit, and one second end is coupled to this second input of this output-stage circuit;
One the 4th switch includes this first output that one first end is coupled to this input stage circuit, and one second end is coupled to this first input end of this dummy output level circuit;
One the 5th switch includes this second input that one first end is coupled to this input stage circuit, and one second end is coupled to this feedback voltage output of this dummy output level circuit; And
One the 6th switch includes this second output that one first end is coupled to this input stage circuit, and one second end is coupled to this second input of this dummy output level circuit.
28. amplifier installation as claimed in claim 27, wherein when this operator scheme is the offset voltage storage mode, this second switch of this of this commutation circuit first switch, this commutation circuit and the 3rd switch of this commutation circuit are closed, the 6th switch conduction of the 4th switch of this commutation circuit, the 5th switch of this commutation circuit and this commutation circuit.
29. amplifier installation as claimed in claim 27, wherein when this operator scheme is offset voltage elimination pattern, this second switch of this of this commutation circuit first switch, this commutation circuit and the 3rd switch conduction of this commutation circuit, the 6th switch of the 4th switch of this commutation circuit, the 5th switch of this commutation circuit and this commutation circuit cuts out.
30. amplifier installation as claimed in claim 27, wherein the 4th switch of this of this commutation circuit first switch and this commutation circuit is realized with a selector.
31. amplifier installation as claimed in claim 27, wherein the 5th switch of this second switch of this commutation circuit and this commutation circuit is realized with a selector.
32. amplifier installation as claimed in claim 27, wherein the 6th switch of the 3rd switch of this commutation circuit and this commutation circuit is realized with a selector.
33. amplifier installation as claimed in claim 1, it also comprises a bleeder circuit, is coupled between this output-stage circuit and this commutation circuit, is used for adjusting the gain of this amplification voltage corresponding to this input voltage.
34. amplifier installation as claimed in claim 33, wherein this bleeder circuit includes:
One first resistance is coupled between this output-stage circuit and this commutation circuit; And
One second resistance, one end are coupled between this first resistance and this commutation circuit, and the other end is coupled to a ground end.
35. amplifier installation as claimed in claim 1, wherein this amplification voltage is 1 corresponding to the gain of this input voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101028362A CN101304237B (en) | 2007-05-09 | 2007-05-09 | Amplifier apparatus capable of eliminating migration voltage |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101028362A CN101304237B (en) | 2007-05-09 | 2007-05-09 | Amplifier apparatus capable of eliminating migration voltage |
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| CN101304237A CN101304237A (en) | 2008-11-12 |
| CN101304237B true CN101304237B (en) | 2011-02-02 |
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| CN2007101028362A Expired - Fee Related CN101304237B (en) | 2007-05-09 | 2007-05-09 | Amplifier apparatus capable of eliminating migration voltage |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103974487B (en) * | 2013-01-24 | 2016-05-25 | 普诚科技股份有限公司 | Light emitting diode drive device |
| CN105636307B (en) * | 2014-11-28 | 2019-06-21 | 昱京能源科技股份有限公司 | The offset voltage of dimming device protection mechanism eliminates circuit structure |
| US10601383B2 (en) * | 2018-08-20 | 2020-03-24 | Pixart Imaging Inc. | Amplifier circuit and transimpedance amplifier circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4306196A (en) * | 1980-01-14 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Operational amplifier with offset compensation |
| CN1189011A (en) * | 1996-11-20 | 1998-07-29 | 日本电气株式会社 | DC-offset canceler circuit and method for using the circuit |
| CN1441547A (en) * | 2002-02-25 | 2003-09-10 | 日本电气株式会社 | Differential circuit, amplifying circuit, driving circuit and display device using them |
| CN1520032A (en) * | 2003-01-20 | 2004-08-11 | 矽统科技股份有限公司 | Circuit of cancelling DC offset applied to variable gain amplifier |
| CN1604464A (en) * | 2003-10-01 | 2005-04-06 | 日本电气株式会社 | Differential amplifier circuit and drive circuit of liquid crystal display unit using the same |
| US20060255856A1 (en) * | 2005-05-16 | 2006-11-16 | Nec Electronics Corporation | Operational amplifier with less offset voltage |
| US20070085608A1 (en) * | 2005-09-27 | 2007-04-19 | Nec Corporation | Differential amplifier, digital-to-analog converter, and display device |
-
2007
- 2007-05-09 CN CN2007101028362A patent/CN101304237B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4306196A (en) * | 1980-01-14 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Operational amplifier with offset compensation |
| CN1189011A (en) * | 1996-11-20 | 1998-07-29 | 日本电气株式会社 | DC-offset canceler circuit and method for using the circuit |
| CN1441547A (en) * | 2002-02-25 | 2003-09-10 | 日本电气株式会社 | Differential circuit, amplifying circuit, driving circuit and display device using them |
| CN1520032A (en) * | 2003-01-20 | 2004-08-11 | 矽统科技股份有限公司 | Circuit of cancelling DC offset applied to variable gain amplifier |
| CN1604464A (en) * | 2003-10-01 | 2005-04-06 | 日本电气株式会社 | Differential amplifier circuit and drive circuit of liquid crystal display unit using the same |
| US20060255856A1 (en) * | 2005-05-16 | 2006-11-16 | Nec Electronics Corporation | Operational amplifier with less offset voltage |
| US20070085608A1 (en) * | 2005-09-27 | 2007-04-19 | Nec Corporation | Differential amplifier, digital-to-analog converter, and display device |
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| Publication number | Publication date |
|---|---|
| CN101304237A (en) | 2008-11-12 |
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