CN101286451A

CN101286451A - High voltage device manufacture method by deep sub-micron technique

Info

Publication number: CN101286451A
Application number: CNA2007100394376A
Authority: CN
Inventors: 高荣正
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-04-12
Filing date: 2007-04-12
Publication date: 2008-10-15
Anticipated expiration: 2027-04-12
Also published as: CN100570839C

Abstract

The invention relates to a method for producing a high-voltage device by using deep submicron technique; a patterned metal silicide layer is arranged on a high concentration ion area (a first ion area and a second ion area) and gate structure; the horizontal width of patterned metal silicide layer positioned on the first ion area and the second ion area is less than the horizontal width of the first ion area and the second ion area; the gate structure can retain the original characteristic of high breakdown voltage; the patterned metal silicide arranged on the first ion area and the second ion area of the gate structure can reduce the contact resistance when in connection with an external conductive layer and increase the adhesiveness with the silicon substrate.

Description

Utilize deep sub-micron technique to make the method for high voltage device

Technical field

The present invention relates to a kind of method of utilizing deep sub-micron technique to make high voltage device, be the manufacture method of adding the pattern metal silicide in a kind of MOS modular construction, particularly a kind of a kind of manufacture method of the horizontal width limit horizontal width in the high concentration ion district in source/drain electrode in the pattern metal silicide less than the MOS modular construction.

Background technology

The effort the earliest of drain electrode engineering is to use a technology that is called double-diffused drain electrode, and in this technology, phosphorus and arsenic are all implanted in the substrate to form source electrode and drain diffusion.Because the diffusion of phosphorus is fast than arsenic, the distribution at edge mainly is a phosphorus usually, and the face that connects is unlikely to too steep.Because side diffusion is, will expand similar graded profile under the gate electrode.Then develop and the side direction double-diffused drain electrode.Utilize the method can reduce the electric field kurtosis more than 20%.

Existing high voltage grid structure is in the source/drain electrode of stack both sides, produce again one compared to the source/zone that the drain region ion concentration is higher, this grid structure has good performance aspect the voltage bearing, but the direct-connected conductive layer that connects other on source/drain region, as aluminium, copper etc., the material of conductive layer is to being that the adhesive force of substrate is not good with silicon, contact resistance between the two is not low yet, even if in order to reduce the touch voltage between conductive layer and the substrate, employing is aimed at metal silicide technology voluntarily and is reduced contact resistance, but can cause the problem of electric leakage (leakage) because of the composition surface between clearance wall (spacer) and pattern metal silicide (Salicide).

For solving the above-mentioned problem of prior art, the present invention proposes a kind of method of utilizing deep sub-micron technique to make high voltage device: making one earlier has the substrate of semiconductor subassembly, after making grid structure and clearance wall on the substrate; Establish metal level on the substrate after making, and add one group of patterned mask on metal level, patterned mask is positioned at the high concentration ion zone position top of grid structure top, source/drain electrode, its horizontal width of patterning photoresist of high concentration ion zone position top in source/drain electrode is respectively less than the horizontal width of the interior high concentration ion zone position of source/drain electrode, organize the patterning photoresist with this metal level is carried out etching, carry out tempering after the etching, and add solvent unreacted metal is removed, finish structure of the present invention; Compared to prior art, structure of the present invention can be born higher contact resistance and be kept puncture voltage.

Summary of the invention

Main purpose of the present invention is, a kind of method of utilizing deep sub-micron technique to make high voltage device is provided, its control patterning metal silicide layer is positioned at the high concentration ion zone position of source/drain electrode, more can reduce contact resistance compared to prior art, keeps the puncture voltage of grid structure.

For reaching above-mentioned purpose, semi-conductive high voltage configuration and the manufacture method thereof of being applicable to of the present invention is in adding one group of patterning photoresist behind the depositing metal layers on metal level, with be not patterned metal level that the photoresist mask covers in addition etching remove, again via the tempering of heating, make the metal level below be reacted into the pattern metal silicide layer, add removal of solvents unreacted metal layer again with silicon substrate; The pattern metal silicide layer is positioned on the grid structure, the high concentration ion zone position of source/drain electrode, compared to prior art pattern metal silicide layer be positioned on the grid structure, whole source/drain electrode, the present invention more can reduce contact resistance and keep the puncture voltage of grid structure.

Further specify the present invention below in conjunction with drawings and Examples.

Description of drawings

Fig. 1 (a) is that preferred embodiment of the present invention is at each step structure cutaway view of making the MOS assembly to Fig. 1 (l).

Fig. 2 is the embodiment of the present invention flow chart.

Label declaration

10 substrates

The 20STI zone

30 grid oxic horizons

40 polysilicon layers

50 source electrodes

60 drain electrodes

70 first ion districts

80 second ion districts

90 dielectric layers

95 clearance walls

100 patterning photoresist coatings

110 metal levels

The patterning photoresist coating of 120 Fig. 1

130 pattern metal pattern metal silicide pattern metal silicide layers

Embodiment

Fig. 1 (a) is preferred embodiment of the present invention each step structure cutaway view at making MOS assembly to Fig. 1 (l), and Fig. 2 is the embodiment of the present invention flow chart.Please be simultaneously with reference to Fig. 1 and Fig. 2.

At first, carry out step S10, provide and have semiconductor subassembly substrate 10, shown in Fig. 1 (a), had sti region 20, grid structure (forming) in the substrate 10 by grid oxic horizon 30 and polysilicon layer 40, the first ion district 70 and the second ion district 80 arranged in the source/drain electrode of grid structure (50 and 60) and the source/drain electrode (50 and 60) respectively, the ion concentration in the first ion district 70 and the second ion district 80 than source/drain electrode (50 and 60) height, the first ion district 70 and the second ion district, 80 vertical depths do not run through the vertical height of source/drain electrode (50 and 60).

Carry out step S20 again, please refer to Fig. 1 (b), dielectric layer 90 in the substrate 10 after finishing S10, the mode of deposition are the low-pressure chemical vapor deposition technology, and the compound that the material of dielectric layer 90 can select for use silicon dioxide, silicon nitride or silicon dioxide to add silicon nitride is formed; Carry out step S30 afterwards, please refer to Fig. 1 (c),, establish patterning photoresist coating 100, before establishing patterning photoresist coating 100, also can do the technology of an etching earlier, remove the dielectric layer 90 of part in the grid structure top; Then carry out step S40, please refer to Fig. 1 (d), is that mask carries out etching to this dielectric layer 90 with patterning photoresist coating 100, and the mode of etching can adopt the ion etching of dry type anisotropic, after etching finishes, this dielectric layer 90 will become the gap ancient piece of jade, round, flat and with a hole in its centre (spacer) of grid structure both sides.

Then carry out step S50 and S60, please refer to Fig. 1 (e) and Fig. 1 (f), patterning photoresist coating 100 is removed, and residual dielectric layer 90 on the polysilicon layer 40 is removed, allow polysilicon layer 40 expose; Then carry out step S70, please refer to Fig. 1 (g), depositing metal layers 110 in whole grid structure and substrate 10, the mode of deposition can be selected the low-pressure chemical vapor deposition technology for use; Carry out step S80, S90 and S100 then, please refer to Fig. 1 (h), Fig. 1 (i) and Fig. 1 (j), after above grid oxic horizon 30, the first ion district 70 and the second ion district 80 Fig. 1 case photoresist coating 120 being set, patterning photoresist coating 120 with Fig. 1 is that mask carries out dry etching and wet etching to pattern metal silicide layer 130, after etching finishes patterning photoresist coating 120 is removed.After the etching only in the first ion district 70, stay metal level 110 in the second ion district 80 with on the gate structure, wherein be positioned in the first ion district 70 and the second ion district 80 on the horizontal width of metal level 110 less than the horizontal width of grid structure source/drain electrode (50 and 60).

Carry out step S110 again, please refer to Fig. 1 (k), the tempering of heating in the boiler tube is delivered in the whole substrate 10 of finishing above-mentioned steps, the metal of the below of metal level 110 will become pattern metal silicide layer 130 with the pasc reaction in the substrate 10, and the top of metal level 110 then is to keep original metal level 110 to form; At last, carry out step S120, please refer to Fig. 1 (l), add solvent will be not with substrate 10 on the metal level 110 of silicon atom reaction remove, only stay pattern metal silicide layer 130, finish the manufacturing of high voltage grid structure.Pattern metal silicide layer 130 can reduce the contact resistance when being connected with outer conductive layers, increase the absorption affinity of outer conductive layers and grid structure and source/drain electrode (50 and 60) thereof, again because of pattern metal silicide layer 130 does not contact with clearance wall 95, the problem of leakage current and can keep puncture voltage.

Above-described embodiment only is used to illustrate technological thought of the present invention and characteristics, its purpose makes those skilled in the art can understand content of the present invention and is implementing according to this, when can not only limiting claim of the present invention with present embodiment, be all equal variation or modifications of doing according to disclosed spirit, still drop in the claim of the present invention.

Claims

1, a kind of deep sub-micron technique that utilizes is made high-tension device, it is characterized in that comprising the following steps:

One substrate is provided, this substrate comprises, one grid structure, be positioned on this substrate, this grid structure from bottom to top is made up of a grid oxic horizon and a polysilicon layer successively, there is one source/drain region these grid structure both sides, and one first ion doped region and one second ion doped region are arranged respectively in this source/drain region, and this first ion doped region and this second ion doped region do not run through this source/drain region;

Deposit a dielectric layer on this grid structure;

With a dry type anisotropic etching mode this dielectric layer is carried out the clearance wall etching and form grid gap wall;

Form a pattern metal pattern metal silicide layer on this first ion doped region and this second ion doped region, the horizontal width of this patterned metal layer is less than the horizontal width of this first ion doped region and this second ion doped region.

2, the deep sub-micron technique that utilizes according to claim 1 is made high-tension device, it is characterized in that: this first ion doped region and this second ion doped region are that same ion is mixed.

3, the deep sub-micron technique that utilizes according to claim 1 is made high-tension device, it is characterized in that: this first ion doped region and this second ion doping fauna P ⁺Type ion doping or N-type ion doping.

4, the deep sub-micron technique that utilizes according to claim 1 is made high-tension device, it is characterized in that: being patterned as by a patterning photoresist coating that this pattern metal pattern metal silicide layer forms forms.

5, the deep sub-micron technique that utilizes according to claim 1 is made high-tension device, it is characterized in that: the patterning that this pattern metal pattern metal silicide layer forms the etching technics of process be a dry etching and a wet etching.

6, a kind of structure of MOS assembly comprises the substrate with semiconductor subassembly, it is characterized in that this substrate comprises:

One grid structure from bottom to top is made up of a grid oxic horizon and a polysilicon layer successively;

Source/the drain region of this grid structure is positioned at the both sides of this grid structure, and one first ion doped region and one second ion doped region lay respectively within the source/drain electrode of this grid structure;

One pattern metal pattern metal silicide layer, be positioned on this grid structure, this first ion doped region and this second ion doped region, be positioned at this its horizontal width of pattern metal pattern metal silicide layer on this first ion doped region and this second ion doped region less than this first ion doped region and this second ion doped region, reduce grid structure and source/drain electrode and outside contact resistance that is connected and the puncture voltage that continues to keep grid structure by this pattern metal pattern metal silicide layer.

7, the structure of MOS assembly according to claim 6 is characterized in that: this first ion doped region and this second ion doped region are that same ion is mixed.

8, the structure of MOS assembly according to claim 6 is characterized in that: this first ion doped region and this second ion doping fauna P ⁺Type ion doping or N ^-The type ion doping.

9, the structure of MOS assembly according to claim 6 is characterized in that: the patterning that this pattern metal pattern metal silicide layer forms is to form by a patterning photoresist coating.

10, the structure of MOS assembly according to claim 6 is characterized in that: the patterning that this pattern metal pattern metal silicide layer forms the etching technics of process be a dry etching and a wet etching.