CN101282114A - TTL and CMOS compatible input buffer - Google Patents

Abstract

A TTL and CMOS compatible type input buffer comprises a reference voltage generator and an input buffer which comprises at least one stage input invertor which include a PMOS tube P1 and an NMOS tube N2, the grids of which are connected as an input end for inputting signal Vin, a source pole of the PMOS tube P1 is connected with a reference voltage VREF provided by the reference voltage generator; when the circuit works in the TTL mode, the reference voltage generator provides reference voltage VREF for the input invertor between 3.3 and 3.5 V, the turning point voltage of the input invertor is 1.4 V to make input noise margin maximum; when the circuit works in the CMOS mode, the reference voltage generator has no quiescent power dissipation, the reference voltage generator provides reference voltage VREF for the input invertor between 4.6 and 5 V, the turning point voltage of the input invertor is 2.5 V to obtain the maximum noise margin.

Description

A kind of TTL and CMOS compatible input buffer

Technical field

The present invention relates to a kind of input buffer, particularly a kind of TTL and CMOS compatible input buffer.

Background technology

Bipolar integrated circuit is operated in low logic voltage.Usually the logical zero of TTL logical circuit is between 0.0-0.8V, and logical one is between 2.0-5.0V.Therefore, for can identification 0 and 1, be operated in certain some upset that CMOS inverter under the TTL pattern must be between 0.8V and 2.0V, preferably near 1.4V, so that maximum noise margin is provided.And the CMOS inverter is usually operated at 4.5-15V, and representative value is 5V.If the source electrode of PMOS pipe is connected to the supply voltage VCC of a 5V in the CMOS inverter like this, and when connecing TTL logical one (2V) on its grid, the PMOS pipe just can't effectively end, and PMOS pipe and NMOS pipe are in the while conducting state, thereby the generation steady state short circuit current, the power consumption of increase circuit.Therefore for the CMOS input inverter in the CMOS input buffer that can receive the TTL incoming level 2 requirements are arranged: one, the overturn point voltage of inverter will be near 1.4V, so that the maximum noise tolerance limit to be provided; Two, the source electrode of PMOS pipe can not be directly connected on the supply voltage VCC (5V) in the inverter, need connect on the voltage that is lower than 5V, to reduce quiescent dissipation.

At second above-mentioned requirement several solutions have been arranged.A kind of scheme is that the source electrode for PMOS in the CMOS input inverter provides a reference voltage, the voltage that this reference voltage is lower than TTL logical one (2V) deducts the threshold voltage of PMOS pipe, thereby realizing a TTL signal is driven is cmos signal, and makes that this CMOS input inverter power consumption when quiescent operation is very low.Second kind of scheme is similar to first kind, all be that source electrode to PMOS pipe in the CMOS input inverter provides a reference voltage, but this reference voltage can change with the TTL input signal, and the same with first kind of scheme, the quiescent dissipation when the CMOS inverter is operated in the TTL pattern is very low.Also have a kind of design in addition,, guaranteed that the overturn point of input inverter is in a value that " relatively " is stable, but this value is easy to be subjected to the influence of technological parameter by the bulk effect of compensation transistor.

At first point, promptly make the overturn point of the CMOS input inverter in the CMOS input buffer be in this problem of accurate preset value, have in the previous research and adopt special process to solve, but this solution needs special technology device, has the problem that increases production cost.Certainly, if the supply voltage of hypothesis CMOS input inverter is in a stable value always, can be by recently rough overturn point of setting of length and width of NMOS pipe and PMOS pipe in the adjustment inverter.But in fact, the overturn point set of this solution is easy to be subjected to the influence of technology and mains voltage variations and changes.

Summary of the invention

Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, provide a kind of low cost, low-power consumption, noise margin is big, high frequency performance good, TTL and CMOS compatible input buffer easy and simple to handle.

Technical solution of the present invention is: a kind of TTL and CMOS compatible input buffer, it is characterized in that comprising: reference voltage generator and input buffer, input buffer comprises one-level input inverter at least, input inverter comprises PMOS pipe P1 and NMOS pipe N2, PMOS pipe P1 links to each other as the input of input signal Vin with the grid of NMOS pipe N2, and the source electrode of PMOS pipe P1 meets the reference voltage VREF that reference voltage generator provides; When circuit working during at the TTL input pattern, reference voltage generator offers the reference voltage VREF of input inverter between 3.3～3.5V, and the overturn point voltage of input inverter is 1.4V, makes input noise tolerance limit maximum; When circuit working during at the CMOS input pattern, reference voltage generator offers the reference voltage VREF of input inverter between 4.6～5V, and the overturn point voltage of input inverter is 2.5V, to obtain the maximum noise tolerance limit.

Described reference voltage generator comprises resistance pressure-dividing network, manages P21 with reference to input buffer, operational amplifier and PMOS; Resistance pressure-dividing network produces reference voltage VREF1 and is connected to the reverse input end of operational amplifier, produce reference voltage VREF2 and be connected to the input in the same way of operational amplifier with reference to input buffer, the grid of the output control PMOS pipe P21 of operational amplifier, make the drain electrode of PMOS pipe P21 provide reference voltage VREF for the input inverter in the input buffer, the source electrode of PMOS pipe P21 meets reference potential VCC.

Describedly comprise PMOS pipe P22 and NMOS pipe N23 with reference to input buffer, the grid of the grid of PMOS pipe P22, drain electrode and NMOS pipe N23, the input in the same way that drain electrode all is connected to operational amplifier, the source ground of NMOS pipe N23, the source electrode of NMOS pipe N23 links to each other with the drain electrode of PMOS pipe P21.

Described operational amplifier comprises PMOS pipe P41, P43, P44, P45 and P51, and NMOS manages N42, N46, N47, N48 and N52, and capacitor C50; The source electrode of PMOS pipe P41 meets reference potential VCC, the continuous drain electrode of NMOS pipe N42 and the grid of PMOS pipe P43 of being connected to jointly of drain and gate; The source ground of NMOS pipe N42, grid connects the non-signal of mode control signal; The grid of PMOS pipe P44 is as the reverse input end of operational amplifier, the grid of PMOS pipe P45 is as the positive input of operational amplifier, the source electrode of PMOS pipe P44 and PMOS pipe P45 links to each other and is connected to the drain electrode of PMOS pipe P43 jointly, and the source electrode of PMOS pipe P43 meets reference potential VCC; The grid of NMOS pipe N46 and NMOS pipe N47 links to each other and is connected to the drain electrode that PMOS manages P44, the drain electrode of NMOS pipe N46 links to each other with the drain electrode of PMOS pipe P44, the drain electrode of NMOS pipe N47 links to each other with the drain electrode of PMOS pipe P45 and is connected to the source electrode that NMOS manages N48, the source grounding of NMOS pipe N46 and NMOS pipe N47; The grid of NMOS pipe N48 meets reference potential VCC, and drain electrode links to each other the output of another termination operational amplifier of capacitor C50 with the end of capacitor C50; The grid of PMOS pipe P51 links to each other with the grid of PMOS pipe P43, and drain electrode links to each other with the drain electrode of NMOS pipe N52 and the output of operational amplifier, and source electrode meets reference potential VCC; The source ground of NMOS pipe N52, grid links to each other with the source electrode of NMOS pipe N48.

Described input buffer comprises input inverter, second level input inverter and third level input inverter; Input inverter receives outside input signal, adjusts self overturn point according to the difference of signal type, for input signal provides maximum noise margin; Second level input inverter receives the output signal of input inverter, produces a low level and be 0, high value is the output signal of VCC-VTH, generation dc power when avoiding receiving the TTL input signal.Third level input inverter receives the output signal of second level input inverter, and the value VCC-VTH of input high level is compensated to reference potential VCC.

Described second level input inverter comprises PMOS pipe P13, P15 and NMOS pipe N14, the grid of NMOS pipe N14 links to each other as the input of second level input inverter with the grid of PMOS pipe P13, the drain electrode of NMOS pipe N14 links to each other as the output of second level input inverter with the drain electrode of PMOS pipe P13, the source ground of NMOS pipe N14, the source electrode of PMOS pipe P13 links to each other with the drain and gate of PMOS pipe P15, and the source electrode of PMOS pipe P15 meets reference potential VCC.

Described third level input inverter comprises PMOS pipe P30, P32 and NMOS pipe N31, the grid of NMOS pipe N31 links to each other with the grid of PMOS pipe P30, input as third level input inverter, the drain electrode of NMOS pipe N31 links to each other as the output of third level input inverter with the drain electrode of PMOS pipe P30, the source ground of NMOS pipe N31, the source electrode of PMOS pipe P30 meets reference potential VCC; The grid of PMOS pipe P32 connects the output of third level input inverter, and drain electrode connects the input of third level input inverter, and source electrode meets reference potential VCC.

The present invention's advantage compared with prior art is:

(1) reference voltage that all adopts reference voltage generator to provide of the overturn point under two kinds of mode of operations of input buffer of the present invention is determined, overturn point is set according to the input noise tolerance limit, and the maximum noise tolerance limit can be provided;

(2) input buffer of the present invention is based on the CMOS standard technology, and not needing increases the special process mask, has saved the cost of chip manufacturing;

(3) input buffer of the present invention carries out pattern control by introducing mode control signal, and is easy and simple to handle;

(4) can adjust mutually between the reference voltage that the overturn point of input buffer of the present invention and reference voltage generator provide, can avoid the influence that changed by technological parameter and supply voltage;

(5) in the operational amplifier of input buffer of the present invention, introduce frequency compensation network, improved the open-loop frequency response of feedback amplifier, guaranteed under the prerequisite of certain gain margin, to obtain bigger open circuit gain;

(6) the speed height of input buffer of the present invention, under the TTL input pattern, have only very little dc power, under the CMOS pattern, do not have dc power.

Description of drawings

Fig. 1 is the circuit theory diagrams of TTL of the present invention and CMOS compatible input buffer;

Fig. 2 is the circuit diagram of operational amplifier in the reference voltage generator of TTL of the present invention and CMOS compatible input buffer;

Fig. 3 is the frequency response simulation result of operational amplifier output amplitude of the present invention;

Fig. 4 is the simulation result of each reference voltage of the reference voltage generator generation of TTL of the present invention and CMOS compatible input buffer;

Fig. 5 is operated in circuit simulation result under the TTL pattern for TTL of the present invention and CMOS compatible input buffer.

Embodiment

As shown in Figure 1, schematic block circuit diagram for TTL of the present invention and CMOS compatible input buffer, comprise reference voltage generator 3 and input buffer 4, reference voltage generator 3 comprises resistance pressure-dividing network 24, with reference to input buffer 25 and operational amplifier 26, input buffer 4 comprises input inverter 5, second level input inverter 6 and third level input inverter 7.

Used metal-oxide-semiconductor is enhancement device among the present invention.

Input inverter 5 in the input buffer 4 is made up of PMOS pipe P1 and NMOS pipe N2, the grid of PMOS pipe P1 links to each other with the grid of NMOS pipe N2, input as input inverter 5, the drain electrode of PMOS pipe P1 links to each other with the drain electrode of NMOS pipe N2, output as input inverter 5, the source electrode of NMOS pipe N2 links to each other with ground, and the source electrode of PMOS pipe P1 meets the output signal VREF of reference voltage generator 3.

When input inverter 5 is in the TTL pattern, signal on the input Vin is changed between TTL low level 0.8V and TTL high level 2.0V, if the source electrode of PMOS pipe P1 is directly connected on the supply voltage VCC (5V) and can produces quiescent dissipation in the inverter, therefore provide a reference voltage VREF about 3.5V source electrode by reference voltage generator 3, thereby reduce quiescent dissipation to PMOS pipe P1.

To equal the voltage at output voltage point place be the overturn point voltage of inverter to input voltage in the transfer characteristic curve of inverter, and in order to make the noise margin maximum of input inverter 5, its overturn point voltage preferably is in the median (about 1.4V) of TTL logic level.In fact, the overturn point magnitude of voltage of input inverter 5 depends on the breadth length ratio of PMOS pipe P1, NMOS pipe N2, and the size that is added to the reference voltage VREF of PMOS pipe P1 source electrode.The supply voltage VCC of a 5V directly is provided with respect to the source electrode to PMOS pipe P1, provide a reference voltage VREF who is about 3.5V by reference voltage generator 3 to it among the present invention, even be in the median of TTL logic level like this for the overturn point voltage of adjusting input inverter 5, ratio between the breadth length ratio of the breadth length ratio of PMOS pipe P1 and NMOS pipe N2, i.e. (W/L) _PMOS/ (W/L) _NMOSCan be not too small yet, can not influence the reversal rate of inverter.

When input inverter 5 is in the CMOS pattern, the signal of input Vin changes between low level 0 and high level VCC (5V), this moment, the output VREF of reference voltage generator 3 equaled VCC (5V), the overturn point voltage of input inverter 5 is lifted to about 2.5V, guarantees that the input noise tolerance limit of input inverter under the CMOS pattern is enough big.

In the reference voltage generator 3, the grid that starts to control the PMOS pipe P17 that makes usefulness connects the EN mode control signal, and source electrode meets VCC, and drain electrode links to each other with an end of resistance R 18 in the resistance pressure-dividing network 24, the other end of resistance R 18 links to each other at node VREF1 place with resistance R 19, the other end ground connection of resistance R 19.Ratio between resistance R 18 and the resistance R 19 should be set at the overturn point voltage that the voltage that makes node VREF1 place equals input inverter 5.Form by PMOS pipe P22 and NMOS pipe N23 with reference to input buffer 25.The reverse input end of operational amplifier 26 and node VREF1 join, positive input with join the grid of the output of operational amplifier 26 control PMOS pipe P21 with reference to the node VREF2 in the input buffer 25.PMOS pipe P21 adjusts pipe, and size is very big, and its source end and VCC join, and drain electrode is joined with the source electrode that PMOS manages P22.

As shown in Figure 2, form structure chart for the circuit of operational amplifier 26.EN is a mode select signal among the figure, and TTL and COMS compatible input buffer are operated in the TTL pattern when EN=0, be operated in the CMOS pattern during EN=1.Operational amplifier 26 contains biasing circuit 55, first order amplifier 56, second level amplifier 57, compensating circuit 59 and some control circuits.Biasing circuit 55 is made up of PMOS pipe P41 and NMOS pipe N42, the source electrode of PMOS pipe P41 meets supply voltage VCC (5V), drain and gate connects the drain electrode of NMOS pipe N42, the source ground of NMOS pipe N42, the output of grid and inverter 54 joins, and the breadth length ratio of the breadth length ratio of the PMOS pipe P41 here/NMOS pipe N42 is very big.Like this, though NMOS pipe N42 conducting, biasing circuit 55 also can produce one a little less than but near VCC-|VTH, the bias voltage of PMOS pipe P41| is for the grid of tail current source P43 provides a suitable operating voltage.

First order amplifier 56 is made up of PMOS pipe P44, P45 and NMOS pipe N46, N47, the source electrode of PMOS pipe P44 and P45 links to each other with the drain electrode of current source PMOS pipe P43, the grid of PMOS pipe P45 is the positive input of operational amplifier 26, the grid of PMOS pipe P44 is the reverse input end of operational amplifier 26, the drain electrode of PMOS pipe P44 links to each other with the grid of the drain electrode of NMOS pipe N46, grid and NMOS pipe N47, the drain electrode of the drain electrode of PMOS pipe P45 and NMOS pipe N47 is connected in node H, as the output of first order amplifier 56, the source ground of NMOS pipe N47.Second level amplifier 57 comprises PMOS pipe P51 and NMOS pipe N52, the source electrode of PMOS pipe P51 meets supply voltage VCC, the grid of grid and NMOS pipe N43 is connected to the A point, drain electrode is connected to the G point with the drain electrode of NMOS pipe N52, the grid of NMOS pipe N52 is connected to the output of first order amplifier 56, be the H point, source ground.Frequency compensated circuit 59 comprises NMOS pipe N48 and capacitor C50, the grid of NMOS pipe N48 meets supply voltage VCC, be used to provide a channel resistance, its source electrode connects the output H point of first order amplifier 56, the end of drain electrode and capacitor C50 joins, and the output G point of the other end of capacitor C50 and second level amplifier 57 joins.

Input buffer 4 comprises input inverter 5, second level input inverter 6 and third level input inverter 7.Input inverter 5 is made up of PMOS pipe P1 and NMOS pipe N2.Second level input inverter 6 is made up of PMOS pipe P13, P15 and NMOS pipe N14, the grid of PMOS pipe P13 links to each other with the grid of NMOS pipe N14, and link to each other with the output node D of input inverter 5 simultaneously, as the input of second level input inverter 6, the drain electrode of PMOS pipe P13 links to each other as the output of second level input inverter 6 with the drain electrode of NMOS pipe N14; PMOS pipe P15 plays the voltage clamp position, and its source electrode meets supply voltage VCC (5V), and grid links to each other with drain electrode and receives the source electrode that PMOS manages P13.Third level input inverter 7 is made up of PMOS pipe P30, P32 and NMOS pipe N31, the source ground of NMOS pipe N31, grid links to each other as the input of third level input inverter 7 with the grid of PMOS pipe P30, drain electrode links to each other as the output end vo ut of third level input inverter 7 with PMOS pipe P30 drain electrode, the source electrode of PMOS pipe P30 meets supply voltage VCC (5V), PMOS pipe P32 plays the voltage feedback effect, its drain electrode links to each other with the input of third level input inverter 7, grid links to each other with the output of third level input inverter 7, and source electrode links to each other with supply voltage VCC.

Among Fig. 2, PMOS pipe P40, NMOS pipe N49, NMOS pipe N53 and inverter 54 are logic control circuit.The grid of the grid of NMOS pipe N49, NMOS pipe N53 and the input termination mode control signal EN of inverter 54, wherein NMOS manages the source ground of N49, the output of drain electrode and first order amplifier 56, promptly node H connects; The source ground of NMOS pipe N53, the output of drain electrode and operational amplifier, promptly node G connects; Output signal/the EN of inverter 54 receives the grid of PMOS pipe P40, and the source electrode of PMOS pipe P40 meets supply voltage VCC, and drain electrode connects the grid of PMOS pipe P41 in the biasing circuit 55.

When the EN signal when low, TTL and CMOS compatible input buffer are in the TTL pattern ,/EN signal be a height, NMOS pipe N49, N53 and PMOS pipe P40 all end, and the grid of NMOS pipe N42 connects high level, and biasing circuit 55 is started working, and operational amplifier 26 is also worked.PMOS among Fig. 2 pipe P17 conducting, resistance pressure-dividing network 24 work produce the first reference voltage VREF1, and this voltage and the input inverter 5 overturn point magnitude of voltage when the TTL mode of operation equates the reverse input end of while input operational amplifier 26; Produce the positive input of VREF2 voltage input operational amplifier 26 with reference to input buffer 25; Because VREF1 and VREF2 are respectively the forward and the reverse input end voltage of operational amplifier 26, according to ' empty short ' phenomenon of operational amplifier, VREF1 equates with VREF2 voltage.The source voltage of PMOS pipe P1 and equal in the input inverter 5 with reference to the source voltage of the pipe of the PMOS in the input buffer 25 P22, and (W/L) PMOS (P11)=(W/L) PMOS (P22), (W/L) NMOS (P12)=(W/L) NMOS (N23), the overturn point voltage of input inverter 5 equates with predefined overturn point voltage like this, the breadth length ratio of adjusting pipe PMOS pipe P21 is very big, transient current in the time of can providing upset for reference input buffer 25 and input inverter 5, and compare less with reference to input buffer 25 needed electric currents when stablizing, so the gate bias of PMOS pipe P21 compares VCC-|VTH at one, PMOS (P21) | slightly little voltage, when input inverter 5 upsets, transient current flows through PMOS pipe P1 and NMOS pipe N2, the VREF voltage at node B place reduces, VREF2 voltage also reduces thereupon, the output of corresponding operational amplifier 26 also reduces, and the further conducting of PMOS pipe P21 meeting equates thereby VREF2 voltage is returned to VREF1 voltage for node B charging.Capacitor C8 is connected to the node B in the reference voltage generator 3, can provide a transient current for it when input inverter 5 upsets, improves the stability of reference voltage.Capacitor C20 is connected between the first reference voltage VREF1 and the ground, the smoothly electric source disturbance little interference that may cause.

EN=0 during the TTL mode of operation, EN=0 equals supply voltage VCC through inverter 54 generation/EN signals in Fig. 2, the grid that is added to PMOS pipe P40 ends it, the grid that is added to NMOS pipe N42 makes its conducting, biasing circuit 55 is started working, for operational amplifier 26 provides stable current offset, NMOS pipe N42 in the biasing circuit 55 is for falling than pipe, and (W/L) PMOS (P41)/(W/L) NMOS (N42) is very big, even NMOS pipe N42 conducting like this, biasing circuit 55 also can produce one and approach VCC-|VTH, PMOS (P41) | bias voltage.Bias point A is VCC-|VTH for the voltage that the grid of PMOS pipe P43 and PMOS pipe P51 provides, PMOS (P41) |.Because node A place voltage descends, PMOS pipe P43 and P51 conducting, operational amplifier 26 is started working.Operational amplifier 26 is for guaranteeing gain greater than 50dB, and unity gain bandwidth adopts and is with frequency compensated two-layer configuration greater than 100MHz.The gain A V1 of first order amplifier 56 is:

${\mathrm{<figure-callout\; id="1"\; label="A\; V"\; filenames="A20081011242000161.png,A20081011242000171.png"\; state="\{\{state\}\}">A</figure-callout>}}_V=\frac{{-2g}_{\mathrm{mpmos}\left(44\right)}}{I_{\mathrm{pmos}\left(43\right)}({\mathrm{\&lambda;}}_{\mathrm{pmos}\left(45\right)}+{\mathrm{\&lambda;}}_{\mathrm{nmos}\left(47\right)})}$

The gain A V2 of second level amplifier 57 is:

$A_{\mathrm{<figure-callout\; id="2"\; label="V"\; filenames="A20081011242000171.png"\; state="\{\{state\}\}">V</figure-callout>}2}=\frac{{-g}_{\mathrm{mnmos}\left(52\right)}}{I_{\mathrm{nmos}\left(52\right)}({\mathrm{\&lambda;}}_{\mathrm{nmos}\left(52\right)}+{\mathrm{\&lambda;}}_{\mathrm{Pmos}\left(51\right)})}$

Capacitor C50 is a miller compensation electric capacity, and capacitor C50 and NMOS pipe N48 can improve the high frequency stability of operational amplifier, and its gain bandwidth product GB is:

$\mathrm{GB}=\frac{g_{\mathrm{mPmos}\left(44\right)}}{C_{\left(50\right)}}$

Under 0.5 μ m standard CMOS process, carry out emulation, the output frequency response of operational amplifier 26 as shown in Figure 3, lateral coordinates is the frequency coordinate that has adopted logarithmic scale in this Bode diagram, along slope coordinate is that the common logarithm of amplifier gain modulus multiply by 20, by simulation result as can be known the gain of operational amplifier 26 be 54dB, unit bandwidth is 370MHz.

Pipe PMOS pipe P21 is adjusted in the output control of operational amplifier 26, make the reference voltage VREF at node B place can do suitable self adaptive adjustment, reach 3.5V, be in the median (about 1.4V) of TTL logic incoming level with the overturn point voltage that guarantees input inverter 5, and be not subjected to the influence of technological parameter change and electric source disturbance.Simulation result as shown in Figure 4, reference voltage VREF is 3.4V, VREF1 is about 1.382V, VREF2 is about 1.383V.

EN=1 during the CMOS mode of operation, be added to the grid of PMOS pipe P17 among Fig. 1, this moment, resistance pressure-dividing network 24 was closed, obtain after anti-phase by inverter among Fig. 2 54 simultaneously /the EN signal is a low level, make PMOS manage the P40 conducting, supply voltage VCC (5V) is added to PMOS pipe P40, P43, the grid of P51, biasing circuit 55, first order amplifier 56 and second level amplifier 57 are closed, EN is a high level, can manage N49 by NMOS simultaneously closes the pipe of the NMOS in the second level amplifier 57 N52, by NMOS pipe N53 the operational amplifier at node G place is exported VOUT and be changed to low level, the grid of PMOS pipe P21 in the low level control chart 1 at node G place, PMOS pipe P21 conducting, be delivered to node B with what supply voltage VCC (5V) had no loss, supply voltage VCC (5V) is added to the source electrode of PMOS pipe P1, and the overturn point voltage of input inverter 5 is lifted to 2.5V, has guaranteed that noise margin is enough big under the CMOS mode of operation.

The reason of such scheme is: when input buffer 4 is operated in the TTL pattern, input signal Vin overturns between 0.8V (low-voltage) and 2V (high voltage) with the TTL logical schema, reference voltage generator 3 offers reference voltage VREF near 3.5V of source electrode of PMOS pipe P1, can avoid the direct quiescent dissipation of introducing when linking to each other with VCC (5V) of source electrode of PMOS pipe P1 like this.This moment, the overturn point of input inverter 5 was the median (about 1.4V) of Transistor-Transistor Logic level, had optimum noise margin, and was not subjected to the influence of technological parameter change and electric source disturbance.Under the CMOS mode of operation, the input signal Vin of input inverter 5 overturns between 0V and supply voltage VCC (5V), equal VCC by the voltage that reference voltage generator 3 offers PMOS pipe P1 source electrode this moment, the overturn point voltage of input inverter 5 is lifted to 2.5V, has guaranteed that noise margin is enough big under the CMOS mode of operation.

The content that is not described in detail in the specification of the present invention belongs to those skilled in the art's known technology.

Claims (7)

1, a kind of TTL and CMOS compatible input buffer, it is characterized in that comprising: reference voltage generator (3) and input buffer (4), input buffer (4) comprises one-level input inverter (5) at least, input inverter (5) comprises PMOS pipe P1 and NMOS pipe N2, PMOS pipe P1 links to each other as the input of input signal Vin with the grid of NMOS pipe N2, and the source electrode of PMOS pipe P1 meets the reference voltage VREF that reference voltage generator (3) provides; When circuit working during at the TTL input pattern, reference voltage generator (3) offers the reference voltage VREF of input inverter (5) between 3.3～3.5V, and the overturn point voltage of input inverter (5) is 1.4V, makes input noise tolerance limit maximum; When circuit working during at the CMOS input pattern, reference voltage generator (3) offers the reference voltage VREF of input inverter (5) between 4.6～5V, and the overturn point voltage of input inverter (5) is 2.5V, to obtain the maximum noise tolerance limit.

2, a kind of TTL according to claim 1 and CMOS compatible input buffer is characterized in that: described reference voltage generator (3) comprises resistance pressure-dividing network (24), manages P21 with reference to input buffer (25), operational amplifier (26) and PMOS; Resistance pressure-dividing network (24) produces reference voltage VREF1 and is connected to the reverse input end of operational amplifier (26), produce reference voltage VREF2 and be connected to the input in the same way of operational amplifier (26) with reference to input buffer (25), the grid of the output control PMOS pipe P21 of operational amplifier (26), the drain electrode that makes PMOS manage P21 is that the input inverter (5) in the input buffer (4) provides reference voltage VREF, and the source electrode of PMOS pipe P21 meets reference potential VCC.

3, a kind of TTL according to claim 2 and CMOS compatible input buffer, it is characterized in that: describedly comprise PMOS pipe P22 and NMOS pipe N23 with reference to input buffer (25), the grid of the grid of PMOS pipe P22, drain electrode and NMOS pipe N23, the input in the same way that drain electrode all is connected to operational amplifier (26), the source ground of NMOS pipe N23, the source electrode of NMOS pipe N23 links to each other with the drain electrode of PMOS pipe P21.

4, a kind of TTL according to claim 2 and CMOS compatible input buffer, it is characterized in that: described operational amplifier (26) comprises PMOS pipe P41, P43, P44, P45 and P51, NMOS manages N42, N46, N47, N48 and N52, and capacitor C50; The source electrode of PMOS pipe P41 meets reference potential VCC, the continuous drain electrode of NMOS pipe N42 and the grid of PMOS pipe P43 of being connected to jointly of drain and gate; The source ground of NMOS pipe N42, grid connects the non-signal of mode control signal; The grid of PMOS pipe P44 is as the reverse input end of operational amplifier (26), the grid of PMOS pipe P45 is as the positive input of operational amplifier (26), the source electrode of PMOS pipe P44 and PMOS pipe P45 links to each other and is connected to the drain electrode of PMOS pipe P43 jointly, and the source electrode of PMOS pipe P43 meets reference potential VCC; The grid of NMOS pipe N46 and NMOS pipe N47 links to each other and is connected to the drain electrode that PMOS manages P44, the drain electrode of NMOS pipe N46 links to each other with the drain electrode of PMOS pipe P44, the drain electrode of NMOS pipe N47 links to each other with the drain electrode of PMOS pipe P45 and is connected to the source electrode that NMOS manages N48, the source grounding of NMOS pipe N46 and NMOS pipe N47; The grid of NMOS pipe N48 meets reference potential VCC, and drain electrode links to each other the output of another termination operational amplifier (26) of capacitor C50 with the end of capacitor C50; The grid of PMOS pipe P51 links to each other with the grid of PMOS pipe P43, and drain electrode links to each other with the drain electrode of NMOS pipe N52 and the output of operational amplifier (26), and source electrode meets reference potential VCC; The source ground of NMOS pipe N52, grid links to each other with the source electrode of NMOS pipe N48.

5, a kind of TTL according to claim 1 and CMOS compatible input buffer is characterized in that: described input buffer (4) comprises input inverter (5), second level input inverter (6) and third level input inverter (7); Input inverter (5) receives outside input signal, adjusts self overturn point according to the difference of signal type, for input signal provides maximum noise margin; Second level input inverter (6) receives the output signal of input inverter (5), produces a low level and be 0, high value is the output signal of VCC-VTH, generation dc power when avoiding receiving the TTL input signal.Third level input inverter (7) receives the output signal of second level input inverter (6), and the value VCC-VTH of input high level is compensated to reference potential VCC.

6, a kind of TTL according to claim 5 and CMOS compatible input buffer, it is characterized in that: described second level input inverter (6) comprises PMOS pipe P13, P15 and NMOS pipe N14, the grid of NMOS pipe N14 links to each other as the input of second level input inverter (6) with the grid of PMOS pipe P13, the drain electrode of NMOS pipe N14 links to each other as the output of second level input inverter (6) with the drain electrode of PMOS pipe P13, the source ground of NMOS pipe N14, the source electrode of PMOS pipe P13 links to each other with the drain and gate of PMOS pipe P15, and the source electrode of PMOS pipe P15 meets reference potential VCC.

7, a kind of TTL according to claim 1 and CMOS compatible input buffer, it is characterized in that: described third level input inverter (7) comprises PMOS pipe P30, P32 and NMOS pipe N31, the grid of NMOS pipe N31 links to each other with the grid of PMOS pipe P30, input as third level input inverter (7), the drain electrode of NMOS pipe N31 links to each other as the output of third level input inverter (7) with the drain electrode of PMOS pipe P30, the source ground of NMOS pipe N31, the source electrode of PMOS pipe P30 meets reference potential VCC; The grid of PMOS pipe P32 connects the output of third level input inverter (7), and drain electrode connects the input of third level input inverter (7), and source electrode meets reference potential VCC.

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