CN101271879A - Element-mounting board and semiconductor module - Google Patents
Element-mounting board and semiconductor module Download PDFInfo
- Publication number
- CN101271879A CN101271879A CNA2007101617808A CN200710161780A CN101271879A CN 101271879 A CN101271879 A CN 101271879A CN A2007101617808 A CNA2007101617808 A CN A2007101617808A CN 200710161780 A CN200710161780 A CN 200710161780A CN 101271879 A CN101271879 A CN 101271879A
- Authority
- CN
- China
- Prior art keywords
- pair
- electrode
- wiring
- signal
- mounting substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides an element mounting board that is superior in differential signal transmission characteristics, as well as is small-sized. The element-mounting board includes a wiring layer 8, signal wires 2a and 3a which are disposed mutually facing and parallel on conductive layers 2 and 3, a pair of pad electrodes 5a and 5b formed on the upper surface of the wiring layer 8, a pair of pad electrodes 7a and 7b disposed on the lower surface of the wiring layer 8, conductive portions 1b, 4b and 6b formed penetrating through each insulating layer and making electrical connections between the lower and upper conductive layers, a circuit element 9 mounted on the upper surface of the wiring layer 8; and a pair of signal electrodes 9a and 9b which are disposed on the circuit element 9 and connected via a pair of pad electrodes 5a and 5b, as well as, conductive materials 10a and 10b.; Furthermore, the board is constituted of a pair of differential transmission lines of equal length, formed by a line from the pad electrode 5a to the pad electrode 7a via the signal wire 2a, and the line from the pad electrode 5b to the pad electrode 7b via the signal wire 3a.
Description
Technical field
The present invention relates to element mounting substrate, particularly relate to element mounting substrate with differential transmission circuit.
Background technology
Along with the high speed of the conversion speed of the circuit arrangement that is used for electronic equipment and transmission speed etc.,, change the differential transmission mode that adopts into from existing single-ended transmission mode as transfer of data.The differential transmission mode is to produce positive phase signals and this two phase signals of inversion signal from a signal, uses two signal line to carry out transmission manner.In this mode, because electromagnetic coupled between the holding wire of positive phase signals and inversion signal is so two-phase holding wire and signal code each other in the relation of backhaul current path, are compared with existing single-ended transmission mode, can reduce the electromagnetic radiation noise of differential mode, and can high-speed transfer.
In recent years, along with miniaturization, the densification of circuit arrangement, the wiring substrate of forming circuit device also requires its small sizeization.But, when adopting the differential transmission mode, signal demand two signal line, therefore, the distribution of the signal relation that forms on the wiring substrate becomes 2 times, thereby compares with existing single-ended transmission mode, the problem that exists the wiring efficiency on the wiring substrate to worsen.For overcoming such problem, and propose by stacked under the state of two signal line with holding wire toward each other configuration abreast carry out the method (for example with reference to patent documentation 1) of differential transmission.
In patent documentation 1 in the disclosed wiring substrate, with two signal wirings (holding wire) in wiring substrate inside laminated configuration abreast in opposite directions, and respectively this two signal line is connected with the connection pads that is formed at the wiring substrate the superiors (electrode pad) via imbedding path.And then two integrated circuit (IC) chip (circuit element) are equipped on the superiors of wiring substrate and it is connected to each other via such connection pads.
Patent documentation 1: the spy opens the 2001-210959 communique
But, adopt at the circuit arrangement (element mounting substrate) of reality under the situation of holding wire of transmission differential signal, for guaranteeing the positive phase signals that differential lines is internal and the electrical equivalent of inversion signal, and two transmission line integral body that need to contain holding wire are made as isometric circuit.But, in above-mentioned wiring substrate, because the line length (passage depth) of imbedding path is different on two signal line, so contain the isometric property inefficacy of the integral body of holding wire, not the matching of the differential impedance that generation brings thus.Therefore, have reflecting background and produce, and the circuit element on the wiring substrate produces the problem points of misoperation.
Summary of the invention
The present invention proposes in view of described problem, and its purpose is, the element mounting substrate of the good and miniaturization of a kind of transmission characteristic of differential wave is provided.
For solving above-mentioned problem, the invention provides a kind of element mounting substrate, it is characterized in that, possess: with conductive layer and insulating barrier interaction cascading a plurality of wiring layers, be located at a pair of first electrode of a side interarea of wiring layer, be located on the different conductive layer in the wiring layer and the signal wiring that disposes abreast toward each other, be located at a pair of second electrode of the spirit one side interarea of wiring layer, connect insulating barrier setting and will be between first electrode and the signal wiring and the conductor portion that is electrically connected respectively between the signal wiring and second electrode, constitute isometric pair of differential transmission line by first circuit from first electrode, one side to described second electrode, one side and second circuit from the opposite side of first electrode to the opposite side of second electrode.
According to the present invention, in wiring layer, signal wiring toward each other abreast under the state of laminated configuration, can be made as a pair of isometric differential transmission circuit with first electrode of element mounting substrate and two circuits via such signal wiring between second electrode.Therefore, can make the element mounting substrate that can correctly transmit the signal of regulation and make the circuit element operate as normal of lift-launch.In addition, and in same level, the situation of signal wiring configured in parallel is compared, but therefore the occupied area of eliminating tolerancing signal distribution, can realize having the miniaturization of the element mounting substrate of sort signal distribution.
In the above-described configuration, has following feature, possess element mounting substrate and be located at circuit element on the side interarea of wiring layer of element mounting substrate, the a pair of signal electrode of circuit element is electrically connected respectively with a pair of first electrode, and a pair of second electrode is worked as outside extraction electrode.Thus, can with from the signal of the regulation of the circuit element that is equipped on element mounting substrate accurately and at high speed to external transmission.
According to the present invention, provide the element mounting substrate of the good and miniaturization of the transmission characteristic of signal.
Description of drawings
Fig. 1 is the plane graph of the structure of expression element mounting substrate of first embodiment of the invention and semiconductor module;
Fig. 2 (A), (B) are along the element mounting substrate of X-X line among Fig. 1 and Y-Y line and the profile of semiconductor module;
Fig. 3 is the plane graph of the structure of expression element mounting substrate of second embodiment of the invention and semiconductor module;
Fig. 4 (A), (B) are along the element mounting substrate of X-X line among Fig. 3 and Y-Y line and the profile of semiconductor module;
Fig. 5 is the plane graph of the structure of expression element mounting substrate of third embodiment of the invention and semiconductor module;
Fig. 6 (A), (B) are along the element mounting substrate of X-X line among Fig. 5 and Y-Y line and the profile of semiconductor module;
Fig. 7 represents that the 4th embodiment's installs the ideograph of the installment state of semiconductor module to motherboard;
Fig. 8 represents that the 5th embodiment's installs the ideograph of the installment state of semiconductor module to motherboard.
Description of symbols
1 insulating barrier
The 1a connecting hole
The 1b conductor portion
2 conductive layers
The 2a signal wiring
2b path composition surface
3 conductive layers
The 3a signal wiring
3b path composition surface
4 insulating barriers
The 4a connecting hole
The 4b conductor portion
5 conductive layers
The 5a pad electrode
The 5b pad electrode
6 insulating barriers
The 6a connecting hole
The 6b conductor portion
7 conductive layers
The 7a pad electrode
The 7b pad electrode
The 7c pad electrode
8 wiring layers
9 circuit elements
The 9a signal electrode
The 9b signal electrode
The 10a conductive component
The 10b conductive component
100 element mounting substrates
150 semiconductor modules
Embodiment
Below, the embodiment that the present invention is specialized with reference to description of drawings.Need to prove that in institute's drawings attached, same structural element uses identical symbol, suitably omit explanation.
(first embodiment)
Fig. 1 is the plane graph of the structure of the element mounting substrate of first embodiment of the invention and semiconductor module.Fig. 2 (A) is along the element mounting substrate of X-X line among Fig. 1 and the profile of semiconductor module, and Fig. 2 (B) is along the element mounting substrate of Y-Y line among Fig. 1 and the profile of semiconductor module.
The element mounting substrate 100 of first embodiment possesses conductive layer 2,3,5,7 and insulating barrier 1,4, the wiring layer 8 that 6 interaction cascadings are a plurality of, be located on conductive layer 2 and the conductive layer 3 and the signal wiring 2a of configured in parallel toward each other, 3a, be located at a pair of pad electrode 5a on the conductive layer 5 of wiring layer 8 upper face sides, 5b, be located at a pair of pad electrode 7a on the conductive layer 7 of sides below the wiring layer 8,7b, connect each insulating barrier setting and with the conductor portion 1b that is electrically connected between upper and lower conductive layers, 4b, 6b.In addition, the circuit element 9 that the semiconductor module 150 of first embodiment possesses element mounting substrate 100, the side interarea that is equipped on the wiring layer 8 of element mounting substrate 100 is upper face side, a pair of signal electrode 9a, the 9b that are located on this circuit element 9 and are connected with a pair of pad electrode 5a, 5b via conductive component 10a, 10b.Thus, element mounting substrate 100 and the semiconductor module 150 that possesses this substrate are by constituting pair of differential transmission line via signal wiring 32a until the circuit of pad electrode 7b until the circuit of pad electrode 7a with from pad electrode 5b via signal wiring 2a from pad electrode 5a.
Insulating barrier 1 is located between conductive layer 2 and the conductive layer 3.By insulating barrier 1 with electric insulation between conductive layer 2 and the conductive layer 3.Adopting with epoxy resin on the insulating barrier 1 is the film of principal component, and its thickness for example is about 80 μ m.At this, as the insulating barrier 1 that with epoxy resin is principal component, both can be for impregnation in the glass fibre of braiding the film of type of resin, perhaps also can be the film of the filler that in insulating barrier 1, added diameter with about 2 μ m～10 μ m degree.As this filler, aluminium oxide (Al is arranged
2O
3), silicon dioxide (SiO
2), aluminium nitride (AlN), silicon nitride (SiN), and boron nitride (BN) etc.The weight pack completeness of this filler preferably about 30%～about 80%.
Conductive layer 2 and conductive layer 3 are formed at the top and bottom of insulating barrier 1 respectively.For example adopt copper (Cu) and aluminium metals such as (Al) on conductive layer 2 and the conductive layer 3, its thickness for example is about 20 μ m.Conductive layer 2 is processed into the Wiring pattern of regulations such as signal wiring 2a and path composition surface 2b, and conductive layer 3 is processed into the Wiring pattern of regulations such as signal wiring 3a and path composition surface 3b.At this, signal wiring 2a and signal wiring 3a constitute a pair of signal wiring of transmission differential signal at the regional A of regulation toward each other and configured in parallel.
On the insulating barrier 1 between conductive layer 2 and the conductive layer 3, above it, have a connecting hole 1a towards following, in this connecting hole 1a, be formed with the conductor portion 1b that constitutes by copper etc.This conductor portion 1b is disposed at the position of regulation, and conductive layer 2 and the conductive layer 3 that is formed at the top and bottom of insulating barrier 1 is electrically connected.
Insulating barrier 4 covering conductive layer 2 and forming on insulating barrier 1.Utilize insulating barrier 4 with electric insulation between conductive layer 2 and the conductive layer 5.Insulating barrier 4 adopts the material with composition identical with insulating barrier 1, and its thickness for example is about 60 μ m.
On the insulating barrier 4 between conductive layer 2 and the insulating barrier 5, above it, have a connecting hole 4a towards following, in this connecting hole 4a, be formed with the conductor portion 4b that constitutes by copper etc.This conductor portion 4b is disposed at the position of regulation, and conductive layer 2 and conductive layer 5 that the top and bottom of insulating barrier 4 are formed are electrically connected.
Insulating barrier 6 covering conductive layer 3 and forming below insulating barrier 1.Utilize insulating barrier 6 with electric insulation between conductive layer 3 and the conductive layer 7.Insulating barrier 6 adopts the material with composition identical with insulating barrier 1, and its thickness for example is about 60 μ m.
On the insulating barrier 6 between conductive layer 3 and the insulating barrier 7, below it, have a connecting hole 6a towards top, in this connecting hole 6a, be formed with the conductor portion 6b that constitutes by copper etc.This conductor portion 6b is disposed at the position of regulation, and conductive layer 3 and conductive layer 7 that the top and bottom of insulating barrier 6 are formed are electrically connected.
In the element mounting substrate 100 of present embodiment, the length of conductor portion 4b and conductor portion 1b, 6b and with the length of conductor portion 1b, 4b and conductor portion 6b with equate, wherein, conductor portion 4b will be electrically connected electrical connection, conductor portion 6b between pad electrode 5b and the signal wiring 3a electrical connection between signal wiring 2a and the pad electrode 7a, conductor portion 1b, 4b electrical connection between pad electrode 5a and the signal wiring 2a, conductor portion 1b, 6b between signal wiring 3a and the pad electrode 7b.In addition, in the element mounting substrate 100 of present embodiment, dispose the distribution length that contains signal wiring 2a and the distribution equal in length that contains signal wiring 3a that disposes the conductive layer 3 of signal wiring 3a of the conductive layer 2 of signal wiring 2a.
According to the element mounting substrate of the as above present embodiment of explanation and possess the semiconductor module of this substrate, can obtain effect as follows.
(1) in wiring layer 8, signal wiring 2a, 3a toward each other and abreast under the state of laminated configuration, can will be made as a pair of isometric differential transmission circuit via pad electrode 5a, the 5b of element mounting substrate and two circuits of such signal wiring 2a, 3a between pad electrode 7a, the 7b.This be because, the line length from pad electrode 5a to signal wiring 2a and from pad electrode 5b poor (degree of depth that is equivalent to conductor portion 1b) of line length to signal wiring 3a by circuit to pad electrode 7a and the difference to the line length of pad electrode 7b counteracting from signal distribution 3a from signal distribution 2a.Therefore, owing to can suppress not matching of differential impedance, so the element mounting substrate that can obtain correctly transmitting the signal of regulation and can make the circuit element regular event of lift-launch.
(2) because with signal wiring 2a, 3a laminated configuration toward each other and abreast, thereby with same level abreast the situation of configuration signal distribution compare, but therefore the occupied area of eliminating tolerancing signal distribution, can realize having the miniaturization of the element mounting substrate of such signal wiring.
(3) a pair of signal electrode 9a, the 9b with circuit element 9 is electrically connected respectively with a pair of pad electrode 5a, 5b, make a pair of pad electrode 7a, 7b as being used for the signal of circuit element 9 is worked to the outside extraction electrode of external transmission, thus, can be accurately and transmit signal at high speed from the regulation that is equipped on the circuit element 9 on the element mounting substrate.
Need to prove, in the above-described embodiments, represented the example of the wiring layer 8 of four layers of structure, but the invention is not restricted to this, for example also can be applied to have the wiring layer of the above structure of two-layer structure or five layers of structure.Under this situation, by being provided with disposing toward each other and abreast between the different conductive layers of a pair of signal wiring in wiring layer, and a pair of pad electrode that will be located at a pair of pad electrode of a side interarea of wiring layer and the opposite side interarea of being located at wiring layer is connected via each conductive layer is connected the conductor portion that is provided with in the vertical direction of element mounting substrate, can enjoy same effect.
In the above-described embodiments, represent to be equipped with the element mounting substrate of circuit element 9 and the example of semiconductor module, but the invention is not restricted to this, for example also can be the element mounting substrate of the state that do not carry circuit element 9.
In the above-described embodiments, the a pair of pad electrode 7a of element mounting substrate, the example that 7b works as outside extraction electrode have been represented to make, but be not limited thereto, for example also can be below element mounting substrate other circuit element of lift-launch, and a pair of signal electrode of this circuit element is connected respectively with a pair of pad electrode 7a, the 7b of element mounting substrate.In view of the above, circuit element 9 that can be on element mounting substrate and below circuit element between accurately and the signal of transmission regulation at high speed.In addition, with the circuit element 9 of the upper face side of element mounting substrate and below under the stacked situation of circuit element of side, can be with the further miniaturization of element mounting substrate.Such embodiment is described in detail in detail below.
(second embodiment)
Fig. 3 is the plane graph of the structure of expression element mounting substrate of second embodiment of the invention and semiconductor module.Fig. 4 (A) is along the element mounting substrate of X-X line among Fig. 3 and the profile of semiconductor module, and Fig. 4 (B) is along the element mounting substrate of Y-Y line among Fig. 3 and the profile of semiconductor module.
In the semiconductor module 250, below the wiring layer 8 of element mounting substrate 200, be provided with a plurality of pad electrode 7c on the conductive layer 7 of side.The circuit element 11 of present embodiment is a BGA type IC chip, below flat encapsulation, outside input and output with pad (not shown) clathrate be arranged side by side, and this pad is connected via solder ball 12 with pad electrode 7c.In Fig. 3, semiconductor module 250 shown in Figure 4, by from pad electrode 5a via signal wiring 2a until the circuit of pad electrode 7a with constitute the pair of differential transmission line of equal length until the circuit of pad electrode 7b via signal wiring 3a from pad electrode 5b.Need to prove, also can transmit circuit the pad electrode of circuit element 9 and circuit element 11 is connected each other by the pair of differential of equal length.
(the 3rd embodiment)
Fig. 5 is the plane graph of the structure of expression element mounting substrate of third embodiment of the invention and semiconductor module.Fig. 6 (A) is along the element mounting substrate of X-X line among Fig. 5 and the profile of semiconductor module, and Fig. 6 (B) is along the element mounting substrate of Y-Y line among Fig. 5 and the profile of semiconductor module.
In the semiconductor module 350 of the 3rd embodiment, not only be equipped with the circuit element 9 of the semiconductor module 150 of first embodiment, but also on the face of the opposite side of the face that is equipped with circuit element 9, be equipped with circuit element 13.Need to prove that the element mounting substrate 300 of present embodiment is identical with the element mounting substrate 100 of first embodiment in fact, therefore, identical element uses same-sign, suitably omits explanation.
(the 4th embodiment)
In the present embodiment, the semiconductor module that will illustrate in the various embodiments described above is embedded the method that is installed on the motherboard describe.Fig. 7 represents that the 4th embodiment's installs the ideograph of the installment state of semiconductor module to motherboard.Motherboard 440 is the electronic circuit boards that are configured for constituting a plurality of parts of electronic installation stackedly.On the motherboard 440 of present embodiment, the mode that the circuit element 400 that is provided with according to a side of the element mounting substrate 400 that does not possess with stacked semiconductor module 450 is interfered is formed with through hole 420.
The isometric each other pair of differential transmission line 403 that the element mounting substrate 400 of semiconductor module 450 has the pair of differential transmission line 402 of the equal length each other that circuit element 409 and circuit element 411 is electrically connected, circuit element 409 and motherboard 440 are electrically connected.Need to prove that for ease of explanation, each differential transmission circuit 402,403 shown in Figure 7 represented by a line, but identical by the element mounting substrate that illustrates in the paired point of two distributions and the various embodiments described above.
(the 5th embodiment)
In the present embodiment, the method that the semiconductor module that will illustrate in the various embodiments described above vertically is installed on the motherboard describes.Fig. 8 represents that the 5th embodiment's installs the ideograph of the installment state of semiconductor module to motherboard.The insertion mouth 520 that the mode that is formed with the end of the semiconductor module of installing according to insertion 550 on the motherboard 540 of present embodiment and is fixed constitutes.Semiconductor module 550 to be inserted into the state that inserts in the mouth 520, contacts with the not shown electrode that is formed with the external connection terminals 522 of being located at the end on motherboard 540, fixes.
The pair of differential transmission line 504 of the equal length each other that the element mounting substrate 550 of semiconductor module 550 has the pair of differential transmission line 502,503 of the equal length each other that circuit element 509 and circuit element 511 is electrically connected, be electrically connected circuit element 509 and motherboard 540, the pair of differential transmission line 505 of the equal length each other that circuit element 511 and motherboard 540 are electrically connected.Need to prove that for ease of explanation, each differential transmission circuit 502,503,504,505 shown in Figure 8 represented by a line, but identical by the element mounting substrate that illustrates in the paired point of two distributions and the various embodiments described above.
Each above-mentioned embodiment of above reference describes the present invention, but the invention is not restricted to each above-mentioned embodiment, even also be to belong to of the present invention with the structure appropriate combination of each embodiment and displacement.In addition, based on those skilled in the art's knowledge, also can increase distortion such as various design alterations to each embodiment, the embodiment that increases this distortion also belongs to scope of the present invention.
Claims (5)
1, a kind of element mounting substrate is characterized in that, possesses:
With conductive layer and insulating barrier interaction cascading a plurality of wiring layers,
Be located at a side interarea of described wiring layer a pair of first electrode,
Be located on the different conductive layer in the described wiring layer and toward each other abreast the signal wiring of configuration,
Be located at the opposite side interarea of described wiring layer a pair of second electrode,
Connect described insulating barrier setting and will reach the conductor portion that is electrically connected respectively between described signal wiring and described second electrode between described first electrode and the described signal wiring,
Constitute isometric pair of differential transmission line by first circuit from described first electrode, one side to described second electrode, one side and second circuit from the opposite side of described first electrode to the opposite side of described second electrode.
2, element mounting substrate as claimed in claim 1, it is characterized in that, the described conductor portion of described first circuit respectively is provided with one from a side interarea towards the opposite side interarea on each insulating barrier, the described conductor portion of described second circuit respectively is provided with one from a side interarea towards the opposite side interarea on each insulating barrier.
3, a kind of element mounting substrate is characterized in that, possesses:
With conductive layer and insulating barrier interaction cascading a plurality of wiring layers,
Be located at a side interarea of described wiring layer a pair of first electrode,
Be located on the different conductive layer in the described wiring layer and toward each other abreast the signal wiring of configuration,
Be located at the opposite side interarea of described wiring layer a pair of second electrode,
Connect described insulating barrier setting and with first conductor portion that is electrically connected between one of described a pair of first electrode and described a pair of signal wiring one,
Connect described insulating barrier setting and with second conductor portion that is electrically connected between one of described a pair of signal wiring and described a pair of second electrode one,
Connect described insulating barrier setting and with the 3rd conductor portion that is electrically connected between another of another and described a pair of signal wiring of described a pair of first electrode,
Connect described insulating barrier setting and with the 4th conductor portion that is electrically connected between another of another and described a pair of second electrode of described a pair of signal wiring,
Dispose one conductive layer of described a pair of signal wiring one the distribution length that contains described a pair of signal wiring, with another another the distribution equal in length that contains described a pair of signal wiring of conductive layer that disposes described a pair of signal wiring
Perpendicular to the length sum of described first conductor portion on the direction of the interarea of wiring layer and described second conductor portion, with equate perpendicular to described the 3rd conductor portion on the direction of the interarea of wiring layer and the length sum of described the 4th conductor portion,
Constitute isometric pair of differential transmission line by first circuit from a side of described first electrode to a side of described second electrode and second circuit from the opposite side of described first electrode to the opposite side of described second electrode.
4, a kind of semiconductor module is characterized in that, possesses:
As each described element mounting substrate in the claim 1～3 and as described in element mounting substrate as described in the circuit element that is provided with on the side interarea of wiring layer,
The a pair of signal electrode of described circuit element is electrically connected respectively with described a pair of first electrode, and described a pair of second electrode works as outside extraction electrode.
5, a kind of semiconductor module is characterized in that, possesses:
As each described element mounting substrate in the claim 1～3, as described in element mounting substrate as described in first circuit element that is provided with on the side interarea of wiring layer and as described in element mounting substrate as described in the second circuit element that is provided with on the opposite side interarea of wiring layer
The a pair of signal electrode of described first circuit element is electrically connected respectively with described a pair of first electrode, a pair of signal electrode of described second circuit element is electrically connected respectively with described a pair of second electrode.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006266887 | 2006-09-29 | ||
| JP266887/06 | 2006-09-29 | ||
| JP226726/07 | 2007-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101271879A true CN101271879A (en) | 2008-09-24 |
Family
ID=40005704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007101617808A Pending CN101271879A (en) | 2006-09-29 | 2007-09-26 | Element-mounting board and semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101271879A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753490B (en) * | 2008-12-18 | 2013-03-27 | 株式会社电装 | Sensor device for occupant protection system |
| CN109819581A (en) * | 2017-11-20 | 2019-05-28 | 鹏鼎控股(深圳)股份有限公司 | Radio frequency circuit board and preparation method thereof |
| CN112703593A (en) * | 2019-08-23 | 2021-04-23 | 日本特殊陶业株式会社 | Wiring board |
-
2007
- 2007-09-26 CN CNA2007101617808A patent/CN101271879A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101753490B (en) * | 2008-12-18 | 2013-03-27 | 株式会社电装 | Sensor device for occupant protection system |
| CN109819581A (en) * | 2017-11-20 | 2019-05-28 | 鹏鼎控股(深圳)股份有限公司 | Radio frequency circuit board and preparation method thereof |
| CN112703593A (en) * | 2019-08-23 | 2021-04-23 | 日本特殊陶业株式会社 | Wiring board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6777796B2 (en) | Stacked semiconductor chips on a wiring board | |
| US6717251B2 (en) | Stacked type semiconductor device | |
| KR100731235B1 (en) | Semiconductor device | |
| US8921995B1 (en) | Integrated circuit package including a three-dimensional fan-out/fan-in signal routing | |
| US6819001B2 (en) | Interposer, interposer package and device assembly employing the same | |
| KR20010066905A (en) | Semiconductor device | |
| US20090146314A1 (en) | Semiconductor Device | |
| CN110911380B (en) | Electronic equipment | |
| US20080078571A1 (en) | Device mounting board and semiconductor module | |
| CN100573858C (en) | Chip packing-body | |
| US7365438B2 (en) | Semiconductor device with semiconductor components connected to one another | |
| CN101271879A (en) | Element-mounting board and semiconductor module | |
| CN114334889A (en) | Electronic package and bearing substrate thereof | |
| CN106067447A (en) | Semiconductor package assembly and a manufacturing method thereof | |
| US7705445B2 (en) | Semiconductor package with low and high-speed signal paths | |
| KR100725517B1 (en) | multi-layered circuit substrate having bonding pads and ball lands arranged on two or more layers, and semiconductor package structure using the same | |
| JPH04290258A (en) | Multichip module | |
| KR20090082844A (en) | Stack chip package structure and manufacturing method thereof | |
| KR102345061B1 (en) | Semiconductor package | |
| JP4388834B2 (en) | Semiconductor device | |
| CN101488483A (en) | Semiconductor chip encapsulation structure | |
| CN112928074A (en) | Semiconductor device package and method of manufacturing the same | |
| CN115104183A (en) | Circuit structure and electronic device | |
| JP2009231328A (en) | Electronic module | |
| KR20070069751A (en) | Stack packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20080924 |
|
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |